build-imxboard.git

BSP:IGKBoard-All: Move BSP scripts to bsp folder

guowenxue

2024-09-26 2b179f80693db10cb5a93ee649917ae6988feaf2

commit \| author \| age
435024	1	diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
G	2	index 709fdaec..00d6d30c 100644
	3	--- a/arch/arm/dts/Makefile
	4	+++ b/arch/arm/dts/Makefile
	5	@@ -1002,6 +1002,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
	6	imx8mp-evk.dtb \
	7	imx8mp-phyboard-pollux-rdk.dtb \
	8	imx8mp-verdin.dtb \
	9	+ gauguin-imx8mp.dtb \
	10	imx8mq-pico-pi.dtb \
	11	imx8mq-kontron-pitx-imx8m.dtb
	12
	13	diff --git a/arch/arm/dts/gauguin-imx8mp-u-boot.dtsi b/arch/arm/dts/gauguin-imx8mp-u-boot.dtsi
	14	new file mode 100644
	15	index 00000000..922b5d6d
	16	--- /dev/null
	17	+++ b/arch/arm/dts/gauguin-imx8mp-u-boot.dtsi
	18	@@ -0,0 +1,234 @@
	19	+// SPDX-License-Identifier: GPL-2.0+
	20	+/*
	21	+ * Copyright 2019, 2021 NXP
	22	+ */
	23	+#include "imx8mp-sec-def.h"
	24	+
	25	+#include "imx8mp-u-boot.dtsi"
	26	+
	27	+/ {
	28	+ wdt-reboot {
	29	+ compatible = "wdt-reboot";
	30	+ wdt = <&wdog1>;
	31	+ u-boot,dm-spl;
	32	+ };
	33	+ firmware {
	34	+ optee {
	35	+ compatible = "linaro,optee-tz";
	36	+ method = "smc";
	37	+ };
	38	+ };
	39	+
	40	+ mcu_rdc {
	41	+ compatible = "imx8m,mcu_rdc";
	42	+ /* rdc config when MCU starts
	43	+ * master
	44	+ * SDMA3p --> domain 1
	45	+ * SDMA3b --> domian 1
	46	+ * SDMA3_SPBA2 --> domian 1
	47	+ * peripheral:
	48	+ * SAI3 --> Only Domian 1 can access
	49	+ * UART4 --> Only Domian 1 can access
	50	+ * GPT1 --> Only Domian 1 can access
	51	+ * SDMA3 --> Only Domian 1 can access
	52	+ * I2C3 --> Only Domian 1 can access
	53	+ * memory:
	54	+ * TCM --> Only Domian 1 can access (0x7E0000~0x81FFFF)
	55	+ * DDR --> Only Domian 1 can access (0x80000000~0x81000000)
	56	+ * end.
	57	+ */
	58	+ start-config = <
	59	+ RDC_MDA RDC_MDA_SDMA3p DID1 0x0 0x0
	60	+ RDC_MDA RDC_MDA_ENET1_TX DID1 0x0 0x0
	61	+ RDC_MDA RDC_MDA_ENET1_RX DID1 0x0 0x0
	62	+ RDC_MDA RDC_MDA_SDMA3b DID1 0x0 0x0
	63	+ RDC_MDA RDC_MDA_SDMA3_SPBA2 DID1 0x0 0x0
	64	+ RDC_PDAP RDC_PDAP_ENET1 PDAP_D0D1_ACCESS 0x0 0x0
	65	+ RDC_PDAP RDC_PDAP_SAI3 PDAP_D1_ACCESS 0x0 0x0
	66	+ RDC_PDAP RDC_PDAP_UART4 PDAP_D1_ACCESS 0x0 0x0
	67	+ RDC_PDAP RDC_PDAP_GPT1 PDAP_D1_ACCESS 0x0 0x0
	68	+ RDC_PDAP RDC_PDAP_SDMA3 PDAP_D1_ACCESS 0x0 0x0
	69	+ RDC_PDAP RDC_PDAP_I2C3 PDAP_D1_ACCESS 0x0 0x0
	70	+ RDC_MEM_REGION 22 TCM_START TCM_END MEM_D1_ACCESS
	71	+ RDC_MEM_REGION 39 M4_DDR_START M4_DDR_END MEM_D1_ACCESS
	72	+ 0x0 0x0 0x0 0x0 0x0
	73	+ >;
	74	+ /* rdc config when MCU stops
	75	+ * memory:
	76	+ * TCM --> domain 0/1 can access (0x7E0000~0x81FFFF)
	77	+ * DDR --> domain 0/1 can access (0x80000000~0x81000000)
	78	+ * end.
	79	+ */
	80	+ stop-config = <
	81	+ RDC_MEM_REGION 22 TCM_START TCM_END MEM_D0D1_ACCESS
	82	+ RDC_MEM_REGION 39 M4_DDR_START M4_DDR_END MEM_D0D1_ACCESS
	83	+ 0x0 0x0 0x0 0x0 0x0
	84	+ >;
	85	+ };
	86	+};
	87	+
	88	+&pinctrl_uart2 {
	89	+ u-boot,dm-spl;
	90	+};
	91	+
	92	+&pinctrl_usdhc3 {
	93	+ u-boot,dm-spl;
	94	+};
	95	+
	96	+&gpio1 {
	97	+ u-boot,dm-spl;
	98	+};
	99	+
	100	+&gpio2 {
	101	+ u-boot,dm-spl;
	102	+};
	103	+
	104	+&gpio3 {
	105	+ u-boot,dm-spl;
	106	+};
	107	+
	108	+&gpio4 {
	109	+ u-boot,dm-spl;
	110	+};
	111	+
	112	+&gpio5 {
	113	+ u-boot,dm-spl;
	114	+};
	115	+
	116	+&uart2 {
	117	+ u-boot,dm-spl;
	118	+};
	119	+
	120	+&crypto {
	121	+ u-boot,dm-spl;
	122	+};
	123	+
	124	+&sec_jr0 {
	125	+ u-boot,dm-spl;
	126	+};
	127	+
	128	+&sec_jr1 {
	129	+ u-boot,dm-spl;
	130	+};
	131	+
	132	+&sec_jr2 {
	133	+ u-boot,dm-spl;
	134	+};
	135	+
	136	+&i2c1 {
	137	+ u-boot,dm-spl;
	138	+};
	139	+
	140	+&i2c2 {
	141	+ u-boot,dm-spl;
	142	+};
	143	+
	144	+&i2c3 {
	145	+ u-boot,dm-spl;
	146	+};
	147	+
	148	+&pinctrl_i2c1 {
	149	+ u-boot,dm-spl;
	150	+};
	151	+
	152	+&pinctrl_i2c1_gpio {
	153	+ u-boot,dm-spl;
	154	+};
	155	+
	156	+&usdhc1 {
	157	+ u-boot,dm-spl;
	158	+ assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
	159	+ assigned-clock-rates = <400000000>;
	160	+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
	161	+};
	162	+
	163	+&usdhc2 {
	164	+ u-boot,dm-spl;
	165	+ sd-uhs-sdr104;
	166	+ sd-uhs-ddr50;
	167	+ assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
	168	+ assigned-clock-rates = <400000000>;
	169	+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
	170	+};
	171	+
	172	+&usdhc3 {
	173	+ u-boot,dm-spl;
	174	+ mmc-hs400-1_8v;
	175	+ mmc-hs400-enhanced-strobe;
	176	+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
	177	+ assigned-clock-rates = <400000000>;
	178	+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
	179	+};
	180	+
	181	+&wdog1 {
	182	+ u-boot,dm-spl;
	183	+};
	184	+
	185	+&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
	186	+ u-boot,dm-spl;
	187	+};
	188	+
	189	+&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
	190	+ u-boot,dm-spl;
	191	+};
	192	+
	193	+&pinctrl_pmic {
	194	+ u-boot,dm-spl;
	195	+};
	196	+
	197	+&eqos {
	198	+ compatible = "fsl,imx-eqos";
	199	+ /delete-property/ assigned-clocks;
	200	+ /delete-property/ assigned-clock-parents;
	201	+ /delete-property/ assigned-clock-rates;
	202	+};
	203	+
	204	+&ethphy0 {
	205	+ reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
	206	+ reset-assert-us = <15000>;
	207	+ reset-deassert-us = <100000>;
	208	+};
	209	+
	210	+&fec {
	211	+ phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
	212	+ phy-reset-duration = <15>;
	213	+ phy-reset-post-delay = <100>;
	214	+};
	215	+
	216	+&flexspi {
	217	+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
	218	+};
	219	+
	220	+&lcdif1 {
	221	+ /delete-property/ assigned-clocks;
	222	+ /delete-property/ assigned-clock-parents;
	223	+ /delete-property/ assigned-clock-rates;
	224	+};
	225	+
	226	+&mipi_dsi {
	227	+ /delete-property/ assigned-clocks;
	228	+ /delete-property/ assigned-clock-parents;
	229	+ /delete-property/ assigned-clock-rates;
	230	+};
	231	+
	232	+&usb3_0 {
	233	+ /delete-property/ power-domains;
	234	+};
	235	+
	236	+&usb3_1 {
	237	+ /delete-property/ power-domains;
	238	+};
	239	+
	240	+&usb_dwc3_0 {
	241	+ compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
	242	+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
	243	+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
	244	+ assigned-clock-rates = <400000000>;
	245	+};
	246	+
	247	+&usb_dwc3_1 {
	248	+ compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
	249	+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
	250	+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
	251	+ assigned-clock-rates = <400000000>;
	252	+};
	253	diff --git a/arch/arm/dts/gauguin-imx8mp.dts b/arch/arm/dts/gauguin-imx8mp.dts
	254	new file mode 100644
	255	index 00000000..2a48b4f6
	256	--- /dev/null
	257	+++ b/arch/arm/dts/gauguin-imx8mp.dts
	258	@@ -0,0 +1,449 @@
	259	+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	260	+/*
	261	+ * Copyright 2019 NXP
	262	+ */
	263	+
	264	+/dts-v1/;
	265	+
	266	+#include <dt-bindings/usb/pd.h>
	267	+#include "imx8mp.dtsi"
	268	+
	269	+/ {
	270	+ model = "ZhiTu GauGuin Board - imx8mp";
	271	+ compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
	272	+
	273	+ chosen {
	274	+ bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
	275	+ stdout-path = &uart2;
	276	+ };
	277	+
	278	+ gpio-leds {
	279	+ compatible = "gpio-leds";
	280	+ pinctrl-names = "default";
	281	+ pinctrl-0 = <&pinctrl_gpio_led>;
	282	+
	283	+ led-red {
	284	+ label = "red:status";
	285	+ gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
	286	+ default-state = "off";
	287	+ };
	288	+
	289	+ led-green {
	290	+ label = "green:status";
	291	+ gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
	292	+ default-state = "off";
	293	+ };
	294	+ };
	295	+
	296	+ memory@40000000 {
	297	+ device_type = "memory";
	298	+ reg = <0x0 0x40000000 0 0xc0000000>,
	299	+ <0x1 0x00000000 0 0xc0000000>;
	300	+ };
	301	+};
	302	+
	303	+/eth0 T1/
	304	+&eqos {
	305	+ pinctrl-names = "default";
	306	+ pinctrl-0 = <&pinctrl_eqos>;
	307	+ phy-mode = "rgmii-id";
	308	+ phy-handle = <&ethphy0>;
	309	+ status = "okay";
	310	+
	311	+ mdio {
	312	+ compatible = "snps,dwmac-mdio";
	313	+ #address-cells = <1>;
	314	+ #size-cells = <0>;
	315	+
	316	+ ethphy0: ethernet-phy@1 {
	317	+ compatible = "ethernet-phy-ieee802.3-c22";
	318	+ reg = <1>;
	319	+ eee-broken-1000t;
	320	+ };
	321	+ };
	322	+};
	323	+
	324	+/eth1 T2/
	325	+&fec {
	326	+ pinctrl-names = "default";
	327	+ pinctrl-0 = <&pinctrl_fec>;
	328	+ phy-mode = "rgmii-id";
	329	+ phy-handle = <&ethphy1>;
	330	+ fsl,magic-packet;
	331	+ status = "okay";
	332	+
	333	+ mdio {
	334	+ #address-cells = <1>;
	335	+ #size-cells = <0>;
	336	+
	337	+ ethphy1: ethernet-phy@1 {
	338	+ compatible = "ethernet-phy-ieee802.3-c22";
	339	+ reg = <1>;
	340	+ eee-broken-1000t;
	341	+ };
	342	+ };
	343	+};
	344	+
	345	+&flexspi {
	346	+ pinctrl-names = "default";
	347	+ pinctrl-0 = <&pinctrl_flexspi0>;
	348	+ status = "okay";
	349	+
	350	+ flash0: mt25qu256aba@0 {
	351	+ reg = <0>;
	352	+ #address-cells = <1>;
	353	+ #size-cells = <1>;
	354	+ compatible = "jedec,spi-nor";
	355	+ spi-max-frequency = <80000000>;
	356	+ spi-tx-bus-width = <4>;
	357	+ spi-rx-bus-width = <4>;
	358	+ };
	359	+};
	360	+
	361	+&i2c1 {
	362	+ clock-frequency = <400000>;
	363	+ pinctrl-names = "default", "gpio";
	364	+ pinctrl-0 = <&pinctrl_i2c1>;
	365	+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
	366	+ scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
	367	+ sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
	368	+ status = "okay";
	369	+
	370	+ pmic: pca9450@25 {
	371	+ reg = <0x25>;
	372	+ compatible = "nxp,pca9450c";
	373	+ /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
	374	+ pinctrl-0 = <&pinctrl_pmic>;
	375	+ gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
	376	+
	377	+ regulators {
	378	+ #address-cells = <1>;
	379	+ #size-cells = <0>;
	380	+
	381	+ pca9450,pmic-buck2-uses-i2c-dvs;
	382	+ /* Run/Standby voltage */
	383	+ pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
	384	+
	385	+ buck1_reg: regulator@0 {
	386	+ reg = <0>;
	387	+ regulator-compatible = "buck1";
	388	+ regulator-min-microvolt = <600000>;
	389	+ regulator-max-microvolt = <2187500>;
	390	+ regulator-boot-on;
	391	+ regulator-always-on;
	392	+ regulator-ramp-delay = <3125>;
	393	+ };
	394	+
	395	+ buck2_reg: regulator@1 {
	396	+ reg = <1>;
	397	+ regulator-compatible = "buck2";
	398	+ regulator-min-microvolt = <600000>;
	399	+ regulator-max-microvolt = <2187500>;
	400	+ regulator-boot-on;
	401	+ regulator-always-on;
	402	+ regulator-ramp-delay = <3125>;
	403	+ };
	404	+
	405	+ buck4_reg: regulator@3 {
	406	+ reg = <3>;
	407	+ regulator-compatible = "buck4";
	408	+ regulator-min-microvolt = <600000>;
	409	+ regulator-max-microvolt = <3400000>;
	410	+ regulator-boot-on;
	411	+ regulator-always-on;
	412	+ };
	413	+
	414	+ buck5_reg: regulator@4 {
	415	+ reg = <4>;
	416	+ regulator-compatible = "buck5";
	417	+ regulator-min-microvolt = <600000>;
	418	+ regulator-max-microvolt = <3400000>;
	419	+ regulator-boot-on;
	420	+ regulator-always-on;
	421	+ };
	422	+
	423	+ buck6_reg: regulator@5 {
	424	+ reg = <5>;
	425	+ regulator-compatible = "buck6";
	426	+ regulator-min-microvolt = <600000>;
	427	+ regulator-max-microvolt = <3400000>;
	428	+ regulator-boot-on;
	429	+ regulator-always-on;
	430	+ };
	431	+
	432	+ ldo1_reg: regulator@6 {
	433	+ reg = <6>;
	434	+ regulator-compatible = "ldo1";
	435	+ regulator-min-microvolt = <1600000>;
	436	+ regulator-max-microvolt = <3300000>;
	437	+ regulator-boot-on;
	438	+ regulator-always-on;
	439	+ };
	440	+
	441	+ ldo2_reg: regulator@7 {
	442	+ reg = <7>;
	443	+ regulator-compatible = "ldo2";
	444	+ regulator-min-microvolt = <800000>;
	445	+ regulator-max-microvolt = <1150000>;
	446	+ regulator-boot-on;
	447	+ regulator-always-on;
	448	+ };
	449	+
	450	+ ldo3_reg: regulator@8 {
	451	+ reg = <8>;
	452	+ regulator-compatible = "ldo3";
	453	+ regulator-min-microvolt = <800000>;
	454	+ regulator-max-microvolt = <3300000>;
	455	+ regulator-boot-on;
	456	+ regulator-always-on;
	457	+ };
	458	+
	459	+ ldo4_reg: regulator@9 {
	460	+ reg = <9>;
	461	+ regulator-compatible = "ldo4";
	462	+ regulator-min-microvolt = <800000>;
	463	+ regulator-max-microvolt = <3300000>;
	464	+ regulator-boot-on;
	465	+ regulator-always-on;
	466	+ };
	467	+
	468	+ ldo5_reg: regulator@10 {
	469	+ reg = <10>;
	470	+ regulator-compatible = "ldo5";
	471	+ regulator-min-microvolt = <1800000>;
	472	+ regulator-max-microvolt = <3300000>;
	473	+ };
	474	+ };
	475	+ };
	476	+};
	477	+
	478	+&i2c2 {
	479	+ clock-frequency = <400000>;
	480	+ pinctrl-names = "default";
	481	+ pinctrl-0 = <&pinctrl_i2c2>;
	482	+ status = "okay";
	483	+};
	484	+
	485	+&i2c3 {
	486	+ clock-frequency = <100000>;
	487	+ pinctrl-names = "default";
	488	+ pinctrl-0 = <&pinctrl_i2c3>;
	489	+ status = "okay";
	490	+};
	491	+
	492	+&snvs_pwrkey {
	493	+ status = "okay";
	494	+};
	495	+
	496	+&uart2 {
	497	+ /* console */
	498	+ pinctrl-names = "default";
	499	+ pinctrl-0 = <&pinctrl_uart2>;
	500	+ status = "okay";
	501	+};
	502	+
	503	+&usb3_phy0 {
	504	+ fsl,phy-tx-vref-tune = <0xe>;
	505	+ fsl,phy-tx-preemp-amp-tune = <3>;
	506	+ fsl,phy-tx-vboost-level = <5>;
	507	+ fsl,phy-comp-dis-tune = <7>;
	508	+ fsl,pcs-tx-deemph-3p5db = <0x21>;
	509	+ fsl,phy-pcs-tx-swing-full = <0x7f>;
	510	+ status = "okay";
	511	+};
	512	+
	513	+&usb3_0 {
	514	+ status = "okay";
	515	+};
	516	+
	517	+&usb_dwc3_0 {
	518	+ dr_mode = "otg";
	519	+ hnp-disable;
	520	+ srp-disable;
	521	+ adp-disable;
	522	+ usb-role-switch;
	523	+ role-switch-default-mode = "none";
	524	+ pinctrl-names = "default";
	525	+ pinctrl-0 = <&pinctrl_usb0_id_grp>;/add otg control gpio/
	526	+ status = "okay";
	527	+};
	528	+
	529	+&usdhc3 {
	530	+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
	531	+ pinctrl-0 = <&pinctrl_usdhc3>;
	532	+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	533	+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	534	+ bus-width = <8>;
	535	+ non-removable;
	536	+ status = "okay";
	537	+};
	538	+
	539	+&wdog1 {
	540	+ pinctrl-names = "default";
	541	+ pinctrl-0 = <&pinctrl_wdog>;
	542	+ fsl,ext-reset-output;
	543	+ status = "okay";
	544	+};
	545	+
	546	+&iomuxc {
	547	+ pinctrl-names = "default";
	548	+
	549	+ pinctrl_eqos: eqosgrp {/T1/
	550	+ fsl,pins = <
	551	+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
	552	+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
	553	+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
	554	+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
	555	+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
	556	+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
	557	+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
	558	+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
	559	+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
	560	+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
	561	+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
	562	+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
	563	+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
	564	+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
	565	+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
	566	+ >;
	567	+ };
	568	+
	569	+ pinctrl_fec: fecgrp {/T2/
	570	+ fsl,pins = <
	571	+ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
	572	+ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
	573	+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
	574	+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
	575	+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
	576	+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
	577	+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
	578	+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
	579	+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
	580	+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
	581	+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
	582	+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
	583	+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
	584	+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
	585	+ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
	586	+ >;
	587	+ };
	588	+
	589	+ pinctrl_flexspi0: flexspi0grp {
	590	+ fsl,pins = <
	591	+ MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
	592	+ MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
	593	+ MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
	594	+ MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
	595	+ MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
	596	+ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
	597	+ >;
	598	+ };
	599	+
	600	+ pinctrl_gpio_led: gpioledgrp {
	601	+ fsl,pins = <
	602	+ MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x19
	603	+ MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x19
	604	+ >;
	605	+ };
	606	+
	607	+ pinctrl_i2c1: i2c1grp {
	608	+ fsl,pins = <
	609	+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
	610	+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
	611	+ >;
	612	+ };
	613	+
	614	+ pinctrl_i2c2: i2c2grp {
	615	+ fsl,pins = <
	616	+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
	617	+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
	618	+ >;
	619	+ };
	620	+
	621	+ pinctrl_i2c3: i2c3grp {
	622	+ fsl,pins = <
	623	+ MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
	624	+ MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
	625	+ >;
	626	+ };
	627	+
	628	+ pinctrl_i2c1_gpio: i2c1grp-gpio {
	629	+ fsl,pins = <
	630	+ MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
	631	+ MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
	632	+ >;
	633	+ };
	634	+
	635	+ pinctrl_pmic: pmicirq {
	636	+ fsl,pins = <
	637	+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
	638	+ >;
	639	+ };
	640	+
	641	+ pinctrl_uart2: uart2grp {
	642	+ fsl,pins = <
	643	+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
	644	+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
	645	+ >;
	646	+ };
	647	+
	648	+ pinctrl_usb0_id_grp: usb0grp{
	649	+ fsl,pins = <
	650	+ MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x1c4
	651	+ >;
	652	+ };
	653	+
	654	+ pinctrl_usdhc3: usdhc3grp {
	655	+ fsl,pins = <
	656	+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
	657	+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
	658	+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
	659	+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
	660	+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
	661	+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
	662	+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
	663	+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
	664	+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
	665	+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
	666	+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
	667	+ >;
	668	+ };
	669	+
	670	+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
	671	+ fsl,pins = <
	672	+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
	673	+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
	674	+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
	675	+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
	676	+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
	677	+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
	678	+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
	679	+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
	680	+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
	681	+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
	682	+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
	683	+ >;
	684	+ };
	685	+
	686	+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
	687	+ fsl,pins = <
	688	+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
	689	+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
	690	+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
	691	+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
	692	+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
	693	+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
	694	+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
	695	+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
	696	+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
	697	+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
	698	+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
	699	+ >;
	700	+ };
	701	+
	702	+ pinctrl_wdog: wdoggrp {
	703	+ fsl,pins = <
	704	+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
	705	+ >;
	706	+ };
	707	+};
	708	diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
	709	index a225a978..860f0003 100644
	710	--- a/arch/arm/mach-imx/imx8m/Kconfig
	711	+++ b/arch/arm/mach-imx/imx8m/Kconfig
	712	@@ -241,6 +241,16 @@ config TARGET_IMX8MP_EVK
	713	select ARCH_MISC_INIT
	714	select SPL_CRYPTO if SPL
	715
	716	+config TARGET_GAUGUIN_IMX8MP
	717	+ bool "ZhiTu IMX8MP LPDDR4 GauGuin Board"
	718	+ select IMX8MP
	719	+ select SUPPORT_SPL
	720	+ select IMX8M_LPDDR4
	721	+ select FSL_CAAM
	722	+ select FSL_BLOB
	723	+ select ARCH_MISC_INIT
	724	+ select SPL_CRYPTO if SPL
	725	+
	726	config TARGET_IMX8MP_DDR4_EVK
	727	bool "imx8mp DDR4 EVK board"
	728	select IMX8MP
	729	@@ -366,5 +376,6 @@ source "board/technexion/pico-imx8mq/Kconfig"
	730	source "board/variscite/imx8mn_var_som/Kconfig"
	731	source "board/toradex/verdin-imx8mm/Kconfig"
	732	source "board/toradex/verdin-imx8mp/Kconfig"
	733	+source "board/freescale/gauguin-imx8mp/Kconfig"
	734
	735	endif
	736	diff --git a/board/freescale/gauguin-imx8mp/Kconfig b/board/freescale/gauguin-imx8mp/Kconfig
	737	new file mode 100644
	738	index 00000000..a3eb059f
	739	--- /dev/null
	740	+++ b/board/freescale/gauguin-imx8mp/Kconfig
	741	@@ -0,0 +1,17 @@
	742	+if TARGET_GAUGUIN_IMX8MP \|\| TARGET_IMX8MP_DDR4_EVK
	743	+
	744	+config SYS_BOARD
	745	+ default "gauguin-imx8mp"
	746	+
	747	+config SYS_VENDOR
	748	+ default "freescale"
	749	+
	750	+config SYS_CONFIG_NAME
	751	+ default "gauguin-imx8mp"
	752	+
	753	+config IMX_CONFIG
	754	+ default "board/freescale/gauguin-imx8mp/imximage-8mp-lpddr4.cfg"
	755	+
	756	+source "board/freescale/common/Kconfig"
	757	+
	758	+endif
	759	diff --git a/board/freescale/gauguin-imx8mp/MAINTAINERS b/board/freescale/gauguin-imx8mp/MAINTAINERS
	760	new file mode 100644
	761	index 00000000..1f793c27
	762	--- /dev/null
	763	+++ b/board/freescale/gauguin-imx8mp/MAINTAINERS
	764	@@ -0,0 +1,6 @@
	765	+i.MX8MP GauGuin Board
	766	+M: Guo Wenxue <guowenxue@gmail.com>
	767	+S: Maintained
	768	+F: board/freescale/gauguin-imx8mp/
	769	+F: include/configs/gauguin-imx8mp.h
	770	+F: configs/gauguin-imx8mp_defconfig
	771	diff --git a/board/freescale/gauguin-imx8mp/Makefile b/board/freescale/gauguin-imx8mp/Makefile
	772	new file mode 100644
	773	index 00000000..30c74f9b
	774	--- /dev/null
	775	+++ b/board/freescale/gauguin-imx8mp/Makefile
	776	@@ -0,0 +1,17 @@
	777	+#
	778	+# Copyright 2019 NXP
	779	+#
	780	+# SPDX-License-Identifier: GPL-2.0+
	781	+#
	782	+
	783	+obj-y += gauguin-imx8mp.o
	784	+
	785	+ifdef CONFIG_SPL_BUILD
	786	+obj-y += spl.o
	787	+ifdef CONFIG_IMX8M_LPDDR4_FREQ0_3200MTS
	788	+obj-y += lpddr4_timing_ndm.o
	789	+else
	790	+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
	791	+obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o
	792	+endif
	793	+endif
	794	diff --git a/board/freescale/gauguin-imx8mp/ddr4_timing.c b/board/freescale/gauguin-imx8mp/ddr4_timing.c
	795	new file mode 100644
	796	index 00000000..3e3cc01b
	797	--- /dev/null
	798	+++ b/board/freescale/gauguin-imx8mp/ddr4_timing.c
	799	@@ -0,0 +1,1311 @@
	800	+/*
	801	+ * Copyright 2019 NXP
	802	+ *
	803	+ * SPDX-License-Identifier: GPL-2.0+
	804	+ *
	805	+ * Generated code from MX8M_DDR_tool
	806	+ *
	807	+ * Align with uboot version:
	808	+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
	809	+ * For imx_v2019.04_5.4.x and above version:
	810	+ * please replace #include <asm/arch/imx8m_ddr.h> with #include <asm/arch/ddr.h>
	811	+ */
	812	+
	813	+#include <linux/kernel.h>
	814	+#include <asm/arch/ddr.h>
	815	+
	816	+struct dram_cfg_param ddr_ddrc_cfg[] = {
	817	+ / Initialize DDRC registers /
	818	+ { 0x3d400304, 0x1 },
	819	+ { 0x3d400030, 0x1 },
	820	+ { 0x3d400000, 0x81040010 },
	821	+ { 0x3d400030, 0xaa },
	822	+ { 0x3d400034, 0x221306 },
	823	+ { 0x3d400050, 0x210070 },
	824	+ { 0x3d400054, 0x10008 },
	825	+ { 0x3d400060, 0x0 },
	826	+ { 0x3d400064, 0xc30118 },
	827	+ { 0x3d4000c0, 0x0 },
	828	+ { 0x3d4000c4, 0x1000 },
	829	+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
	830	+ { 0x3d400070, 0x1027f54 },
	831	+#else
	832	+ { 0x3d400070, 0x1027f10 },
	833	+#endif
	834	+ { 0x3d400074, 0x7b0 },
	835	+ { 0x3d4000d0, 0xc0030188 },
	836	+ { 0x3d4000d4, 0x9e0000 },
	837	+ { 0x3d4000dc, 0xc500501 },
	838	+ { 0x3d4000e0, 0x280400 },
	839	+ { 0x3d4000e4, 0x110000 },
	840	+ { 0x3d4000e8, 0x2000600 },
	841	+ { 0x3d4000ec, 0x1010 },
	842	+ { 0x3d4000f0, 0x20 },
	843	+ { 0x3d4000f4, 0xec7 },
	844	+ { 0x3d400100, 0x1618361a },
	845	+ { 0x3d400104, 0x50626 },
	846	+ { 0x3d400108, 0x80b0610 },
	847	+ { 0x3d40010c, 0x400c },
	848	+ { 0x3d400110, 0xc04060d },
	849	+ { 0x3d400114, 0x8080504 },
	850	+ { 0x3d40011c, 0x808 },
	851	+ { 0x3d400120, 0x6060d0a },
	852	+ { 0x3d400124, 0x2050c },
	853	+ { 0x3d40012c, 0x160b010e },
	854	+ { 0x3d400130, 0x8 },
	855	+ { 0x3d40013c, 0x0 },
	856	+ { 0x3d400180, 0x1000040 },
	857	+ { 0x3d400184, 0x61a8 },
	858	+ { 0x3d400190, 0x391820b },
	859	+ { 0x3d400194, 0x2020303 },
	860	+ { 0x3d400198, 0x7f04011 },
	861	+ { 0x3d40019c, 0xb0 },
	862	+ { 0x3d4001a0, 0xe0400018 },
	863	+ { 0x3d4001a4, 0x48005a },
	864	+ { 0x3d4001a8, 0x80000000 },
	865	+ { 0x3d4001b0, 0x1 },
	866	+ { 0x3d4001b4, 0x110b },
	867	+ { 0x3d4001b8, 0x4 },
	868	+ { 0x3d4001c0, 0x1 },
	869	+ { 0x3d4001c4, 0x0 },
	870	+ { 0x3d400200, 0x1f },
	871	+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
	872	+ { 0x3d400204, 0x3f0505 },
	873	+ { 0x3d400208, 0x700 },
	874	+ { 0x3d40020c, 0x14141400 },
	875	+ { 0x3d400210, 0x1f1f },
	876	+ { 0x3d400214, 0x4040403 },
	877	+ { 0x3d400218, 0x4040404 },
	878	+ { 0x3d40021c, 0xf04 },
	879	+#else
	880	+ { 0x3d400204, 0x3f0909 },
	881	+ { 0x3d400208, 0x700 },
	882	+ { 0x3d40020c, 0x0 },
	883	+ { 0x3d400210, 0x1f1f },
	884	+ { 0x3d400214, 0x7070707 },
	885	+ { 0x3d400218, 0x7070707 },
	886	+ { 0x3d40021c, 0xf07 },
	887	+#endif
	888	+ { 0x3d400220, 0x3f01 },
	889	+ { 0x3d400240, 0x6000618 },
	890	+ { 0x3d400244, 0x1323 },
	891	+ { 0x3d400250, 0x00001a05 },
	892	+ { 0x3d400254, 0x1f },
	893	+ { 0x3d40025c, 0x10000010 },
	894	+ { 0x3d400264, 0x100000ff },
	895	+ { 0x3d40026c, 0x100002ff },
	896	+ { 0x3d40036c, 0x0 },
	897	+ { 0x3d400400, 0x100 },
	898	+ { 0x3d400404, 0x72ff },
	899	+ { 0x3d400408, 0x72ff },
	900	+ { 0x3d400494, 0x2100e07 },
	901	+ { 0x3d400498, 0x620096 },
	902	+ { 0x3d40049c, 0x1100e07 },
	903	+ { 0x3d4004a0, 0xc8012c },
	904	+ { 0x3d402050, 0x210070 },
	905	+ { 0x3d402064, 0x40005e },
	906	+ { 0x3d4020dc, 0x40501 },
	907	+ { 0x3d4020e0, 0x0 },
	908	+ { 0x3d4020e8, 0x2000600 },
	909	+ { 0x3d4020ec, 0x10 },
	910	+ { 0x3d402100, 0xb081209 },
	911	+ { 0x3d402104, 0x2020d },
	912	+ { 0x3d402108, 0x5050309 },
	913	+ { 0x3d40210c, 0x400c },
	914	+ { 0x3d402110, 0x4030205 },
	915	+ { 0x3d402114, 0x3030202 },
	916	+ { 0x3d40211c, 0x303 },
	917	+ { 0x3d402120, 0x3030d04 },
	918	+ { 0x3d402124, 0x20208 },
	919	+ { 0x3d40212c, 0x1005010e },
	920	+ { 0x3d402130, 0x8 },
	921	+ { 0x3d40213c, 0x0 },
	922	+ { 0x3d402180, 0x1000040 },
	923	+ { 0x3d402190, 0x3858204 },
	924	+ { 0x3d402194, 0x2020303 },
	925	+ { 0x3d4021b4, 0x504 },
	926	+ { 0x3d4021b8, 0x4 },
	927	+ { 0x3d402240, 0x6000604 },
	928	+ { 0x3d4020f4, 0xec7 },
	929	+};
	930	+
	931	+/* PHY Initialize Configuration */
	932	+struct dram_cfg_param ddr_ddrphy_cfg[] = {
	933	+ { 0x1005f, 0x2df },
	934	+ { 0x1015f, 0x2df },
	935	+ { 0x1105f, 0x2df },
	936	+ { 0x1115f, 0x2df },
	937	+ { 0x1205f, 0x2df },
	938	+ { 0x1215f, 0x2df },
	939	+ { 0x1305f, 0x2df },
	940	+ { 0x1315f, 0x2df },
	941	+ { 0x11005f, 0x2df },
	942	+ { 0x11015f, 0x2df },
	943	+ { 0x11105f, 0x2df },
	944	+ { 0x11115f, 0x2df },
	945	+ { 0x11205f, 0x2df },
	946	+ { 0x11215f, 0x2df },
	947	+ { 0x11305f, 0x2df },
	948	+ { 0x11315f, 0x2df },
	949	+ { 0x55, 0x355 },
	950	+ { 0x1055, 0x355 },
	951	+ { 0x2055, 0x355 },
	952	+ { 0x3055, 0x355 },
	953	+ { 0x4055, 0x55 },
	954	+ { 0x5055, 0x55 },
	955	+ { 0x6055, 0x355 },
	956	+ { 0x7055, 0x355 },
	957	+ { 0x8055, 0x355 },
	958	+ { 0x9055, 0x355 },
	959	+ { 0x200c5, 0x19 },
	960	+ { 0x1200c5, 0x6 },
	961	+ { 0x2002e, 0x2 },
	962	+ { 0x12002e, 0x1 },
	963	+ { 0x20024, 0x8 },
	964	+ { 0x2003a, 0x2 },
	965	+ { 0x120024, 0x8 },
	966	+ { 0x2003a, 0x2 },
	967	+ { 0x20056, 0x7 },
	968	+ { 0x120056, 0xa },
	969	+ { 0x1004d, 0x1a },
	970	+ { 0x1014d, 0x1a },
	971	+ { 0x1104d, 0x1a },
	972	+ { 0x1114d, 0x1a },
	973	+ { 0x1204d, 0x1a },
	974	+ { 0x1214d, 0x1a },
	975	+ { 0x1304d, 0x1a },
	976	+ { 0x1314d, 0x1a },
	977	+ { 0x11004d, 0x1a },
	978	+ { 0x11014d, 0x1a },
	979	+ { 0x11104d, 0x1a },
	980	+ { 0x11114d, 0x1a },
	981	+ { 0x11204d, 0x1a },
	982	+ { 0x11214d, 0x1a },
	983	+ { 0x11304d, 0x1a },
	984	+ { 0x11314d, 0x1a },
	985	+ { 0x10049, 0xeba },
	986	+ { 0x10149, 0xeba },
	987	+ { 0x11049, 0xeba },
	988	+ { 0x11149, 0xeba },
	989	+ { 0x12049, 0xeba },
	990	+ { 0x12149, 0xeba },
	991	+ { 0x13049, 0xeba },
	992	+ { 0x13149, 0xeba },
	993	+ { 0x110049, 0xeba },
	994	+ { 0x110149, 0xeba },
	995	+ { 0x111049, 0xeba },
	996	+ { 0x111149, 0xeba },
	997	+ { 0x112049, 0xeba },
	998	+ { 0x112149, 0xeba },
	999	+ { 0x113049, 0xeba },
	1000	+ { 0x113149, 0xeba },
	1001	+ { 0x43, 0xe7 },
	1002	+ { 0x1043, 0xe7 },
	1003	+ { 0x2043, 0xe7 },
	1004	+ { 0x3043, 0xe7 },
	1005	+ { 0x4043, 0xe7 },
	1006	+ { 0x5043, 0xe7 },
	1007	+ { 0x6043, 0xe7 },
	1008	+ { 0x7043, 0xe7 },
	1009	+ { 0x8043, 0xe7 },
	1010	+ { 0x9043, 0xe7 },
	1011	+ { 0x20018, 0x5 },
	1012	+ { 0x20075, 0x2 },
	1013	+ { 0x20050, 0x0 },
	1014	+ { 0x20008, 0x320 },
	1015	+ { 0x120008, 0x10a },
	1016	+ { 0x20088, 0x9 },
	1017	+ { 0x200b2, 0x248 },
	1018	+ { 0x10043, 0x5b1 },
	1019	+ { 0x10143, 0x5b1 },
	1020	+ { 0x11043, 0x5b1 },
	1021	+ { 0x11143, 0x5b1 },
	1022	+ { 0x12043, 0x5b1 },
	1023	+ { 0x12143, 0x5b1 },
	1024	+ { 0x13043, 0x5b1 },
	1025	+ { 0x13143, 0x5b1 },
	1026	+ { 0x1200b2, 0x248 },
	1027	+ { 0x110043, 0x5b1 },
	1028	+ { 0x110143, 0x5b1 },
	1029	+ { 0x111043, 0x5b1 },
	1030	+ { 0x111143, 0x5b1 },
	1031	+ { 0x112043, 0x5b1 },
	1032	+ { 0x112143, 0x5b1 },
	1033	+ { 0x113043, 0x5b1 },
	1034	+ { 0x113143, 0x5b1 },
	1035	+ { 0x200fa, 0x1 },
	1036	+ { 0x1200fa, 0x1 },
	1037	+ { 0x20019, 0x5 },
	1038	+ { 0x120019, 0x5 },
	1039	+ { 0x200f0, 0x5555 },
	1040	+ { 0x200f1, 0x5555 },
	1041	+ { 0x200f2, 0x5555 },
	1042	+ { 0x200f3, 0x5555 },
	1043	+ { 0x200f4, 0x5555 },
	1044	+ { 0x200f5, 0x5555 },
	1045	+ { 0x200f6, 0x5555 },
	1046	+ { 0x200f7, 0xf000 },
	1047	+ { 0x20025, 0x0 },
	1048	+ { 0x2002d, 0x0 },
	1049	+ { 0x12002d, 0x0 },
	1050	+ { 0x2007d, 0x212 },
	1051	+ { 0x12007d, 0x212 },
	1052	+ { 0x2007c, 0x61 },
	1053	+ { 0x12007c, 0x61 },
	1054	+ { 0x1004a, 0x500 },
	1055	+ { 0x1104a, 0x500 },
	1056	+ { 0x1204a, 0x500 },
	1057	+ { 0x1304a, 0x500 },
	1058	+ { 0x2002c, 0x0 },
	1059	+};
	1060	+
	1061	+/* ddr phy trained csr */
	1062	+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
	1063	+ { 0x200b2, 0x0 },
	1064	+ { 0x1200b2, 0x0 },
	1065	+ { 0x2200b2, 0x0 },
	1066	+ { 0x200cb, 0x0 },
	1067	+ { 0x10043, 0x0 },
	1068	+ { 0x110043, 0x0 },
	1069	+ { 0x210043, 0x0 },
	1070	+ { 0x10143, 0x0 },
	1071	+ { 0x110143, 0x0 },
	1072	+ { 0x210143, 0x0 },
	1073	+ { 0x11043, 0x0 },
	1074	+ { 0x111043, 0x0 },
	1075	+ { 0x211043, 0x0 },
	1076	+ { 0x11143, 0x0 },
	1077	+ { 0x111143, 0x0 },
	1078	+ { 0x211143, 0x0 },
	1079	+ { 0x12043, 0x0 },
	1080	+ { 0x112043, 0x0 },
	1081	+ { 0x212043, 0x0 },
	1082	+ { 0x12143, 0x0 },
	1083	+ { 0x112143, 0x0 },
	1084	+ { 0x212143, 0x0 },
	1085	+ { 0x13043, 0x0 },
	1086	+ { 0x113043, 0x0 },
	1087	+ { 0x213043, 0x0 },
	1088	+ { 0x13143, 0x0 },
	1089	+ { 0x113143, 0x0 },
	1090	+ { 0x213143, 0x0 },
	1091	+ { 0x80, 0x0 },
	1092	+ { 0x100080, 0x0 },
	1093	+ { 0x200080, 0x0 },
	1094	+ { 0x1080, 0x0 },
	1095	+ { 0x101080, 0x0 },
	1096	+ { 0x201080, 0x0 },
	1097	+ { 0x2080, 0x0 },
	1098	+ { 0x102080, 0x0 },
	1099	+ { 0x202080, 0x0 },
	1100	+ { 0x3080, 0x0 },
	1101	+ { 0x103080, 0x0 },
	1102	+ { 0x203080, 0x0 },
	1103	+ { 0x4080, 0x0 },
	1104	+ { 0x104080, 0x0 },
	1105	+ { 0x204080, 0x0 },
	1106	+ { 0x5080, 0x0 },
	1107	+ { 0x105080, 0x0 },
	1108	+ { 0x205080, 0x0 },
	1109	+ { 0x6080, 0x0 },
	1110	+ { 0x106080, 0x0 },
	1111	+ { 0x206080, 0x0 },
	1112	+ { 0x7080, 0x0 },
	1113	+ { 0x107080, 0x0 },
	1114	+ { 0x207080, 0x0 },
	1115	+ { 0x8080, 0x0 },
	1116	+ { 0x108080, 0x0 },
	1117	+ { 0x208080, 0x0 },
	1118	+ { 0x9080, 0x0 },
	1119	+ { 0x109080, 0x0 },
	1120	+ { 0x209080, 0x0 },
	1121	+ { 0x10080, 0x0 },
	1122	+ { 0x110080, 0x0 },
	1123	+ { 0x210080, 0x0 },
	1124	+ { 0x10180, 0x0 },
	1125	+ { 0x110180, 0x0 },
	1126	+ { 0x210180, 0x0 },
	1127	+ { 0x11080, 0x0 },
	1128	+ { 0x111080, 0x0 },
	1129	+ { 0x211080, 0x0 },
	1130	+ { 0x11180, 0x0 },
	1131	+ { 0x111180, 0x0 },
	1132	+ { 0x211180, 0x0 },
	1133	+ { 0x12080, 0x0 },
	1134	+ { 0x112080, 0x0 },
	1135	+ { 0x212080, 0x0 },
	1136	+ { 0x12180, 0x0 },
	1137	+ { 0x112180, 0x0 },
	1138	+ { 0x212180, 0x0 },
	1139	+ { 0x13080, 0x0 },
	1140	+ { 0x113080, 0x0 },
	1141	+ { 0x213080, 0x0 },
	1142	+ { 0x13180, 0x0 },
	1143	+ { 0x113180, 0x0 },
	1144	+ { 0x213180, 0x0 },
	1145	+ { 0x10081, 0x0 },
	1146	+ { 0x110081, 0x0 },
	1147	+ { 0x210081, 0x0 },
	1148	+ { 0x10181, 0x0 },
	1149	+ { 0x110181, 0x0 },
	1150	+ { 0x210181, 0x0 },
	1151	+ { 0x11081, 0x0 },
	1152	+ { 0x111081, 0x0 },
	1153	+ { 0x211081, 0x0 },
	1154	+ { 0x11181, 0x0 },
	1155	+ { 0x111181, 0x0 },
	1156	+ { 0x211181, 0x0 },
	1157	+ { 0x12081, 0x0 },
	1158	+ { 0x112081, 0x0 },
	1159	+ { 0x212081, 0x0 },
	1160	+ { 0x12181, 0x0 },
	1161	+ { 0x112181, 0x0 },
	1162	+ { 0x212181, 0x0 },
	1163	+ { 0x13081, 0x0 },
	1164	+ { 0x113081, 0x0 },
	1165	+ { 0x213081, 0x0 },
	1166	+ { 0x13181, 0x0 },
	1167	+ { 0x113181, 0x0 },
	1168	+ { 0x213181, 0x0 },
	1169	+ { 0x100d0, 0x0 },
	1170	+ { 0x1100d0, 0x0 },
	1171	+ { 0x2100d0, 0x0 },
	1172	+ { 0x101d0, 0x0 },
	1173	+ { 0x1101d0, 0x0 },
	1174	+ { 0x2101d0, 0x0 },
	1175	+ { 0x110d0, 0x0 },
	1176	+ { 0x1110d0, 0x0 },
	1177	+ { 0x2110d0, 0x0 },
	1178	+ { 0x111d0, 0x0 },
	1179	+ { 0x1111d0, 0x0 },
	1180	+ { 0x2111d0, 0x0 },
	1181	+ { 0x120d0, 0x0 },
	1182	+ { 0x1120d0, 0x0 },
	1183	+ { 0x2120d0, 0x0 },
	1184	+ { 0x121d0, 0x0 },
	1185	+ { 0x1121d0, 0x0 },
	1186	+ { 0x2121d0, 0x0 },
	1187	+ { 0x130d0, 0x0 },
	1188	+ { 0x1130d0, 0x0 },
	1189	+ { 0x2130d0, 0x0 },
	1190	+ { 0x131d0, 0x0 },
	1191	+ { 0x1131d0, 0x0 },
	1192	+ { 0x2131d0, 0x0 },
	1193	+ { 0x100d1, 0x0 },
	1194	+ { 0x1100d1, 0x0 },
	1195	+ { 0x2100d1, 0x0 },
	1196	+ { 0x101d1, 0x0 },
	1197	+ { 0x1101d1, 0x0 },
	1198	+ { 0x2101d1, 0x0 },
	1199	+ { 0x110d1, 0x0 },
	1200	+ { 0x1110d1, 0x0 },
	1201	+ { 0x2110d1, 0x0 },
	1202	+ { 0x111d1, 0x0 },
	1203	+ { 0x1111d1, 0x0 },
	1204	+ { 0x2111d1, 0x0 },
	1205	+ { 0x120d1, 0x0 },
	1206	+ { 0x1120d1, 0x0 },
	1207	+ { 0x2120d1, 0x0 },
	1208	+ { 0x121d1, 0x0 },
	1209	+ { 0x1121d1, 0x0 },
	1210	+ { 0x2121d1, 0x0 },
	1211	+ { 0x130d1, 0x0 },
	1212	+ { 0x1130d1, 0x0 },
	1213	+ { 0x2130d1, 0x0 },
	1214	+ { 0x131d1, 0x0 },
	1215	+ { 0x1131d1, 0x0 },
	1216	+ { 0x2131d1, 0x0 },
	1217	+ { 0x10068, 0x0 },
	1218	+ { 0x10168, 0x0 },
	1219	+ { 0x10268, 0x0 },
	1220	+ { 0x10368, 0x0 },
	1221	+ { 0x10468, 0x0 },
	1222	+ { 0x10568, 0x0 },
	1223	+ { 0x10668, 0x0 },
	1224	+ { 0x10768, 0x0 },
	1225	+ { 0x10868, 0x0 },
	1226	+ { 0x11068, 0x0 },
	1227	+ { 0x11168, 0x0 },
	1228	+ { 0x11268, 0x0 },
	1229	+ { 0x11368, 0x0 },
	1230	+ { 0x11468, 0x0 },
	1231	+ { 0x11568, 0x0 },
	1232	+ { 0x11668, 0x0 },
	1233	+ { 0x11768, 0x0 },
	1234	+ { 0x11868, 0x0 },
	1235	+ { 0x12068, 0x0 },
	1236	+ { 0x12168, 0x0 },
	1237	+ { 0x12268, 0x0 },
	1238	+ { 0x12368, 0x0 },
	1239	+ { 0x12468, 0x0 },
	1240	+ { 0x12568, 0x0 },
	1241	+ { 0x12668, 0x0 },
	1242	+ { 0x12768, 0x0 },
	1243	+ { 0x12868, 0x0 },
	1244	+ { 0x13068, 0x0 },
	1245	+ { 0x13168, 0x0 },
	1246	+ { 0x13268, 0x0 },
	1247	+ { 0x13368, 0x0 },
	1248	+ { 0x13468, 0x0 },
	1249	+ { 0x13568, 0x0 },
	1250	+ { 0x13668, 0x0 },
	1251	+ { 0x13768, 0x0 },
	1252	+ { 0x13868, 0x0 },
	1253	+ { 0x10069, 0x0 },
	1254	+ { 0x10169, 0x0 },
	1255	+ { 0x10269, 0x0 },
	1256	+ { 0x10369, 0x0 },
	1257	+ { 0x10469, 0x0 },
	1258	+ { 0x10569, 0x0 },
	1259	+ { 0x10669, 0x0 },
	1260	+ { 0x10769, 0x0 },
	1261	+ { 0x10869, 0x0 },
	1262	+ { 0x11069, 0x0 },
	1263	+ { 0x11169, 0x0 },
	1264	+ { 0x11269, 0x0 },
	1265	+ { 0x11369, 0x0 },
	1266	+ { 0x11469, 0x0 },
	1267	+ { 0x11569, 0x0 },
	1268	+ { 0x11669, 0x0 },
	1269	+ { 0x11769, 0x0 },
	1270	+ { 0x11869, 0x0 },
	1271	+ { 0x12069, 0x0 },
	1272	+ { 0x12169, 0x0 },
	1273	+ { 0x12269, 0x0 },
	1274	+ { 0x12369, 0x0 },
	1275	+ { 0x12469, 0x0 },
	1276	+ { 0x12569, 0x0 },
	1277	+ { 0x12669, 0x0 },
	1278	+ { 0x12769, 0x0 },
	1279	+ { 0x12869, 0x0 },
	1280	+ { 0x13069, 0x0 },
	1281	+ { 0x13169, 0x0 },
	1282	+ { 0x13269, 0x0 },
	1283	+ { 0x13369, 0x0 },
	1284	+ { 0x13469, 0x0 },
	1285	+ { 0x13569, 0x0 },
	1286	+ { 0x13669, 0x0 },
	1287	+ { 0x13769, 0x0 },
	1288	+ { 0x13869, 0x0 },
	1289	+ { 0x1008c, 0x0 },
	1290	+ { 0x11008c, 0x0 },
	1291	+ { 0x21008c, 0x0 },
	1292	+ { 0x1018c, 0x0 },
	1293	+ { 0x11018c, 0x0 },
	1294	+ { 0x21018c, 0x0 },
	1295	+ { 0x1108c, 0x0 },
	1296	+ { 0x11108c, 0x0 },
	1297	+ { 0x21108c, 0x0 },
	1298	+ { 0x1118c, 0x0 },
	1299	+ { 0x11118c, 0x0 },
	1300	+ { 0x21118c, 0x0 },
	1301	+ { 0x1208c, 0x0 },
	1302	+ { 0x11208c, 0x0 },
	1303	+ { 0x21208c, 0x0 },
	1304	+ { 0x1218c, 0x0 },
	1305	+ { 0x11218c, 0x0 },
	1306	+ { 0x21218c, 0x0 },
	1307	+ { 0x1308c, 0x0 },
	1308	+ { 0x11308c, 0x0 },
	1309	+ { 0x21308c, 0x0 },
	1310	+ { 0x1318c, 0x0 },
	1311	+ { 0x11318c, 0x0 },
	1312	+ { 0x21318c, 0x0 },
	1313	+ { 0x1008d, 0x0 },
	1314	+ { 0x11008d, 0x0 },
	1315	+ { 0x21008d, 0x0 },
	1316	+ { 0x1018d, 0x0 },
	1317	+ { 0x11018d, 0x0 },
	1318	+ { 0x21018d, 0x0 },
	1319	+ { 0x1108d, 0x0 },
	1320	+ { 0x11108d, 0x0 },
	1321	+ { 0x21108d, 0x0 },
	1322	+ { 0x1118d, 0x0 },
	1323	+ { 0x11118d, 0x0 },
	1324	+ { 0x21118d, 0x0 },
	1325	+ { 0x1208d, 0x0 },
	1326	+ { 0x11208d, 0x0 },
	1327	+ { 0x21208d, 0x0 },
	1328	+ { 0x1218d, 0x0 },
	1329	+ { 0x11218d, 0x0 },
	1330	+ { 0x21218d, 0x0 },
	1331	+ { 0x1308d, 0x0 },
	1332	+ { 0x11308d, 0x0 },
	1333	+ { 0x21308d, 0x0 },
	1334	+ { 0x1318d, 0x0 },
	1335	+ { 0x11318d, 0x0 },
	1336	+ { 0x21318d, 0x0 },
	1337	+ { 0x100c0, 0x0 },
	1338	+ { 0x1100c0, 0x0 },
	1339	+ { 0x2100c0, 0x0 },
	1340	+ { 0x101c0, 0x0 },
	1341	+ { 0x1101c0, 0x0 },
	1342	+ { 0x2101c0, 0x0 },
	1343	+ { 0x102c0, 0x0 },
	1344	+ { 0x1102c0, 0x0 },
	1345	+ { 0x2102c0, 0x0 },
	1346	+ { 0x103c0, 0x0 },
	1347	+ { 0x1103c0, 0x0 },
	1348	+ { 0x2103c0, 0x0 },
	1349	+ { 0x104c0, 0x0 },
	1350	+ { 0x1104c0, 0x0 },
	1351	+ { 0x2104c0, 0x0 },
	1352	+ { 0x105c0, 0x0 },
	1353	+ { 0x1105c0, 0x0 },
	1354	+ { 0x2105c0, 0x0 },
	1355	+ { 0x106c0, 0x0 },
	1356	+ { 0x1106c0, 0x0 },
	1357	+ { 0x2106c0, 0x0 },
	1358	+ { 0x107c0, 0x0 },
	1359	+ { 0x1107c0, 0x0 },
	1360	+ { 0x2107c0, 0x0 },
	1361	+ { 0x108c0, 0x0 },
	1362	+ { 0x1108c0, 0x0 },
	1363	+ { 0x2108c0, 0x0 },
	1364	+ { 0x110c0, 0x0 },
	1365	+ { 0x1110c0, 0x0 },
	1366	+ { 0x2110c0, 0x0 },
	1367	+ { 0x111c0, 0x0 },
	1368	+ { 0x1111c0, 0x0 },
	1369	+ { 0x2111c0, 0x0 },
	1370	+ { 0x112c0, 0x0 },
	1371	+ { 0x1112c0, 0x0 },
	1372	+ { 0x2112c0, 0x0 },
	1373	+ { 0x113c0, 0x0 },
	1374	+ { 0x1113c0, 0x0 },
	1375	+ { 0x2113c0, 0x0 },
	1376	+ { 0x114c0, 0x0 },
	1377	+ { 0x1114c0, 0x0 },
	1378	+ { 0x2114c0, 0x0 },
	1379	+ { 0x115c0, 0x0 },
	1380	+ { 0x1115c0, 0x0 },
	1381	+ { 0x2115c0, 0x0 },
	1382	+ { 0x116c0, 0x0 },
	1383	+ { 0x1116c0, 0x0 },
	1384	+ { 0x2116c0, 0x0 },
	1385	+ { 0x117c0, 0x0 },
	1386	+ { 0x1117c0, 0x0 },
	1387	+ { 0x2117c0, 0x0 },
	1388	+ { 0x118c0, 0x0 },
	1389	+ { 0x1118c0, 0x0 },
	1390	+ { 0x2118c0, 0x0 },
	1391	+ { 0x120c0, 0x0 },
	1392	+ { 0x1120c0, 0x0 },
	1393	+ { 0x2120c0, 0x0 },
	1394	+ { 0x121c0, 0x0 },
	1395	+ { 0x1121c0, 0x0 },
	1396	+ { 0x2121c0, 0x0 },
	1397	+ { 0x122c0, 0x0 },
	1398	+ { 0x1122c0, 0x0 },
	1399	+ { 0x2122c0, 0x0 },
	1400	+ { 0x123c0, 0x0 },
	1401	+ { 0x1123c0, 0x0 },
	1402	+ { 0x2123c0, 0x0 },
	1403	+ { 0x124c0, 0x0 },
	1404	+ { 0x1124c0, 0x0 },
	1405	+ { 0x2124c0, 0x0 },
	1406	+ { 0x125c0, 0x0 },
	1407	+ { 0x1125c0, 0x0 },
	1408	+ { 0x2125c0, 0x0 },
	1409	+ { 0x126c0, 0x0 },
	1410	+ { 0x1126c0, 0x0 },
	1411	+ { 0x2126c0, 0x0 },
	1412	+ { 0x127c0, 0x0 },
	1413	+ { 0x1127c0, 0x0 },
	1414	+ { 0x2127c0, 0x0 },
	1415	+ { 0x128c0, 0x0 },
	1416	+ { 0x1128c0, 0x0 },
	1417	+ { 0x2128c0, 0x0 },
	1418	+ { 0x130c0, 0x0 },
	1419	+ { 0x1130c0, 0x0 },
	1420	+ { 0x2130c0, 0x0 },
	1421	+ { 0x131c0, 0x0 },
	1422	+ { 0x1131c0, 0x0 },
	1423	+ { 0x2131c0, 0x0 },
	1424	+ { 0x132c0, 0x0 },
	1425	+ { 0x1132c0, 0x0 },
	1426	+ { 0x2132c0, 0x0 },
	1427	+ { 0x133c0, 0x0 },
	1428	+ { 0x1133c0, 0x0 },
	1429	+ { 0x2133c0, 0x0 },
	1430	+ { 0x134c0, 0x0 },
	1431	+ { 0x1134c0, 0x0 },
	1432	+ { 0x2134c0, 0x0 },
	1433	+ { 0x135c0, 0x0 },
	1434	+ { 0x1135c0, 0x0 },
	1435	+ { 0x2135c0, 0x0 },
	1436	+ { 0x136c0, 0x0 },
	1437	+ { 0x1136c0, 0x0 },
	1438	+ { 0x2136c0, 0x0 },
	1439	+ { 0x137c0, 0x0 },
	1440	+ { 0x1137c0, 0x0 },
	1441	+ { 0x2137c0, 0x0 },
	1442	+ { 0x138c0, 0x0 },
	1443	+ { 0x1138c0, 0x0 },
	1444	+ { 0x2138c0, 0x0 },
	1445	+ { 0x100c1, 0x0 },
	1446	+ { 0x1100c1, 0x0 },
	1447	+ { 0x2100c1, 0x0 },
	1448	+ { 0x101c1, 0x0 },
	1449	+ { 0x1101c1, 0x0 },
	1450	+ { 0x2101c1, 0x0 },
	1451	+ { 0x102c1, 0x0 },
	1452	+ { 0x1102c1, 0x0 },
	1453	+ { 0x2102c1, 0x0 },
	1454	+ { 0x103c1, 0x0 },
	1455	+ { 0x1103c1, 0x0 },
	1456	+ { 0x2103c1, 0x0 },
	1457	+ { 0x104c1, 0x0 },
	1458	+ { 0x1104c1, 0x0 },
	1459	+ { 0x2104c1, 0x0 },
	1460	+ { 0x105c1, 0x0 },
	1461	+ { 0x1105c1, 0x0 },
	1462	+ { 0x2105c1, 0x0 },
	1463	+ { 0x106c1, 0x0 },
	1464	+ { 0x1106c1, 0x0 },
	1465	+ { 0x2106c1, 0x0 },
	1466	+ { 0x107c1, 0x0 },
	1467	+ { 0x1107c1, 0x0 },
	1468	+ { 0x2107c1, 0x0 },
	1469	+ { 0x108c1, 0x0 },
	1470	+ { 0x1108c1, 0x0 },
	1471	+ { 0x2108c1, 0x0 },
	1472	+ { 0x110c1, 0x0 },
	1473	+ { 0x1110c1, 0x0 },
	1474	+ { 0x2110c1, 0x0 },
	1475	+ { 0x111c1, 0x0 },
	1476	+ { 0x1111c1, 0x0 },
	1477	+ { 0x2111c1, 0x0 },
	1478	+ { 0x112c1, 0x0 },
	1479	+ { 0x1112c1, 0x0 },
	1480	+ { 0x2112c1, 0x0 },
	1481	+ { 0x113c1, 0x0 },
	1482	+ { 0x1113c1, 0x0 },
	1483	+ { 0x2113c1, 0x0 },
	1484	+ { 0x114c1, 0x0 },
	1485	+ { 0x1114c1, 0x0 },
	1486	+ { 0x2114c1, 0x0 },
	1487	+ { 0x115c1, 0x0 },
	1488	+ { 0x1115c1, 0x0 },
	1489	+ { 0x2115c1, 0x0 },
	1490	+ { 0x116c1, 0x0 },
	1491	+ { 0x1116c1, 0x0 },
	1492	+ { 0x2116c1, 0x0 },
	1493	+ { 0x117c1, 0x0 },
	1494	+ { 0x1117c1, 0x0 },
	1495	+ { 0x2117c1, 0x0 },
	1496	+ { 0x118c1, 0x0 },
	1497	+ { 0x1118c1, 0x0 },
	1498	+ { 0x2118c1, 0x0 },
	1499	+ { 0x120c1, 0x0 },
	1500	+ { 0x1120c1, 0x0 },
	1501	+ { 0x2120c1, 0x0 },
	1502	+ { 0x121c1, 0x0 },
	1503	+ { 0x1121c1, 0x0 },
	1504	+ { 0x2121c1, 0x0 },
	1505	+ { 0x122c1, 0x0 },
	1506	+ { 0x1122c1, 0x0 },
	1507	+ { 0x2122c1, 0x0 },
	1508	+ { 0x123c1, 0x0 },
	1509	+ { 0x1123c1, 0x0 },
	1510	+ { 0x2123c1, 0x0 },
	1511	+ { 0x124c1, 0x0 },
	1512	+ { 0x1124c1, 0x0 },
	1513	+ { 0x2124c1, 0x0 },
	1514	+ { 0x125c1, 0x0 },
	1515	+ { 0x1125c1, 0x0 },
	1516	+ { 0x2125c1, 0x0 },
	1517	+ { 0x126c1, 0x0 },
	1518	+ { 0x1126c1, 0x0 },
	1519	+ { 0x2126c1, 0x0 },
	1520	+ { 0x127c1, 0x0 },
	1521	+ { 0x1127c1, 0x0 },
	1522	+ { 0x2127c1, 0x0 },
	1523	+ { 0x128c1, 0x0 },
	1524	+ { 0x1128c1, 0x0 },
	1525	+ { 0x2128c1, 0x0 },
	1526	+ { 0x130c1, 0x0 },
	1527	+ { 0x1130c1, 0x0 },
	1528	+ { 0x2130c1, 0x0 },
	1529	+ { 0x131c1, 0x0 },
	1530	+ { 0x1131c1, 0x0 },
	1531	+ { 0x2131c1, 0x0 },
	1532	+ { 0x132c1, 0x0 },
	1533	+ { 0x1132c1, 0x0 },
	1534	+ { 0x2132c1, 0x0 },
	1535	+ { 0x133c1, 0x0 },
	1536	+ { 0x1133c1, 0x0 },
	1537	+ { 0x2133c1, 0x0 },
	1538	+ { 0x134c1, 0x0 },
	1539	+ { 0x1134c1, 0x0 },
	1540	+ { 0x2134c1, 0x0 },
	1541	+ { 0x135c1, 0x0 },
	1542	+ { 0x1135c1, 0x0 },
	1543	+ { 0x2135c1, 0x0 },
	1544	+ { 0x136c1, 0x0 },
	1545	+ { 0x1136c1, 0x0 },
	1546	+ { 0x2136c1, 0x0 },
	1547	+ { 0x137c1, 0x0 },
	1548	+ { 0x1137c1, 0x0 },
	1549	+ { 0x2137c1, 0x0 },
	1550	+ { 0x138c1, 0x0 },
	1551	+ { 0x1138c1, 0x0 },
	1552	+ { 0x2138c1, 0x0 },
	1553	+ { 0x10020, 0x0 },
	1554	+ { 0x110020, 0x0 },
	1555	+ { 0x210020, 0x0 },
	1556	+ { 0x11020, 0x0 },
	1557	+ { 0x111020, 0x0 },
	1558	+ { 0x211020, 0x0 },
	1559	+ { 0x12020, 0x0 },
	1560	+ { 0x112020, 0x0 },
	1561	+ { 0x212020, 0x0 },
	1562	+ { 0x13020, 0x0 },
	1563	+ { 0x113020, 0x0 },
	1564	+ { 0x213020, 0x0 },
	1565	+ { 0x20072, 0x0 },
	1566	+ { 0x20073, 0x0 },
	1567	+ { 0x20074, 0x0 },
	1568	+ { 0x100aa, 0x0 },
	1569	+ { 0x110aa, 0x0 },
	1570	+ { 0x120aa, 0x0 },
	1571	+ { 0x130aa, 0x0 },
	1572	+ { 0x20010, 0x0 },
	1573	+ { 0x120010, 0x0 },
	1574	+ { 0x220010, 0x0 },
	1575	+ { 0x20011, 0x0 },
	1576	+ { 0x120011, 0x0 },
	1577	+ { 0x220011, 0x0 },
	1578	+ { 0x100ae, 0x0 },
	1579	+ { 0x1100ae, 0x0 },
	1580	+ { 0x2100ae, 0x0 },
	1581	+ { 0x100af, 0x0 },
	1582	+ { 0x1100af, 0x0 },
	1583	+ { 0x2100af, 0x0 },
	1584	+ { 0x110ae, 0x0 },
	1585	+ { 0x1110ae, 0x0 },
	1586	+ { 0x2110ae, 0x0 },
	1587	+ { 0x110af, 0x0 },
	1588	+ { 0x1110af, 0x0 },
	1589	+ { 0x2110af, 0x0 },
	1590	+ { 0x120ae, 0x0 },
	1591	+ { 0x1120ae, 0x0 },
	1592	+ { 0x2120ae, 0x0 },
	1593	+ { 0x120af, 0x0 },
	1594	+ { 0x1120af, 0x0 },
	1595	+ { 0x2120af, 0x0 },
	1596	+ { 0x130ae, 0x0 },
	1597	+ { 0x1130ae, 0x0 },
	1598	+ { 0x2130ae, 0x0 },
	1599	+ { 0x130af, 0x0 },
	1600	+ { 0x1130af, 0x0 },
	1601	+ { 0x2130af, 0x0 },
	1602	+ { 0x20020, 0x0 },
	1603	+ { 0x120020, 0x0 },
	1604	+ { 0x220020, 0x0 },
	1605	+ { 0x100a0, 0x0 },
	1606	+ { 0x100a1, 0x0 },
	1607	+ { 0x100a2, 0x0 },
	1608	+ { 0x100a3, 0x0 },
	1609	+ { 0x100a4, 0x0 },
	1610	+ { 0x100a5, 0x0 },
	1611	+ { 0x100a6, 0x0 },
	1612	+ { 0x100a7, 0x0 },
	1613	+ { 0x110a0, 0x0 },
	1614	+ { 0x110a1, 0x0 },
	1615	+ { 0x110a2, 0x0 },
	1616	+ { 0x110a3, 0x0 },
	1617	+ { 0x110a4, 0x0 },
	1618	+ { 0x110a5, 0x0 },
	1619	+ { 0x110a6, 0x0 },
	1620	+ { 0x110a7, 0x0 },
	1621	+ { 0x120a0, 0x0 },
	1622	+ { 0x120a1, 0x0 },
	1623	+ { 0x120a2, 0x0 },
	1624	+ { 0x120a3, 0x0 },
	1625	+ { 0x120a4, 0x0 },
	1626	+ { 0x120a5, 0x0 },
	1627	+ { 0x120a6, 0x0 },
	1628	+ { 0x120a7, 0x0 },
	1629	+ { 0x130a0, 0x0 },
	1630	+ { 0x130a1, 0x0 },
	1631	+ { 0x130a2, 0x0 },
	1632	+ { 0x130a3, 0x0 },
	1633	+ { 0x130a4, 0x0 },
	1634	+ { 0x130a5, 0x0 },
	1635	+ { 0x130a6, 0x0 },
	1636	+ { 0x130a7, 0x0 },
	1637	+ { 0x2007c, 0x0 },
	1638	+ { 0x12007c, 0x0 },
	1639	+ { 0x22007c, 0x0 },
	1640	+ { 0x2007d, 0x0 },
	1641	+ { 0x12007d, 0x0 },
	1642	+ { 0x22007d, 0x0 },
	1643	+ { 0x400fd, 0x0 },
	1644	+ { 0x400c0, 0x0 },
	1645	+ { 0x90201, 0x0 },
	1646	+ { 0x190201, 0x0 },
	1647	+ { 0x290201, 0x0 },
	1648	+ { 0x90202, 0x0 },
	1649	+ { 0x190202, 0x0 },
	1650	+ { 0x290202, 0x0 },
	1651	+ { 0x90203, 0x0 },
	1652	+ { 0x190203, 0x0 },
	1653	+ { 0x290203, 0x0 },
	1654	+ { 0x90204, 0x0 },
	1655	+ { 0x190204, 0x0 },
	1656	+ { 0x290204, 0x0 },
	1657	+ { 0x90205, 0x0 },
	1658	+ { 0x190205, 0x0 },
	1659	+ { 0x290205, 0x0 },
	1660	+ { 0x90206, 0x0 },
	1661	+ { 0x190206, 0x0 },
	1662	+ { 0x290206, 0x0 },
	1663	+ { 0x90207, 0x0 },
	1664	+ { 0x190207, 0x0 },
	1665	+ { 0x290207, 0x0 },
	1666	+ { 0x90208, 0x0 },
	1667	+ { 0x190208, 0x0 },
	1668	+ { 0x290208, 0x0 },
	1669	+ { 0x10062, 0x0 },
	1670	+ { 0x10162, 0x0 },
	1671	+ { 0x10262, 0x0 },
	1672	+ { 0x10362, 0x0 },
	1673	+ { 0x10462, 0x0 },
	1674	+ { 0x10562, 0x0 },
	1675	+ { 0x10662, 0x0 },
	1676	+ { 0x10762, 0x0 },
	1677	+ { 0x10862, 0x0 },
	1678	+ { 0x11062, 0x0 },
	1679	+ { 0x11162, 0x0 },
	1680	+ { 0x11262, 0x0 },
	1681	+ { 0x11362, 0x0 },
	1682	+ { 0x11462, 0x0 },
	1683	+ { 0x11562, 0x0 },
	1684	+ { 0x11662, 0x0 },
	1685	+ { 0x11762, 0x0 },
	1686	+ { 0x11862, 0x0 },
	1687	+ { 0x12062, 0x0 },
	1688	+ { 0x12162, 0x0 },
	1689	+ { 0x12262, 0x0 },
	1690	+ { 0x12362, 0x0 },
	1691	+ { 0x12462, 0x0 },
	1692	+ { 0x12562, 0x0 },
	1693	+ { 0x12662, 0x0 },
	1694	+ { 0x12762, 0x0 },
	1695	+ { 0x12862, 0x0 },
	1696	+ { 0x13062, 0x0 },
	1697	+ { 0x13162, 0x0 },
	1698	+ { 0x13262, 0x0 },
	1699	+ { 0x13362, 0x0 },
	1700	+ { 0x13462, 0x0 },
	1701	+ { 0x13562, 0x0 },
	1702	+ { 0x13662, 0x0 },
	1703	+ { 0x13762, 0x0 },
	1704	+ { 0x13862, 0x0 },
	1705	+ { 0x20077, 0x0 },
	1706	+ { 0x10001, 0x0 },
	1707	+ { 0x11001, 0x0 },
	1708	+ { 0x12001, 0x0 },
	1709	+ { 0x13001, 0x0 },
	1710	+ { 0x10040, 0x0 },
	1711	+ { 0x10140, 0x0 },
	1712	+ { 0x10240, 0x0 },
	1713	+ { 0x10340, 0x0 },
	1714	+ { 0x10440, 0x0 },
	1715	+ { 0x10540, 0x0 },
	1716	+ { 0x10640, 0x0 },
	1717	+ { 0x10740, 0x0 },
	1718	+ { 0x10840, 0x0 },
	1719	+ { 0x10030, 0x0 },
	1720	+ { 0x10130, 0x0 },
	1721	+ { 0x10230, 0x0 },
	1722	+ { 0x10330, 0x0 },
	1723	+ { 0x10430, 0x0 },
	1724	+ { 0x10530, 0x0 },
	1725	+ { 0x10630, 0x0 },
	1726	+ { 0x10730, 0x0 },
	1727	+ { 0x10830, 0x0 },
	1728	+ { 0x11040, 0x0 },
	1729	+ { 0x11140, 0x0 },
	1730	+ { 0x11240, 0x0 },
	1731	+ { 0x11340, 0x0 },
	1732	+ { 0x11440, 0x0 },
	1733	+ { 0x11540, 0x0 },
	1734	+ { 0x11640, 0x0 },
	1735	+ { 0x11740, 0x0 },
	1736	+ { 0x11840, 0x0 },
	1737	+ { 0x11030, 0x0 },
	1738	+ { 0x11130, 0x0 },
	1739	+ { 0x11230, 0x0 },
	1740	+ { 0x11330, 0x0 },
	1741	+ { 0x11430, 0x0 },
	1742	+ { 0x11530, 0x0 },
	1743	+ { 0x11630, 0x0 },
	1744	+ { 0x11730, 0x0 },
	1745	+ { 0x11830, 0x0 },
	1746	+ { 0x12040, 0x0 },
	1747	+ { 0x12140, 0x0 },
	1748	+ { 0x12240, 0x0 },
	1749	+ { 0x12340, 0x0 },
	1750	+ { 0x12440, 0x0 },
	1751	+ { 0x12540, 0x0 },
	1752	+ { 0x12640, 0x0 },
	1753	+ { 0x12740, 0x0 },
	1754	+ { 0x12840, 0x0 },
	1755	+ { 0x12030, 0x0 },
	1756	+ { 0x12130, 0x0 },
	1757	+ { 0x12230, 0x0 },
	1758	+ { 0x12330, 0x0 },
	1759	+ { 0x12430, 0x0 },
	1760	+ { 0x12530, 0x0 },
	1761	+ { 0x12630, 0x0 },
	1762	+ { 0x12730, 0x0 },
	1763	+ { 0x12830, 0x0 },
	1764	+ { 0x13040, 0x0 },
	1765	+ { 0x13140, 0x0 },
	1766	+ { 0x13240, 0x0 },
	1767	+ { 0x13340, 0x0 },
	1768	+ { 0x13440, 0x0 },
	1769	+ { 0x13540, 0x0 },
	1770	+ { 0x13640, 0x0 },
	1771	+ { 0x13740, 0x0 },
	1772	+ { 0x13840, 0x0 },
	1773	+ { 0x13030, 0x0 },
	1774	+ { 0x13130, 0x0 },
	1775	+ { 0x13230, 0x0 },
	1776	+ { 0x13330, 0x0 },
	1777	+ { 0x13430, 0x0 },
	1778	+ { 0x13530, 0x0 },
	1779	+ { 0x13630, 0x0 },
	1780	+ { 0x13730, 0x0 },
	1781	+ { 0x13830, 0x0 },
	1782	+};
	1783	+/* P0 message block paremeter for training firmware */
	1784	+struct dram_cfg_param ddr_fsp0_cfg[] = {
	1785	+ { 0xd0000, 0x0 },
	1786	+ { 0x54003, 0xc80 },
	1787	+ { 0x54004, 0x2 },
	1788	+ { 0x54005, 0x2230 },
	1789	+ { 0x54006, 0x25b },
	1790	+ { 0x54007, 0x2000 },
	1791	+ { 0x54008, 0x101 },
	1792	+ { 0x5400b, 0x31f },
	1793	+ { 0x5400c, 0xc8 },
	1794	+ { 0x5400d, 0x100 },
	1795	+ { 0x54012, 0x1 },
	1796	+ { 0x5402f, 0xc50 },
	1797	+ { 0x54030, 0x501 },
	1798	+ { 0x54031, 0x28 },
	1799	+ { 0x54032, 0x400 },
	1800	+ { 0x54033, 0x200 },
	1801	+ { 0x54034, 0x600 },
	1802	+ { 0x54035, 0x1010 },
	1803	+ { 0x54036, 0x101 },
	1804	+ { 0x5403f, 0x1221 },
	1805	+ { 0x541fc, 0x100 },
	1806	+ { 0xd0000, 0x1 },
	1807	+};
	1808	+
	1809	+
	1810	+/* P1 message block paremeter for training firmware */
	1811	+struct dram_cfg_param ddr_fsp1_cfg[] = {
	1812	+ { 0xd0000, 0x0 },
	1813	+ { 0x54002, 0x1 },
	1814	+ { 0x54003, 0x42a },
	1815	+ { 0x54004, 0x2 },
	1816	+ { 0x54005, 0x2230 },
	1817	+ { 0x54006, 0x25b },
	1818	+ { 0x54007, 0x2000 },
	1819	+ { 0x54008, 0x101 },
	1820	+ { 0x5400b, 0x21f },
	1821	+ { 0x5400c, 0xc8 },
	1822	+ { 0x5400d, 0x100 },
	1823	+ { 0x54012, 0x1 },
	1824	+ { 0x5402f, 0x4 },
	1825	+ { 0x54030, 0x501 },
	1826	+ { 0x54033, 0x200 },
	1827	+ { 0x54034, 0x600 },
	1828	+ { 0x54035, 0x10 },
	1829	+ { 0x54036, 0x101 },
	1830	+ { 0x5403f, 0x1221 },
	1831	+ { 0x541fc, 0x100 },
	1832	+ { 0xd0000, 0x1 },
	1833	+};
	1834	+
	1835	+
	1836	+/* P0 2D message block paremeter for training firmware */
	1837	+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
	1838	+ { 0xd0000, 0x0 },
	1839	+ { 0x54003, 0xc80 },
	1840	+ { 0x54004, 0x2 },
	1841	+ { 0x54005, 0x2230 },
	1842	+ { 0x54006, 0x25b },
	1843	+ { 0x54007, 0x2000 },
	1844	+ { 0x54008, 0x101 },
	1845	+ { 0x5400b, 0x61 },
	1846	+ { 0x5400c, 0xc8 },
	1847	+ { 0x5400d, 0x100 },
	1848	+ { 0x5400e, 0x1f7f },
	1849	+ { 0x54012, 0x1 },
	1850	+ { 0x5402f, 0xc50 },
	1851	+ { 0x54030, 0x501 },
	1852	+ { 0x54031, 0x28 },
	1853	+ { 0x54032, 0x400 },
	1854	+ { 0x54033, 0x200 },
	1855	+ { 0x54034, 0x600 },
	1856	+ { 0x54035, 0x1010 },
	1857	+ { 0x54036, 0x101 },
	1858	+ { 0x5403f, 0x1221 },
	1859	+ { 0x541fc, 0x100 },
	1860	+ { 0xd0000, 0x1 },
	1861	+};
	1862	+
	1863	+/* DRAM PHY init engine image */
	1864	+struct dram_cfg_param ddr_phy_pie[] = {
	1865	+ { 0xd0000, 0x0 },
	1866	+ { 0x90000, 0x10 },
	1867	+ { 0x90001, 0x400 },
	1868	+ { 0x90002, 0x10e },
	1869	+ { 0x90003, 0x0 },
	1870	+ { 0x90004, 0x0 },
	1871	+ { 0x90005, 0x8 },
	1872	+ { 0x90029, 0xb },
	1873	+ { 0x9002a, 0x480 },
	1874	+ { 0x9002b, 0x109 },
	1875	+ { 0x9002c, 0x8 },
	1876	+ { 0x9002d, 0x448 },
	1877	+ { 0x9002e, 0x139 },
	1878	+ { 0x9002f, 0x8 },
	1879	+ { 0x90030, 0x478 },
	1880	+ { 0x90031, 0x109 },
	1881	+ { 0x90032, 0x2 },
	1882	+ { 0x90033, 0x10 },
	1883	+ { 0x90034, 0x139 },
	1884	+ { 0x90035, 0xb },
	1885	+ { 0x90036, 0x7c0 },
	1886	+ { 0x90037, 0x139 },
	1887	+ { 0x90038, 0x44 },
	1888	+ { 0x90039, 0x633 },
	1889	+ { 0x9003a, 0x159 },
	1890	+ { 0x9003b, 0x14f },
	1891	+ { 0x9003c, 0x630 },
	1892	+ { 0x9003d, 0x159 },
	1893	+ { 0x9003e, 0x47 },
	1894	+ { 0x9003f, 0x633 },
	1895	+ { 0x90040, 0x149 },
	1896	+ { 0x90041, 0x4f },
	1897	+ { 0x90042, 0x633 },
	1898	+ { 0x90043, 0x179 },
	1899	+ { 0x90044, 0x8 },
	1900	+ { 0x90045, 0xe0 },
	1901	+ { 0x90046, 0x109 },
	1902	+ { 0x90047, 0x0 },
	1903	+ { 0x90048, 0x7c8 },
	1904	+ { 0x90049, 0x109 },
	1905	+ { 0x9004a, 0x0 },
	1906	+ { 0x9004b, 0x1 },
	1907	+ { 0x9004c, 0x8 },
	1908	+ { 0x9004d, 0x0 },
	1909	+ { 0x9004e, 0x45a },
	1910	+ { 0x9004f, 0x9 },
	1911	+ { 0x90050, 0x0 },
	1912	+ { 0x90051, 0x448 },
	1913	+ { 0x90052, 0x109 },
	1914	+ { 0x90053, 0x40 },
	1915	+ { 0x90054, 0x633 },
	1916	+ { 0x90055, 0x179 },
	1917	+ { 0x90056, 0x1 },
	1918	+ { 0x90057, 0x618 },
	1919	+ { 0x90058, 0x109 },
	1920	+ { 0x90059, 0x40c0 },
	1921	+ { 0x9005a, 0x633 },
	1922	+ { 0x9005b, 0x149 },
	1923	+ { 0x9005c, 0x8 },
	1924	+ { 0x9005d, 0x4 },
	1925	+ { 0x9005e, 0x48 },
	1926	+ { 0x9005f, 0x4040 },
	1927	+ { 0x90060, 0x633 },
	1928	+ { 0x90061, 0x149 },
	1929	+ { 0x90062, 0x0 },
	1930	+ { 0x90063, 0x4 },
	1931	+ { 0x90064, 0x48 },
	1932	+ { 0x90065, 0x40 },
	1933	+ { 0x90066, 0x633 },
	1934	+ { 0x90067, 0x149 },
	1935	+ { 0x90068, 0x10 },
	1936	+ { 0x90069, 0x4 },
	1937	+ { 0x9006a, 0x18 },
	1938	+ { 0x9006b, 0x0 },
	1939	+ { 0x9006c, 0x4 },
	1940	+ { 0x9006d, 0x78 },
	1941	+ { 0x9006e, 0x549 },
	1942	+ { 0x9006f, 0x633 },
	1943	+ { 0x90070, 0x159 },
	1944	+ { 0x90071, 0xd49 },
	1945	+ { 0x90072, 0x633 },
	1946	+ { 0x90073, 0x159 },
	1947	+ { 0x90074, 0x94a },
	1948	+ { 0x90075, 0x633 },
	1949	+ { 0x90076, 0x159 },
	1950	+ { 0x90077, 0x441 },
	1951	+ { 0x90078, 0x633 },
	1952	+ { 0x90079, 0x149 },
	1953	+ { 0x9007a, 0x42 },
	1954	+ { 0x9007b, 0x633 },
	1955	+ { 0x9007c, 0x149 },
	1956	+ { 0x9007d, 0x1 },
	1957	+ { 0x9007e, 0x633 },
	1958	+ { 0x9007f, 0x149 },
	1959	+ { 0x90080, 0x0 },
	1960	+ { 0x90081, 0xe0 },
	1961	+ { 0x90082, 0x109 },
	1962	+ { 0x90083, 0xa },
	1963	+ { 0x90084, 0x10 },
	1964	+ { 0x90085, 0x109 },
	1965	+ { 0x90086, 0x9 },
	1966	+ { 0x90087, 0x3c0 },
	1967	+ { 0x90088, 0x149 },
	1968	+ { 0x90089, 0x9 },
	1969	+ { 0x9008a, 0x3c0 },
	1970	+ { 0x9008b, 0x159 },
	1971	+ { 0x9008c, 0x18 },
	1972	+ { 0x9008d, 0x10 },
	1973	+ { 0x9008e, 0x109 },
	1974	+ { 0x9008f, 0x0 },
	1975	+ { 0x90090, 0x3c0 },
	1976	+ { 0x90091, 0x109 },
	1977	+ { 0x90092, 0x18 },
	1978	+ { 0x90093, 0x4 },
	1979	+ { 0x90094, 0x48 },
	1980	+ { 0x90095, 0x18 },
	1981	+ { 0x90096, 0x4 },
	1982	+ { 0x90097, 0x58 },
	1983	+ { 0x90098, 0xb },
	1984	+ { 0x90099, 0x10 },
	1985	+ { 0x9009a, 0x109 },
	1986	+ { 0x9009b, 0x1 },
	1987	+ { 0x9009c, 0x10 },
	1988	+ { 0x9009d, 0x109 },
	1989	+ { 0x9009e, 0x5 },
	1990	+ { 0x9009f, 0x7c0 },
	1991	+ { 0x900a0, 0x109 },
	1992	+ { 0x900a1, 0x0 },
	1993	+ { 0x900a2, 0x8140 },
	1994	+ { 0x900a3, 0x10c },
	1995	+ { 0x900a4, 0x10 },
	1996	+ { 0x900a5, 0x8138 },
	1997	+ { 0x900a6, 0x104 },
	1998	+ { 0x900a7, 0x8 },
	1999	+ { 0x900a8, 0x448 },
	2000	+ { 0x900a9, 0x109 },
	2001	+ { 0x900aa, 0xf },
	2002	+ { 0x900ab, 0x7c0 },
	2003	+ { 0x900ac, 0x109 },
	2004	+ { 0x900ad, 0x47 },
	2005	+ { 0x900ae, 0x630 },
	2006	+ { 0x900af, 0x109 },
	2007	+ { 0x900b0, 0x8 },
	2008	+ { 0x900b1, 0x618 },
	2009	+ { 0x900b2, 0x109 },
	2010	+ { 0x900b3, 0x8 },
	2011	+ { 0x900b4, 0xe0 },
	2012	+ { 0x900b5, 0x109 },
	2013	+ { 0x900b6, 0x0 },
	2014	+ { 0x900b7, 0x7c8 },
	2015	+ { 0x900b8, 0x109 },
	2016	+ { 0x900b9, 0x8 },
	2017	+ { 0x900ba, 0x8140 },
	2018	+ { 0x900bb, 0x10c },
	2019	+ { 0x900bc, 0x0 },
	2020	+ { 0x900bd, 0x478 },
	2021	+ { 0x900be, 0x109 },
	2022	+ { 0x900bf, 0x0 },
	2023	+ { 0x900c0, 0x1 },
	2024	+ { 0x900c1, 0x8 },
	2025	+ { 0x900c2, 0x8 },
	2026	+ { 0x900c3, 0x4 },
	2027	+ { 0x900c4, 0x0 },
	2028	+ { 0x90006, 0x8 },
	2029	+ { 0x90007, 0x7c8 },
	2030	+ { 0x90008, 0x109 },
	2031	+ { 0x90009, 0x0 },
	2032	+ { 0x9000a, 0x400 },
	2033	+ { 0x9000b, 0x106 },
	2034	+ { 0xd00e7, 0x400 },
	2035	+ { 0x90017, 0x0 },
	2036	+ { 0x90026, 0x2a },
	2037	+ { 0x2000b, 0x64 },
	2038	+ { 0x2000c, 0xc8 },
	2039	+ { 0x2000d, 0x7d0 },
	2040	+ { 0x2000e, 0x2c },
	2041	+ { 0x12000b, 0x21 },
	2042	+ { 0x12000c, 0x42 },
	2043	+ { 0x12000d, 0x29a },
	2044	+ { 0x12000e, 0x21 },
	2045	+ { 0x9000c, 0x0 },
	2046	+ { 0x9000d, 0x173 },
	2047	+ { 0x9000e, 0x60 },
	2048	+ { 0x9000f, 0x6110 },
	2049	+ { 0x90010, 0x2152 },
	2050	+ { 0x90011, 0xdfbd },
	2051	+ { 0x90012, 0xffff },
	2052	+ { 0x90013, 0x6152 },
	2053	+ { 0x20089, 0x1 },
	2054	+ { 0x20088, 0x19 },
	2055	+ { 0xc0080, 0x0 },
	2056	+ { 0xd0000, 0x1 }
	2057	+};
	2058	+
	2059	+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
	2060	+ {
	2061	+ /* P0 3200mts 1D */
	2062	+ .drate = 3200,
	2063	+ .fw_type = FW_1D_IMAGE,
	2064	+ .fsp_cfg = ddr_fsp0_cfg,
	2065	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
	2066	+ },
	2067	+ {
	2068	+ /* P1 1066mts 1D */
	2069	+ .drate = 1066,
	2070	+ .fw_type = FW_1D_IMAGE,
	2071	+ .fsp_cfg = ddr_fsp1_cfg,
	2072	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
	2073	+ },
	2074	+ {
	2075	+ /* P0 3200mts 2D */
	2076	+ .drate = 3200,
	2077	+ .fw_type = FW_2D_IMAGE,
	2078	+ .fsp_cfg = ddr_fsp0_2d_cfg,
	2079	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
	2080	+ },
	2081	+};
	2082	+
	2083	+/* ddr timing config params */
	2084	+struct dram_timing_info dram_timing = {
	2085	+ .ddrc_cfg = ddr_ddrc_cfg,
	2086	+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
	2087	+ .ddrphy_cfg = ddr_ddrphy_cfg,
	2088	+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
	2089	+ .fsp_msg = ddr_dram_fsp_msg,
	2090	+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
	2091	+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
	2092	+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
	2093	+ .ddrphy_pie = ddr_phy_pie,
	2094	+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
	2095	+ .fsp_table = { 3200, 1066, },
	2096	+};
	2097	+
	2098	+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
	2099	+void board_dram_ecc_scrub(void)
	2100	+{
	2101	+ ddrc_inline_ecc_scrub(0x0,0x7ffffff);
	2102	+ ddrc_inline_ecc_scrub(0x8000000,0xfffffff);
	2103	+ ddrc_inline_ecc_scrub(0x10000000,0x17ffffff);
	2104	+ ddrc_inline_ecc_scrub(0x18000000,0x1fffffff);
	2105	+ ddrc_inline_ecc_scrub(0x20000000,0x27ffffff);
	2106	+ ddrc_inline_ecc_scrub(0x28000000,0x2fffffff);
	2107	+ ddrc_inline_ecc_scrub(0x30000000,0x37ffffff);
	2108	+ ddrc_inline_ecc_scrub_end(0x0,0x3fffffff);
	2109	+}
	2110	+#endif
	2111	diff --git a/board/freescale/gauguin-imx8mp/gauguin-imx8mp.c b/board/freescale/gauguin-imx8mp/gauguin-imx8mp.c
	2112	new file mode 100644
	2113	index 00000000..5f5667b0
	2114	--- /dev/null
	2115	+++ b/board/freescale/gauguin-imx8mp/gauguin-imx8mp.c
	2116	@@ -0,0 +1,531 @@
	2117	+// SPDX-License-Identifier: GPL-2.0+
	2118	+/*
	2119	+ * Copyright 2019 NXP
	2120	+ */
	2121	+
	2122	+#include <common.h>
	2123	+#include <efi_loader.h>
	2124	+#include <env.h>
	2125	+#include <errno.h>
	2126	+#include <init.h>
	2127	+#include <miiphy.h>
	2128	+#include <netdev.h>
	2129	+#include <linux/delay.h>
	2130	+#include <asm/global_data.h>
	2131	+#include <asm/io.h>
	2132	+#include <asm/mach-imx/iomux-v3.h>
	2133	+#include <asm-generic/gpio.h>
	2134	+#include <asm/arch/imx8mp_pins.h>
	2135	+#include <asm/arch/clock.h>
	2136	+#include <asm/arch/sys_proto.h>
	2137	+#include <asm/mach-imx/gpio.h>
	2138	+#include <asm/mach-imx/mxc_i2c.h>
	2139	+#include <spl.h>
	2140	+#include <asm/mach-imx/dma.h>
	2141	+#include <power/pmic.h>
	2142	+#include "../common/tcpc.h"
	2143	+#include <usb.h>
	2144	+#include <dwc3-uboot.h>
	2145	+#include <imx_sip.h>
	2146	+#include <linux/arm-smccc.h>
	2147	+#include <mmc.h>
	2148	+
	2149	+DECLARE_GLOBAL_DATA_PTR;
	2150	+
	2151	+#define UART_PAD_CTRL (PAD_CTL_DSE6 \| PAD_CTL_FSEL1)
	2152	+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 \| PAD_CTL_ODE \| PAD_CTL_PUE \| PAD_CTL_PE)
	2153	+
	2154	+static iomux_v3_cfg_t const uart_pads[] = {
	2155	+ MX8MP_PAD_UART2_RXD__UART2_DCE_RX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	2156	+ MX8MP_PAD_UART2_TXD__UART2_DCE_TX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	2157	+};
	2158	+
	2159	+static iomux_v3_cfg_t const wdog_pads[] = {
	2160	+ MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B \| MUX_PAD_CTRL(WDOG_PAD_CTRL),
	2161	+};
	2162	+
	2163	+#ifdef CONFIG_NAND_MXS
	2164	+
	2165	+static void setup_gpmi_nand(void)
	2166	+{
	2167	+ init_nand_clk();
	2168	+}
	2169	+#endif
	2170	+
	2171	+#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
	2172	+struct efi_fw_image fw_images[] = {
	2173	+ {
	2174	+ .image_type_id = IMX_BOOT_IMAGE_GUID,
	2175	+ .fw_name = u"IMX8MP-EVK-RAW",
	2176	+ .image_index = 1,
	2177	+ },
	2178	+};
	2179	+
	2180	+struct efi_capsule_update_info update_info = {
	2181	+ .dfu_string = "mmc 2=flash-bin raw 0 0x2000 mmcpart 1",
	2182	+ .images = fw_images,
	2183	+};
	2184	+
	2185	+u8 num_image_type_guids = ARRAY_SIZE(fw_images);
	2186	+#endif /* EFI_HAVE_CAPSULE_SUPPORT */
	2187	+
	2188	+int board_early_init_f(void)
	2189	+{
	2190	+ struct wdog_regs wdog = (struct wdog_regs )WDOG1_BASE_ADDR;
	2191	+
	2192	+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
	2193	+
	2194	+ set_wdog_reset(wdog);
	2195	+
	2196	+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
	2197	+
	2198	+ init_uart_clk(1);
	2199	+
	2200	+ return 0;
	2201	+}
	2202	+
	2203	+#ifdef CONFIG_OF_BOARD_SETUP
	2204	+int ft_board_setup(void blob, struct bd_info bd)
	2205	+{
	2206	+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
	2207	+#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK
	2208	+ int rc;
	2209	+ phys_addr_t ecc_start = 0x120000000;
	2210	+ size_t ecc_size = 0x20000000;
	2211	+
	2212	+ rc = add_res_mem_dt_node(blob, "ecc", ecc_start, ecc_size);
	2213	+ if (rc < 0) {
	2214	+ printf("Could not create ecc reserved-memory node.\n");
	2215	+ return rc;
	2216	+ }
	2217	+#else
	2218	+ int rc;
	2219	+ phys_addr_t ecc0_start = 0xb0000000;
	2220	+ phys_addr_t ecc1_start = 0x130000000;
	2221	+ phys_addr_t ecc2_start = 0x1b0000000;
	2222	+ size_t ecc_size = 0x10000000;
	2223	+
	2224	+ rc = add_res_mem_dt_node(blob, "ecc", ecc0_start, ecc_size);
	2225	+ if (rc < 0) {
	2226	+ printf("Could not create ecc0 reserved-memory node.\n");
	2227	+ return rc;
	2228	+ }
	2229	+
	2230	+ rc = add_res_mem_dt_node(blob, "ecc", ecc1_start, ecc_size);
	2231	+ if (rc < 0) {
	2232	+ printf("Could not create ecc1 reserved-memory node.\n");
	2233	+ return rc;
	2234	+ }
	2235	+
	2236	+ rc = add_res_mem_dt_node(blob, "ecc", ecc2_start, ecc_size);
	2237	+ if (rc < 0) {
	2238	+ printf("Could not create ecc2 reserved-memory node.\n");
	2239	+ return rc;
	2240	+ }
	2241	+#endif
	2242	+#endif
	2243	+
	2244	+ return 0;
	2245	+}
	2246	+#endif
	2247	+
	2248	+#ifdef CONFIG_USB_TCPC
	2249	+struct tcpc_port port1;
	2250	+struct tcpc_port port2;
	2251	+
	2252	+static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr)
	2253	+{
	2254	+ struct udevice *bus;
	2255	+ struct udevice *i2c_dev = NULL;
	2256	+ int ret;
	2257	+ uint8_t valb;
	2258	+
	2259	+ ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus);
	2260	+ if (ret) {
	2261	+ printf("%s: Can't find bus\n", __func__);
	2262	+ return -EINVAL;
	2263	+ }
	2264	+
	2265	+ ret = dm_i2c_probe(bus, addr, 0, &i2c_dev);
	2266	+ if (ret) {
	2267	+ printf("%s: Can't find device id=0x%x\n",
	2268	+ __func__, addr);
	2269	+ return -ENODEV;
	2270	+ }
	2271	+
	2272	+ ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1);
	2273	+ if (ret) {
	2274	+ printf("%s dm_i2c_read failed, err %d\n", __func__, ret);
	2275	+ return -EIO;
	2276	+ }
	2277	+ valb \|= 0x4; /* Set DB_EXIT to exit dead battery mode */
	2278	+ ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1);
	2279	+ if (ret) {
	2280	+ printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
	2281	+ return -EIO;
	2282	+ }
	2283	+
	2284	+ /* Set OVP threshold to 23V */
	2285	+ valb = 0x6;
	2286	+ ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1);
	2287	+ if (ret) {
	2288	+ printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
	2289	+ return -EIO;
	2290	+ }
	2291	+
	2292	+ return 0;
	2293	+}
	2294	+
	2295	+int pd_switch_snk_enable(struct tcpc_port *port)
	2296	+{
	2297	+ if (port == &port1) {
	2298	+ debug("Setup pd switch on port 1\n");
	2299	+ return setup_pd_switch(1, 0x72);
	2300	+ } else
	2301	+ return -EINVAL;
	2302	+}
	2303	+
	2304	+/* Port2 is the power supply, port 1 does not support power */
	2305	+struct tcpc_port_config port1_config = {
	2306	+ .i2c_bus = 1, /i2c2/
	2307	+ .addr = 0x50,
	2308	+ .port_type = TYPEC_PORT_UFP,
	2309	+ .max_snk_mv = 20000,
	2310	+ .max_snk_ma = 3000,
	2311	+ .max_snk_mw = 45000,
	2312	+ .op_snk_mv = 15000,
	2313	+ .switch_setup_func = &pd_switch_snk_enable,
	2314	+ .disable_pd = true,
	2315	+};
	2316	+
	2317	+struct tcpc_port_config port2_config = {
	2318	+ .i2c_bus = 2, /i2c3/
	2319	+ .addr = 0x50,
	2320	+ .port_type = TYPEC_PORT_UFP,
	2321	+ .max_snk_mv = 20000,
	2322	+ .max_snk_ma = 3000,
	2323	+ .max_snk_mw = 45000,
	2324	+ .op_snk_mv = 15000,
	2325	+};
	2326	+
	2327	+#define USB_TYPEC_SEL IMX_GPIO_NR(4, 20)
	2328	+#define USB_TYPEC_EN IMX_GPIO_NR(2, 20)
	2329	+
	2330	+static iomux_v3_cfg_t ss_mux_gpio[] = {
	2331	+ MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	2332	+ MX8MP_PAD_SD2_WP__GPIO2_IO20 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	2333	+};
	2334	+
	2335	+void ss_mux_select(enum typec_cc_polarity pol)
	2336	+{
	2337	+ if (pol == TYPEC_POLARITY_CC1)
	2338	+ gpio_direction_output(USB_TYPEC_SEL, 0);
	2339	+ else
	2340	+ gpio_direction_output(USB_TYPEC_SEL, 1);
	2341	+}
	2342	+
	2343	+static int setup_typec(void)
	2344	+{
	2345	+ int ret;
	2346	+ struct gpio_desc per_12v_desc;
	2347	+
	2348	+ debug("tcpc_init port 2\n");
	2349	+ ret = tcpc_init(&port2, port2_config, NULL);
	2350	+ if (ret) {
	2351	+ printf("%s: tcpc port2 init failed, err=%d\n",
	2352	+ __func__, ret);
	2353	+ } else if (tcpc_pd_sink_check_charging(&port2)) {
	2354	+ printf("Power supply on USB2\n");
	2355	+
	2356	+ /* Enable PER 12V, any check before it? */
	2357	+ ret = dm_gpio_lookup_name("gpio@20_1", &per_12v_desc);
	2358	+ if (ret) {
	2359	+ printf("%s lookup gpio@20_1 failed ret = %d\n", __func__, ret);
	2360	+ return -ENODEV;
	2361	+ }
	2362	+
	2363	+ ret = dm_gpio_request(&per_12v_desc, "per_12v_en");
	2364	+ if (ret) {
	2365	+ printf("%s request per_12v failed ret = %d\n", __func__, ret);
	2366	+ return -EIO;
	2367	+ }
	2368	+
	2369	+ /* Enable PER 12V regulator */
	2370	+ dm_gpio_set_dir_flags(&per_12v_desc, GPIOD_IS_OUT \| GPIOD_IS_OUT_ACTIVE);
	2371	+ }
	2372	+
	2373	+ debug("tcpc_init port 1\n");
	2374	+ imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
	2375	+ gpio_request(USB_TYPEC_SEL, "typec_sel");
	2376	+ gpio_request(USB_TYPEC_EN, "typec_en");
	2377	+ gpio_direction_output(USB_TYPEC_EN, 0);
	2378	+
	2379	+ ret = tcpc_init(&port1, port1_config, &ss_mux_select);
	2380	+ if (ret) {
	2381	+ printf("%s: tcpc port1 init failed, err=%d\n",
	2382	+ __func__, ret);
	2383	+ } else {
	2384	+ return ret;
	2385	+ }
	2386	+
	2387	+ return ret;
	2388	+}
	2389	+#endif
	2390	+
	2391	+#ifdef CONFIG_USB_DWC3
	2392	+
	2393	+#define USB_PHY_CTRL0 0xF0040
	2394	+#define USB_PHY_CTRL0_REF_SSP_EN BIT(2)
	2395	+
	2396	+#define USB_PHY_CTRL1 0xF0044
	2397	+#define USB_PHY_CTRL1_RESET BIT(0)
	2398	+#define USB_PHY_CTRL1_COMMONONN BIT(1)
	2399	+#define USB_PHY_CTRL1_ATERESET BIT(3)
	2400	+#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19)
	2401	+#define USB_PHY_CTRL1_VDATDETENB0 BIT(20)
	2402	+
	2403	+#define USB_PHY_CTRL2 0xF0048
	2404	+#define USB_PHY_CTRL2_TXENABLEN0 BIT(8)
	2405	+
	2406	+#define USB_PHY_CTRL6 0xF0058
	2407	+
	2408	+#define HSIO_GPR_BASE (0x32F10000U)
	2409	+#define HSIO_GPR_REG_0 (HSIO_GPR_BASE)
	2410	+#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT (1)
	2411	+#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN (0x1U << HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT)
	2412	+
	2413	+
	2414	+static struct dwc3_device dwc3_device_data = {
	2415	+#ifdef CONFIG_SPL_BUILD
	2416	+ .maximum_speed = USB_SPEED_HIGH,
	2417	+#else
	2418	+ .maximum_speed = USB_SPEED_SUPER,
	2419	+#endif
	2420	+ .base = USB1_BASE_ADDR,
	2421	+ .dr_mode = USB_DR_MODE_PERIPHERAL,
	2422	+ .index = 0,
	2423	+ .power_down_scale = 2,
	2424	+};
	2425	+
	2426	+int usb_gadget_handle_interrupts(int index)
	2427	+{
	2428	+ dwc3_uboot_handle_interrupt(index);
	2429	+ return 0;
	2430	+}
	2431	+
	2432	+static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
	2433	+{
	2434	+ u32 RegData;
	2435	+
	2436	+ /* enable usb clock via hsio gpr */
	2437	+ RegData = readl(HSIO_GPR_REG_0);
	2438	+ RegData \|= HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN;
	2439	+ writel(RegData, HSIO_GPR_REG_0);
	2440	+
	2441	+ /* USB3.0 PHY signal fsel for 100M ref */
	2442	+ RegData = readl(dwc3->base + USB_PHY_CTRL0);
	2443	+ RegData = (RegData & 0xfffff81f) \| (0x2a<<5);
	2444	+ writel(RegData, dwc3->base + USB_PHY_CTRL0);
	2445	+
	2446	+ RegData = readl(dwc3->base + USB_PHY_CTRL6);
	2447	+ RegData &=~0x1;
	2448	+ writel(RegData, dwc3->base + USB_PHY_CTRL6);
	2449	+
	2450	+ RegData = readl(dwc3->base + USB_PHY_CTRL1);
	2451	+ RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 \| USB_PHY_CTRL1_VDATDETENB0 \|
	2452	+ USB_PHY_CTRL1_COMMONONN);
	2453	+ RegData \|= USB_PHY_CTRL1_RESET \| USB_PHY_CTRL1_ATERESET;
	2454	+ writel(RegData, dwc3->base + USB_PHY_CTRL1);
	2455	+
	2456	+ RegData = readl(dwc3->base + USB_PHY_CTRL0);
	2457	+ RegData \|= USB_PHY_CTRL0_REF_SSP_EN;
	2458	+ writel(RegData, dwc3->base + USB_PHY_CTRL0);
	2459	+
	2460	+ RegData = readl(dwc3->base + USB_PHY_CTRL2);
	2461	+ RegData \|= USB_PHY_CTRL2_TXENABLEN0;
	2462	+ writel(RegData, dwc3->base + USB_PHY_CTRL2);
	2463	+
	2464	+ RegData = readl(dwc3->base + USB_PHY_CTRL1);
	2465	+ RegData &= ~(USB_PHY_CTRL1_RESET \| USB_PHY_CTRL1_ATERESET);
	2466	+ writel(RegData, dwc3->base + USB_PHY_CTRL1);
	2467	+}
	2468	+#endif
	2469	+
	2470	+#if defined(CONFIG_USB_DWC3) \|\| defined(CONFIG_USB_XHCI_IMX8M)
	2471	+#define USB2_PWR_EN IMX_GPIO_NR(1, 14)
	2472	+int board_usb_init(int index, enum usb_init_type init)
	2473	+{
	2474	+ int ret = 0;
	2475	+ imx8m_usb_power(index, true);
	2476	+
	2477	+ if (index == 0 && init == USB_INIT_DEVICE) {
	2478	+#ifdef CONFIG_USB_TCPC
	2479	+ ret = tcpc_setup_ufp_mode(&port1);
	2480	+ if (ret)
	2481	+ return ret;
	2482	+#endif
	2483	+ dwc3_nxp_usb_phy_init(&dwc3_device_data);
	2484	+ return dwc3_uboot_init(&dwc3_device_data);
	2485	+ } else if (index == 0 && init == USB_INIT_HOST) {
	2486	+#ifdef CONFIG_USB_TCPC
	2487	+ ret = tcpc_setup_dfp_mode(&port1);
	2488	+#endif
	2489	+ return ret;
	2490	+ }
	2491	+
	2492	+ return 0;
	2493	+}
	2494	+
	2495	+int board_usb_cleanup(int index, enum usb_init_type init)
	2496	+{
	2497	+ int ret = 0;
	2498	+ if (index == 0 && init == USB_INIT_DEVICE) {
	2499	+ dwc3_uboot_exit(index);
	2500	+ } else if (index == 0 && init == USB_INIT_HOST) {
	2501	+#ifdef CONFIG_USB_TCPC
	2502	+ ret = tcpc_disable_src_vbus(&port1);
	2503	+#endif
	2504	+ }
	2505	+
	2506	+ imx8m_usb_power(index, false);
	2507	+
	2508	+ return ret;
	2509	+}
	2510	+
	2511	+#ifdef CONFIG_USB_TCPC
	2512	+/* Not used so far */
	2513	+int board_typec_get_mode(int index)
	2514	+{
	2515	+ int ret = 0;
	2516	+ enum typec_cc_polarity pol;
	2517	+ enum typec_cc_state state;
	2518	+
	2519	+ if (index == 0) {
	2520	+ tcpc_setup_ufp_mode(&port1);
	2521	+
	2522	+ ret = tcpc_get_cc_status(&port1, &pol, &state);
	2523	+ if (!ret) {
	2524	+ if (state == TYPEC_STATE_SRC_RD_RA \|\| state == TYPEC_STATE_SRC_RD)
	2525	+ return USB_INIT_HOST;
	2526	+ }
	2527	+
	2528	+ return USB_INIT_DEVICE;
	2529	+ } else {
	2530	+ return USB_INIT_HOST;
	2531	+ }
	2532	+}
	2533	+#endif
	2534	+#endif
	2535	+
	2536	+static void setup_fec(void)
	2537	+{
	2538	+ struct iomuxc_gpr_base_regs *gpr =
	2539	+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
	2540	+
	2541	+ /* Enable RGMII TX clk output */
	2542	+ setbits_le32(&gpr->gpr[1], BIT(22));
	2543	+}
	2544	+
	2545	+static int setup_eqos(void)
	2546	+{
	2547	+ struct iomuxc_gpr_base_regs *gpr =
	2548	+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
	2549	+
	2550	+ /* set INTF as RGMII, enable RGMII TXC clock */
	2551	+ clrsetbits_le32(&gpr->gpr[1],
	2552	+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
	2553	+ setbits_le32(&gpr->gpr[1], BIT(19) \| BIT(21));
	2554	+
	2555	+ return set_clk_eqos(ENET_125MHZ);
	2556	+}
	2557	+
	2558	+#if CONFIG_IS_ENABLED(NET)
	2559	+int board_phy_config(struct phy_device *phydev)
	2560	+{
	2561	+ if (phydev->drv->config)
	2562	+ phydev->drv->config(phydev);
	2563	+ return 0;
	2564	+}
	2565	+#endif
	2566	+
	2567	+#define DISPMIX 13
	2568	+#define MIPI 15
	2569	+
	2570	+int board_init(void)
	2571	+{
	2572	+ struct arm_smccc_res res;
	2573	+
	2574	+#ifdef CONFIG_USB_TCPC
	2575	+ setup_typec();
	2576	+
	2577	+ /* Enable USB power default */
	2578	+ imx8m_usb_power(0, true);
	2579	+ imx8m_usb_power(1, true);
	2580	+#endif
	2581	+
	2582	+ if (CONFIG_IS_ENABLED(FEC_MXC)) {
	2583	+ setup_fec();
	2584	+ }
	2585	+
	2586	+ if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) {
	2587	+ setup_eqos();
	2588	+ }
	2589	+
	2590	+#ifdef CONFIG_NAND_MXS
	2591	+ setup_gpmi_nand();
	2592	+#endif
	2593	+
	2594	+#if defined(CONFIG_USB_DWC3) \|\| defined(CONFIG_USB_XHCI_IMX8M)
	2595	+ init_usb_clk();
	2596	+#endif
	2597	+
	2598	+ /* enable the dispmix & mipi phy power domain */
	2599	+ arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN,
	2600	+ DISPMIX, true, 0, 0, 0, 0, &res);
	2601	+ arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN,
	2602	+ MIPI, true, 0, 0, 0, 0, &res);
	2603	+
	2604	+ return 0;
	2605	+}
	2606	+
	2607	+int board_late_init(void)
	2608	+{
	2609	+#ifdef CONFIG_ENV_IS_IN_MMC
	2610	+ board_late_mmc_env_init();
	2611	+#endif
	2612	+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	2613	+ env_set("board_name", "IGKBoard");
	2614	+ env_set("board_rev", "iMX8MP");
	2615	+#endif
	2616	+
	2617	+ return 0;
	2618	+}
	2619	+
	2620	+#ifdef CONFIG_ANDROID_SUPPORT
	2621	+bool is_power_key_pressed(void) {
	2622	+ return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6)));
	2623	+}
	2624	+#endif
	2625	+
	2626	+#ifdef CONFIG_SPL_MMC
	2627	+#define UBOOT_RAW_SECTOR_OFFSET 0x40
	2628	+unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc)
	2629	+{
	2630	+ u32 boot_dev = spl_boot_device();
	2631	+ switch (boot_dev) {
	2632	+ case BOOT_DEVICE_MMC2:
	2633	+ return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET;
	2634	+ default:
	2635	+ return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
	2636	+ }
	2637	+}
	2638	+#endif
	2639	+
	2640	+#ifdef CONFIG_FSL_FASTBOOT
	2641	+#ifdef CONFIG_ANDROID_RECOVERY
	2642	+int is_recovery_key_pressing(void)
	2643	+{
	2644	+ return 0; /* TODO */
	2645	+}
	2646	+#endif /* CONFIG_ANDROID_RECOVERY */
	2647	+#endif /* CONFIG_FSL_FASTBOOT */
	2648	diff --git a/board/freescale/gauguin-imx8mp/imximage-8mp-lpddr4.cfg b/board/freescale/gauguin-imx8mp/imximage-8mp-lpddr4.cfg
	2649	new file mode 100644
	2650	index 00000000..6dedf172
	2651	--- /dev/null
	2652	+++ b/board/freescale/gauguin-imx8mp/imximage-8mp-lpddr4.cfg
	2653	@@ -0,0 +1,9 @@
	2654	+/* SPDX-License-Identifier: GPL-2.0+ */
	2655	+/*
	2656	+ * Copyright 2021 NXP
	2657	+ */
	2658	+
	2659	+
	2660	+ROM_VERSION v2
	2661	+BOOT_FROM sd
	2662	+LOADER u-boot-spl-ddr.bin 0x920000
	2663	diff --git a/board/freescale/gauguin-imx8mp/lpddr4_timing.c b/board/freescale/gauguin-imx8mp/lpddr4_timing.c
	2664	new file mode 100644
	2665	index 00000000..8c5306d5
	2666	--- /dev/null
	2667	+++ b/board/freescale/gauguin-imx8mp/lpddr4_timing.c
	2668	@@ -0,0 +1,2048 @@
	2669	+// SPDX-License-Identifier: GPL-2.0+
	2670	+/*
	2671	+ * Copyright 2019 NXP
	2672	+ */
	2673	+
	2674	+#include <linux/kernel.h>
	2675	+#include <asm/arch/ddr.h>
	2676	+
	2677	+struct dram_cfg_param ddr_ddrc_cfg[] = {
	2678	+ / Initialize DDRC registers /
	2679	+ { 0x3d400304, 0x1 },
	2680	+ { 0x3d400030, 0x1 },
	2681	+ { 0x3d400000, 0xa3080020 },
	2682	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	2683	+ { 0x3d400020, 0x223 },
	2684	+ { 0x3d400024, 0x124f800 },
	2685	+ { 0x3d400064, 0x4900a8 },
	2686	+ { 0x3d400070, 0x1027f90 },
	2687	+ { 0x3d400074, 0x790 },
	2688	+ { 0x3d4000d0, 0xc0030495 },
	2689	+ { 0x3d4000d4, 0x770000 },
	2690	+ { 0x3d4000dc, 0xc40024 },
	2691	+#else
	2692	+ { 0x3d400020, 0x1323 },
	2693	+ { 0x3d400024, 0x1e84800 },
	2694	+ { 0x3d400064, 0x7a017c },
	2695	+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
	2696	+ { 0x3d400070, 0x1027f54 },
	2697	+#else
	2698	+ { 0x3d400070, 0x1027f10 },
	2699	+#endif
	2700	+ { 0x3d400074, 0x7b0 },
	2701	+ { 0x3d4000d0, 0xc00307a3 },
	2702	+ { 0x3d4000d4, 0xc50000 },
	2703	+ { 0x3d4000dc, 0xf4003f },
	2704	+#endif
	2705	+ { 0x3d4000e0, 0x330000 },
	2706	+ { 0x3d4000e8, 0x660048 },
	2707	+ { 0x3d4000ec, 0x160048 },
	2708	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	2709	+ { 0x3d400100, 0x1618141a },
	2710	+ { 0x3d400104, 0x504a6 },
	2711	+ { 0x3d40010c, 0x909000 },
	2712	+ { 0x3d400110, 0xb04060b },
	2713	+ { 0x3d400114, 0x2030909 },
	2714	+ { 0x3d400118, 0x1010006 },
	2715	+ { 0x3d40011c, 0x301 },
	2716	+ { 0x3d400130, 0x20500 },
	2717	+ { 0x3d400134, 0xb100002 },
	2718	+ { 0x3d400138, 0xad },
	2719	+ { 0x3d400144, 0x78003c },
	2720	+ { 0x3d400180, 0x2580012 },
	2721	+ { 0x3d400184, 0x1e0493e },
	2722	+ { 0x3d400188, 0x0 },
	2723	+ { 0x3d400190, 0x4938208 },
	2724	+ { 0x3d400194, 0x80303 },
	2725	+ { 0x3d4001b4, 0x1308 },
	2726	+#else
	2727	+ { 0x3d400100, 0x2028222a },
	2728	+ { 0x3d400104, 0x807bf },
	2729	+ { 0x3d40010c, 0xe0e000 },
	2730	+ { 0x3d400110, 0x12040a12 },
	2731	+ { 0x3d400114, 0x2050f0f },
	2732	+ { 0x3d400118, 0x1010009 },
	2733	+ { 0x3d40011c, 0x501 },
	2734	+ { 0x3d400130, 0x20800 },
	2735	+ { 0x3d400134, 0xe100002 },
	2736	+ { 0x3d400138, 0x184 },
	2737	+ { 0x3d400144, 0xc80064 },
	2738	+ { 0x3d400180, 0x3e8001e },
	2739	+ { 0x3d400184, 0x3207a12 },
	2740	+ { 0x3d400188, 0x0 },
	2741	+ { 0x3d400190, 0x49f820e },
	2742	+ { 0x3d400194, 0x80303 },
	2743	+ { 0x3d4001b4, 0x1f0e },
	2744	+#endif
	2745	+ { 0x3d4001a0, 0xe0400018 },
	2746	+ { 0x3d4001a4, 0xdf00e4 },
	2747	+ { 0x3d4001a8, 0x80000000 },
	2748	+ { 0x3d4001b0, 0x11 },
	2749	+ { 0x3d4001c0, 0x1 },
	2750	+ { 0x3d4001c4, 0x1 },
	2751	+ { 0x3d4000f4, 0xc99 },
	2752	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	2753	+ { 0x3d400108, 0x60c1514 },
	2754	+ { 0x3d400200, 0x16 },
	2755	+ { 0x3d40020c, 0x0 },
	2756	+ { 0x3d400210, 0x1f1f },
	2757	+ { 0x3d400204, 0x80808 },
	2758	+ { 0x3d400214, 0x7070707 },
	2759	+ { 0x3d400218, 0x68070707 },
	2760	+ { 0x3d40021c, 0xf08 },
	2761	+ { 0x3d400250, 0x1f05 },
	2762	+ { 0x3d400254, 0x1f },
	2763	+ { 0x3d400264, 0x90003ff },
	2764	+ { 0x3d40026c, 0x20003ff },
	2765	+ { 0x3d400400, 0x111 },
	2766	+ { 0x3d400408, 0x72ff },
	2767	+ { 0x3d400494, 0x1000e00 },
	2768	+ { 0x3d400498, 0x3ff0000 },
	2769	+ { 0x3d40049c, 0x1000e00 },
	2770	+ { 0x3d4004a0, 0x3ff0000 },
	2771	+ { 0x3d402020, 0x21 },
	2772	+ { 0x3d402024, 0x30d400 },
	2773	+ { 0x3d402050, 0x20d000 },
	2774	+ { 0x3d402064, 0xc001c },
	2775	+#else
	2776	+ { 0x3d400108, 0x9121c1c },
	2777	+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
	2778	+ { 0x3d400200, 0x13 },
	2779	+ { 0x3d40020c, 0x13131300 },
	2780	+ { 0x3d400210, 0x1f1f },
	2781	+ { 0x3d400204, 0x50505 },
	2782	+ { 0x3d400214, 0x4040404 },
	2783	+ { 0x3d400218, 0x68040404 },
	2784	+#else
	2785	+ { 0x3d400200, 0x16 },
	2786	+ { 0x3d40020c, 0x0 },
	2787	+ { 0x3d400210, 0x1f1f },
	2788	+ { 0x3d400204, 0x80808 },
	2789	+ { 0x3d400214, 0x7070707 },
	2790	+ { 0x3d400218, 0x68070707 },
	2791	+#endif
	2792	+ { 0x3d40021c, 0xf08 },
	2793	+ { 0x3d400250, 0x1705 },
	2794	+ { 0x3d400254, 0x2c },
	2795	+ { 0x3d40025c, 0x4000030 },
	2796	+ { 0x3d400264, 0x900093e7 },
	2797	+ { 0x3d40026c, 0x2005574 },
	2798	+ { 0x3d400400, 0x111 },
	2799	+ { 0x3d400404, 0x72ff },
	2800	+ { 0x3d400408, 0x72ff },
	2801	+ { 0x3d400494, 0x2100e07 },
	2802	+ { 0x3d400498, 0x620096 },
	2803	+ { 0x3d40049c, 0x1100e07 },
	2804	+ { 0x3d4004a0, 0xc8012c },
	2805	+ { 0x3d402020, 0x1021 },
	2806	+ { 0x3d402024, 0x30d400 },
	2807	+ { 0x3d402050, 0x20d000 },
	2808	+ { 0x3d402064, 0xc0026 },
	2809	+#endif
	2810	+ { 0x3d4020dc, 0x840000 },
	2811	+ { 0x3d4020e0, 0x330000 },
	2812	+ { 0x3d4020e8, 0x660048 },
	2813	+ { 0x3d4020ec, 0x160048 },
	2814	+ { 0x3d402100, 0xa040305 },
	2815	+ { 0x3d402104, 0x30407 },
	2816	+ { 0x3d402108, 0x203060b },
	2817	+ { 0x3d40210c, 0x505000 },
	2818	+ { 0x3d402110, 0x2040202 },
	2819	+ { 0x3d402114, 0x2030202 },
	2820	+ { 0x3d402118, 0x1010004 },
	2821	+ { 0x3d40211c, 0x301 },
	2822	+ { 0x3d402130, 0x20300 },
	2823	+ { 0x3d402134, 0xa100002 },
	2824	+ { 0x3d402138, 0x27 },
	2825	+ { 0x3d402144, 0x14000a },
	2826	+ { 0x3d402180, 0x640004 },
	2827	+ { 0x3d402190, 0x3818200 },
	2828	+ { 0x3d402194, 0x80303 },
	2829	+ { 0x3d4021b4, 0x100 },
	2830	+ { 0x3d4020f4, 0xc99 },
	2831	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	2832	+ { 0x3d403020, 0x21 },
	2833	+ { 0x3d403024, 0xc3500 },
	2834	+ { 0x3d403050, 0x20d000 },
	2835	+ { 0x3d403064, 0x30007 },
	2836	+#else
	2837	+ { 0x3d403020, 0x1021 },
	2838	+ { 0x3d403024, 0xc3500 },
	2839	+ { 0x3d403050, 0x20d000 },
	2840	+ { 0x3d403064, 0x3000a },
	2841	+#endif
	2842	+ { 0x3d4030dc, 0x840000 },
	2843	+ { 0x3d4030e0, 0x330000 },
	2844	+ { 0x3d4030e8, 0x660048 },
	2845	+ { 0x3d4030ec, 0x160048 },
	2846	+ { 0x3d403100, 0xa010102 },
	2847	+ { 0x3d403104, 0x30404 },
	2848	+ { 0x3d403108, 0x203060b },
	2849	+ { 0x3d40310c, 0x505000 },
	2850	+ { 0x3d403110, 0x2040202 },
	2851	+ { 0x3d403114, 0x2030202 },
	2852	+ { 0x3d403118, 0x1010004 },
	2853	+ { 0x3d40311c, 0x301 },
	2854	+ { 0x3d403130, 0x20300 },
	2855	+ { 0x3d403134, 0xa100002 },
	2856	+ { 0x3d403138, 0xa },
	2857	+ { 0x3d403144, 0x50003 },
	2858	+ { 0x3d403180, 0x190004 },
	2859	+ { 0x3d403190, 0x3818200 },
	2860	+ { 0x3d403194, 0x80303 },
	2861	+ { 0x3d4031b4, 0x100 },
	2862	+ { 0x3d4030f4, 0xc99 },
	2863	+ { 0x3d400028, 0x0 },
	2864	+};
	2865	+
	2866	+/* PHY Initialize Configuration */
	2867	+struct dram_cfg_param ddr_ddrphy_cfg[] = {
	2868	+ { 0x100a0, 0x0 },
	2869	+ { 0x100a1, 0x1 },
	2870	+ { 0x100a2, 0x2 },
	2871	+ { 0x100a3, 0x3 },
	2872	+ { 0x100a4, 0x4 },
	2873	+ { 0x100a5, 0x5 },
	2874	+ { 0x100a6, 0x6 },
	2875	+ { 0x100a7, 0x7 },
	2876	+ { 0x110a0, 0x0 },
	2877	+ { 0x110a1, 0x1 },
	2878	+ { 0x110a2, 0x3 },
	2879	+ { 0x110a3, 0x4 },
	2880	+ { 0x110a4, 0x5 },
	2881	+ { 0x110a5, 0x2 },
	2882	+ { 0x110a6, 0x7 },
	2883	+ { 0x110a7, 0x6 },
	2884	+ { 0x120a0, 0x0 },
	2885	+ { 0x120a1, 0x1 },
	2886	+ { 0x120a2, 0x3 },
	2887	+ { 0x120a3, 0x2 },
	2888	+ { 0x120a4, 0x5 },
	2889	+ { 0x120a5, 0x4 },
	2890	+ { 0x120a6, 0x7 },
	2891	+ { 0x120a7, 0x6 },
	2892	+ { 0x130a0, 0x0 },
	2893	+ { 0x130a1, 0x1 },
	2894	+ { 0x130a2, 0x2 },
	2895	+ { 0x130a3, 0x3 },
	2896	+ { 0x130a4, 0x4 },
	2897	+ { 0x130a5, 0x5 },
	2898	+ { 0x130a6, 0x6 },
	2899	+ { 0x130a7, 0x7 },
	2900	+ { 0x1005f, 0x1ff },
	2901	+ { 0x1015f, 0x1ff },
	2902	+ { 0x1105f, 0x1ff },
	2903	+ { 0x1115f, 0x1ff },
	2904	+ { 0x1205f, 0x1ff },
	2905	+ { 0x1215f, 0x1ff },
	2906	+ { 0x1305f, 0x1ff },
	2907	+ { 0x1315f, 0x1ff },
	2908	+ { 0x11005f, 0x1ff },
	2909	+ { 0x11015f, 0x1ff },
	2910	+ { 0x11105f, 0x1ff },
	2911	+ { 0x11115f, 0x1ff },
	2912	+ { 0x11205f, 0x1ff },
	2913	+ { 0x11215f, 0x1ff },
	2914	+ { 0x11305f, 0x1ff },
	2915	+ { 0x11315f, 0x1ff },
	2916	+ { 0x21005f, 0x1ff },
	2917	+ { 0x21015f, 0x1ff },
	2918	+ { 0x21105f, 0x1ff },
	2919	+ { 0x21115f, 0x1ff },
	2920	+ { 0x21205f, 0x1ff },
	2921	+ { 0x21215f, 0x1ff },
	2922	+ { 0x21305f, 0x1ff },
	2923	+ { 0x21315f, 0x1ff },
	2924	+ { 0x55, 0x1ff },
	2925	+ { 0x1055, 0x1ff },
	2926	+ { 0x2055, 0x1ff },
	2927	+ { 0x3055, 0x1ff },
	2928	+ { 0x4055, 0x1ff },
	2929	+ { 0x5055, 0x1ff },
	2930	+ { 0x6055, 0x1ff },
	2931	+ { 0x7055, 0x1ff },
	2932	+ { 0x8055, 0x1ff },
	2933	+ { 0x9055, 0x1ff },
	2934	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	2935	+ { 0x200c5, 0xa },
	2936	+#else
	2937	+ { 0x200c5, 0x18 },
	2938	+#endif
	2939	+ { 0x1200c5, 0x7 },
	2940	+ { 0x2200c5, 0x7 },
	2941	+ { 0x2002e, 0x2 },
	2942	+ { 0x12002e, 0x2 },
	2943	+ { 0x22002e, 0x2 },
	2944	+ { 0x90204, 0x0 },
	2945	+ { 0x190204, 0x0 },
	2946	+ { 0x290204, 0x0 },
	2947	+ { 0x20024, 0x1e3 },
	2948	+ { 0x2003a, 0x2 },
	2949	+ { 0x120024, 0x1e3 },
	2950	+ { 0x2003a, 0x2 },
	2951	+ { 0x220024, 0x1e3 },
	2952	+ { 0x2003a, 0x2 },
	2953	+ { 0x20056, 0x3 },
	2954	+ { 0x120056, 0x3 },
	2955	+ { 0x220056, 0x3 },
	2956	+ { 0x1004d, 0xe00 },
	2957	+ { 0x1014d, 0xe00 },
	2958	+ { 0x1104d, 0xe00 },
	2959	+ { 0x1114d, 0xe00 },
	2960	+ { 0x1204d, 0xe00 },
	2961	+ { 0x1214d, 0xe00 },
	2962	+ { 0x1304d, 0xe00 },
	2963	+ { 0x1314d, 0xe00 },
	2964	+ { 0x11004d, 0xe00 },
	2965	+ { 0x11014d, 0xe00 },
	2966	+ { 0x11104d, 0xe00 },
	2967	+ { 0x11114d, 0xe00 },
	2968	+ { 0x11204d, 0xe00 },
	2969	+ { 0x11214d, 0xe00 },
	2970	+ { 0x11304d, 0xe00 },
	2971	+ { 0x11314d, 0xe00 },
	2972	+ { 0x21004d, 0xe00 },
	2973	+ { 0x21014d, 0xe00 },
	2974	+ { 0x21104d, 0xe00 },
	2975	+ { 0x21114d, 0xe00 },
	2976	+ { 0x21204d, 0xe00 },
	2977	+ { 0x21214d, 0xe00 },
	2978	+ { 0x21304d, 0xe00 },
	2979	+ { 0x21314d, 0xe00 },
	2980	+ { 0x10049, 0xeba },
	2981	+ { 0x10149, 0xeba },
	2982	+ { 0x11049, 0xeba },
	2983	+ { 0x11149, 0xeba },
	2984	+ { 0x12049, 0xeba },
	2985	+ { 0x12149, 0xeba },
	2986	+ { 0x13049, 0xeba },
	2987	+ { 0x13149, 0xeba },
	2988	+ { 0x110049, 0xeba },
	2989	+ { 0x110149, 0xeba },
	2990	+ { 0x111049, 0xeba },
	2991	+ { 0x111149, 0xeba },
	2992	+ { 0x112049, 0xeba },
	2993	+ { 0x112149, 0xeba },
	2994	+ { 0x113049, 0xeba },
	2995	+ { 0x113149, 0xeba },
	2996	+ { 0x210049, 0xeba },
	2997	+ { 0x210149, 0xeba },
	2998	+ { 0x211049, 0xeba },
	2999	+ { 0x211149, 0xeba },
	3000	+ { 0x212049, 0xeba },
	3001	+ { 0x212149, 0xeba },
	3002	+ { 0x213049, 0xeba },
	3003	+ { 0x213149, 0xeba },
	3004	+ { 0x43, 0x63 },
	3005	+ { 0x1043, 0x63 },
	3006	+ { 0x2043, 0x63 },
	3007	+ { 0x3043, 0x63 },
	3008	+ { 0x4043, 0x63 },
	3009	+ { 0x5043, 0x63 },
	3010	+ { 0x6043, 0x63 },
	3011	+ { 0x7043, 0x63 },
	3012	+ { 0x8043, 0x63 },
	3013	+ { 0x9043, 0x63 },
	3014	+ { 0x20018, 0x3 },
	3015	+ { 0x20075, 0x4 },
	3016	+ { 0x20050, 0x0 },
	3017	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	3018	+ { 0x20008, 0x258 },
	3019	+#else
	3020	+ { 0x20008, 0x3e8 },
	3021	+#endif
	3022	+ { 0x120008, 0x64 },
	3023	+ { 0x220008, 0x19 },
	3024	+ { 0x20088, 0x9 },
	3025	+ { 0x200b2, 0x104 },
	3026	+ { 0x10043, 0x5a1 },
	3027	+ { 0x10143, 0x5a1 },
	3028	+ { 0x11043, 0x5a1 },
	3029	+ { 0x11143, 0x5a1 },
	3030	+ { 0x12043, 0x5a1 },
	3031	+ { 0x12143, 0x5a1 },
	3032	+ { 0x13043, 0x5a1 },
	3033	+ { 0x13143, 0x5a1 },
	3034	+ { 0x1200b2, 0x104 },
	3035	+ { 0x110043, 0x5a1 },
	3036	+ { 0x110143, 0x5a1 },
	3037	+ { 0x111043, 0x5a1 },
	3038	+ { 0x111143, 0x5a1 },
	3039	+ { 0x112043, 0x5a1 },
	3040	+ { 0x112143, 0x5a1 },
	3041	+ { 0x113043, 0x5a1 },
	3042	+ { 0x113143, 0x5a1 },
	3043	+ { 0x2200b2, 0x104 },
	3044	+ { 0x210043, 0x5a1 },
	3045	+ { 0x210143, 0x5a1 },
	3046	+ { 0x211043, 0x5a1 },
	3047	+ { 0x211143, 0x5a1 },
	3048	+ { 0x212043, 0x5a1 },
	3049	+ { 0x212143, 0x5a1 },
	3050	+ { 0x213043, 0x5a1 },
	3051	+ { 0x213143, 0x5a1 },
	3052	+ { 0x200fa, 0x1 },
	3053	+ { 0x1200fa, 0x1 },
	3054	+ { 0x2200fa, 0x1 },
	3055	+ { 0x20019, 0x1 },
	3056	+ { 0x120019, 0x1 },
	3057	+ { 0x220019, 0x1 },
	3058	+ { 0x200f0, 0x660 },
	3059	+ { 0x200f1, 0x0 },
	3060	+ { 0x200f2, 0x4444 },
	3061	+ { 0x200f3, 0x8888 },
	3062	+ { 0x200f4, 0x5665 },
	3063	+ { 0x200f5, 0x0 },
	3064	+ { 0x200f6, 0x0 },
	3065	+ { 0x200f7, 0xf000 },
	3066	+ { 0x20025, 0x0 },
	3067	+ { 0x2002d, 0x0 },
	3068	+ { 0x12002d, 0x0 },
	3069	+ { 0x22002d, 0x0 },
	3070	+ { 0x2007d, 0x212 },
	3071	+ { 0x12007d, 0x212 },
	3072	+ { 0x22007d, 0x212 },
	3073	+ { 0x2007c, 0x61 },
	3074	+ { 0x12007c, 0x61 },
	3075	+ { 0x22007c, 0x61 },
	3076	+ { 0x1004a, 0x500 },
	3077	+ { 0x1104a, 0x500 },
	3078	+ { 0x1204a, 0x500 },
	3079	+ { 0x1304a, 0x500 },
	3080	+ { 0x2002c, 0x0 },
	3081	+};
	3082	+
	3083	+/* ddr phy trained csr */
	3084	+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
	3085	+ { 0x200b2, 0x0 },
	3086	+ { 0x1200b2, 0x0 },
	3087	+ { 0x2200b2, 0x0 },
	3088	+ { 0x200cb, 0x0 },
	3089	+ { 0x10043, 0x0 },
	3090	+ { 0x110043, 0x0 },
	3091	+ { 0x210043, 0x0 },
	3092	+ { 0x10143, 0x0 },
	3093	+ { 0x110143, 0x0 },
	3094	+ { 0x210143, 0x0 },
	3095	+ { 0x11043, 0x0 },
	3096	+ { 0x111043, 0x0 },
	3097	+ { 0x211043, 0x0 },
	3098	+ { 0x11143, 0x0 },
	3099	+ { 0x111143, 0x0 },
	3100	+ { 0x211143, 0x0 },
	3101	+ { 0x12043, 0x0 },
	3102	+ { 0x112043, 0x0 },
	3103	+ { 0x212043, 0x0 },
	3104	+ { 0x12143, 0x0 },
	3105	+ { 0x112143, 0x0 },
	3106	+ { 0x212143, 0x0 },
	3107	+ { 0x13043, 0x0 },
	3108	+ { 0x113043, 0x0 },
	3109	+ { 0x213043, 0x0 },
	3110	+ { 0x13143, 0x0 },
	3111	+ { 0x113143, 0x0 },
	3112	+ { 0x213143, 0x0 },
	3113	+ { 0x80, 0x0 },
	3114	+ { 0x100080, 0x0 },
	3115	+ { 0x200080, 0x0 },
	3116	+ { 0x1080, 0x0 },
	3117	+ { 0x101080, 0x0 },
	3118	+ { 0x201080, 0x0 },
	3119	+ { 0x2080, 0x0 },
	3120	+ { 0x102080, 0x0 },
	3121	+ { 0x202080, 0x0 },
	3122	+ { 0x3080, 0x0 },
	3123	+ { 0x103080, 0x0 },
	3124	+ { 0x203080, 0x0 },
	3125	+ { 0x4080, 0x0 },
	3126	+ { 0x104080, 0x0 },
	3127	+ { 0x204080, 0x0 },
	3128	+ { 0x5080, 0x0 },
	3129	+ { 0x105080, 0x0 },
	3130	+ { 0x205080, 0x0 },
	3131	+ { 0x6080, 0x0 },
	3132	+ { 0x106080, 0x0 },
	3133	+ { 0x206080, 0x0 },
	3134	+ { 0x7080, 0x0 },
	3135	+ { 0x107080, 0x0 },
	3136	+ { 0x207080, 0x0 },
	3137	+ { 0x8080, 0x0 },
	3138	+ { 0x108080, 0x0 },
	3139	+ { 0x208080, 0x0 },
	3140	+ { 0x9080, 0x0 },
	3141	+ { 0x109080, 0x0 },
	3142	+ { 0x209080, 0x0 },
	3143	+ { 0x10080, 0x0 },
	3144	+ { 0x110080, 0x0 },
	3145	+ { 0x210080, 0x0 },
	3146	+ { 0x10180, 0x0 },
	3147	+ { 0x110180, 0x0 },
	3148	+ { 0x210180, 0x0 },
	3149	+ { 0x11080, 0x0 },
	3150	+ { 0x111080, 0x0 },
	3151	+ { 0x211080, 0x0 },
	3152	+ { 0x11180, 0x0 },
	3153	+ { 0x111180, 0x0 },
	3154	+ { 0x211180, 0x0 },
	3155	+ { 0x12080, 0x0 },
	3156	+ { 0x112080, 0x0 },
	3157	+ { 0x212080, 0x0 },
	3158	+ { 0x12180, 0x0 },
	3159	+ { 0x112180, 0x0 },
	3160	+ { 0x212180, 0x0 },
	3161	+ { 0x13080, 0x0 },
	3162	+ { 0x113080, 0x0 },
	3163	+ { 0x213080, 0x0 },
	3164	+ { 0x13180, 0x0 },
	3165	+ { 0x113180, 0x0 },
	3166	+ { 0x213180, 0x0 },
	3167	+ { 0x10081, 0x0 },
	3168	+ { 0x110081, 0x0 },
	3169	+ { 0x210081, 0x0 },
	3170	+ { 0x10181, 0x0 },
	3171	+ { 0x110181, 0x0 },
	3172	+ { 0x210181, 0x0 },
	3173	+ { 0x11081, 0x0 },
	3174	+ { 0x111081, 0x0 },
	3175	+ { 0x211081, 0x0 },
	3176	+ { 0x11181, 0x0 },
	3177	+ { 0x111181, 0x0 },
	3178	+ { 0x211181, 0x0 },
	3179	+ { 0x12081, 0x0 },
	3180	+ { 0x112081, 0x0 },
	3181	+ { 0x212081, 0x0 },
	3182	+ { 0x12181, 0x0 },
	3183	+ { 0x112181, 0x0 },
	3184	+ { 0x212181, 0x0 },
	3185	+ { 0x13081, 0x0 },
	3186	+ { 0x113081, 0x0 },
	3187	+ { 0x213081, 0x0 },
	3188	+ { 0x13181, 0x0 },
	3189	+ { 0x113181, 0x0 },
	3190	+ { 0x213181, 0x0 },
	3191	+ { 0x100d0, 0x0 },
	3192	+ { 0x1100d0, 0x0 },
	3193	+ { 0x2100d0, 0x0 },
	3194	+ { 0x101d0, 0x0 },
	3195	+ { 0x1101d0, 0x0 },
	3196	+ { 0x2101d0, 0x0 },
	3197	+ { 0x110d0, 0x0 },
	3198	+ { 0x1110d0, 0x0 },
	3199	+ { 0x2110d0, 0x0 },
	3200	+ { 0x111d0, 0x0 },
	3201	+ { 0x1111d0, 0x0 },
	3202	+ { 0x2111d0, 0x0 },
	3203	+ { 0x120d0, 0x0 },
	3204	+ { 0x1120d0, 0x0 },
	3205	+ { 0x2120d0, 0x0 },
	3206	+ { 0x121d0, 0x0 },
	3207	+ { 0x1121d0, 0x0 },
	3208	+ { 0x2121d0, 0x0 },
	3209	+ { 0x130d0, 0x0 },
	3210	+ { 0x1130d0, 0x0 },
	3211	+ { 0x2130d0, 0x0 },
	3212	+ { 0x131d0, 0x0 },
	3213	+ { 0x1131d0, 0x0 },
	3214	+ { 0x2131d0, 0x0 },
	3215	+ { 0x100d1, 0x0 },
	3216	+ { 0x1100d1, 0x0 },
	3217	+ { 0x2100d1, 0x0 },
	3218	+ { 0x101d1, 0x0 },
	3219	+ { 0x1101d1, 0x0 },
	3220	+ { 0x2101d1, 0x0 },
	3221	+ { 0x110d1, 0x0 },
	3222	+ { 0x1110d1, 0x0 },
	3223	+ { 0x2110d1, 0x0 },
	3224	+ { 0x111d1, 0x0 },
	3225	+ { 0x1111d1, 0x0 },
	3226	+ { 0x2111d1, 0x0 },
	3227	+ { 0x120d1, 0x0 },
	3228	+ { 0x1120d1, 0x0 },
	3229	+ { 0x2120d1, 0x0 },
	3230	+ { 0x121d1, 0x0 },
	3231	+ { 0x1121d1, 0x0 },
	3232	+ { 0x2121d1, 0x0 },
	3233	+ { 0x130d1, 0x0 },
	3234	+ { 0x1130d1, 0x0 },
	3235	+ { 0x2130d1, 0x0 },
	3236	+ { 0x131d1, 0x0 },
	3237	+ { 0x1131d1, 0x0 },
	3238	+ { 0x2131d1, 0x0 },
	3239	+ { 0x10068, 0x0 },
	3240	+ { 0x10168, 0x0 },
	3241	+ { 0x10268, 0x0 },
	3242	+ { 0x10368, 0x0 },
	3243	+ { 0x10468, 0x0 },
	3244	+ { 0x10568, 0x0 },
	3245	+ { 0x10668, 0x0 },
	3246	+ { 0x10768, 0x0 },
	3247	+ { 0x10868, 0x0 },
	3248	+ { 0x11068, 0x0 },
	3249	+ { 0x11168, 0x0 },
	3250	+ { 0x11268, 0x0 },
	3251	+ { 0x11368, 0x0 },
	3252	+ { 0x11468, 0x0 },
	3253	+ { 0x11568, 0x0 },
	3254	+ { 0x11668, 0x0 },
	3255	+ { 0x11768, 0x0 },
	3256	+ { 0x11868, 0x0 },
	3257	+ { 0x12068, 0x0 },
	3258	+ { 0x12168, 0x0 },
	3259	+ { 0x12268, 0x0 },
	3260	+ { 0x12368, 0x0 },
	3261	+ { 0x12468, 0x0 },
	3262	+ { 0x12568, 0x0 },
	3263	+ { 0x12668, 0x0 },
	3264	+ { 0x12768, 0x0 },
	3265	+ { 0x12868, 0x0 },
	3266	+ { 0x13068, 0x0 },
	3267	+ { 0x13168, 0x0 },
	3268	+ { 0x13268, 0x0 },
	3269	+ { 0x13368, 0x0 },
	3270	+ { 0x13468, 0x0 },
	3271	+ { 0x13568, 0x0 },
	3272	+ { 0x13668, 0x0 },
	3273	+ { 0x13768, 0x0 },
	3274	+ { 0x13868, 0x0 },
	3275	+ { 0x10069, 0x0 },
	3276	+ { 0x10169, 0x0 },
	3277	+ { 0x10269, 0x0 },
	3278	+ { 0x10369, 0x0 },
	3279	+ { 0x10469, 0x0 },
	3280	+ { 0x10569, 0x0 },
	3281	+ { 0x10669, 0x0 },
	3282	+ { 0x10769, 0x0 },
	3283	+ { 0x10869, 0x0 },
	3284	+ { 0x11069, 0x0 },
	3285	+ { 0x11169, 0x0 },
	3286	+ { 0x11269, 0x0 },
	3287	+ { 0x11369, 0x0 },
	3288	+ { 0x11469, 0x0 },
	3289	+ { 0x11569, 0x0 },
	3290	+ { 0x11669, 0x0 },
	3291	+ { 0x11769, 0x0 },
	3292	+ { 0x11869, 0x0 },
	3293	+ { 0x12069, 0x0 },
	3294	+ { 0x12169, 0x0 },
	3295	+ { 0x12269, 0x0 },
	3296	+ { 0x12369, 0x0 },
	3297	+ { 0x12469, 0x0 },
	3298	+ { 0x12569, 0x0 },
	3299	+ { 0x12669, 0x0 },
	3300	+ { 0x12769, 0x0 },
	3301	+ { 0x12869, 0x0 },
	3302	+ { 0x13069, 0x0 },
	3303	+ { 0x13169, 0x0 },
	3304	+ { 0x13269, 0x0 },
	3305	+ { 0x13369, 0x0 },
	3306	+ { 0x13469, 0x0 },
	3307	+ { 0x13569, 0x0 },
	3308	+ { 0x13669, 0x0 },
	3309	+ { 0x13769, 0x0 },
	3310	+ { 0x13869, 0x0 },
	3311	+ { 0x1008c, 0x0 },
	3312	+ { 0x11008c, 0x0 },
	3313	+ { 0x21008c, 0x0 },
	3314	+ { 0x1018c, 0x0 },
	3315	+ { 0x11018c, 0x0 },
	3316	+ { 0x21018c, 0x0 },
	3317	+ { 0x1108c, 0x0 },
	3318	+ { 0x11108c, 0x0 },
	3319	+ { 0x21108c, 0x0 },
	3320	+ { 0x1118c, 0x0 },
	3321	+ { 0x11118c, 0x0 },
	3322	+ { 0x21118c, 0x0 },
	3323	+ { 0x1208c, 0x0 },
	3324	+ { 0x11208c, 0x0 },
	3325	+ { 0x21208c, 0x0 },
	3326	+ { 0x1218c, 0x0 },
	3327	+ { 0x11218c, 0x0 },
	3328	+ { 0x21218c, 0x0 },
	3329	+ { 0x1308c, 0x0 },
	3330	+ { 0x11308c, 0x0 },
	3331	+ { 0x21308c, 0x0 },
	3332	+ { 0x1318c, 0x0 },
	3333	+ { 0x11318c, 0x0 },
	3334	+ { 0x21318c, 0x0 },
	3335	+ { 0x1008d, 0x0 },
	3336	+ { 0x11008d, 0x0 },
	3337	+ { 0x21008d, 0x0 },
	3338	+ { 0x1018d, 0x0 },
	3339	+ { 0x11018d, 0x0 },
	3340	+ { 0x21018d, 0x0 },
	3341	+ { 0x1108d, 0x0 },
	3342	+ { 0x11108d, 0x0 },
	3343	+ { 0x21108d, 0x0 },
	3344	+ { 0x1118d, 0x0 },
	3345	+ { 0x11118d, 0x0 },
	3346	+ { 0x21118d, 0x0 },
	3347	+ { 0x1208d, 0x0 },
	3348	+ { 0x11208d, 0x0 },
	3349	+ { 0x21208d, 0x0 },
	3350	+ { 0x1218d, 0x0 },
	3351	+ { 0x11218d, 0x0 },
	3352	+ { 0x21218d, 0x0 },
	3353	+ { 0x1308d, 0x0 },
	3354	+ { 0x11308d, 0x0 },
	3355	+ { 0x21308d, 0x0 },
	3356	+ { 0x1318d, 0x0 },
	3357	+ { 0x11318d, 0x0 },
	3358	+ { 0x21318d, 0x0 },
	3359	+ { 0x100c0, 0x0 },
	3360	+ { 0x1100c0, 0x0 },
	3361	+ { 0x2100c0, 0x0 },
	3362	+ { 0x101c0, 0x0 },
	3363	+ { 0x1101c0, 0x0 },
	3364	+ { 0x2101c0, 0x0 },
	3365	+ { 0x102c0, 0x0 },
	3366	+ { 0x1102c0, 0x0 },
	3367	+ { 0x2102c0, 0x0 },
	3368	+ { 0x103c0, 0x0 },
	3369	+ { 0x1103c0, 0x0 },
	3370	+ { 0x2103c0, 0x0 },
	3371	+ { 0x104c0, 0x0 },
	3372	+ { 0x1104c0, 0x0 },
	3373	+ { 0x2104c0, 0x0 },
	3374	+ { 0x105c0, 0x0 },
	3375	+ { 0x1105c0, 0x0 },
	3376	+ { 0x2105c0, 0x0 },
	3377	+ { 0x106c0, 0x0 },
	3378	+ { 0x1106c0, 0x0 },
	3379	+ { 0x2106c0, 0x0 },
	3380	+ { 0x107c0, 0x0 },
	3381	+ { 0x1107c0, 0x0 },
	3382	+ { 0x2107c0, 0x0 },
	3383	+ { 0x108c0, 0x0 },
	3384	+ { 0x1108c0, 0x0 },
	3385	+ { 0x2108c0, 0x0 },
	3386	+ { 0x110c0, 0x0 },
	3387	+ { 0x1110c0, 0x0 },
	3388	+ { 0x2110c0, 0x0 },
	3389	+ { 0x111c0, 0x0 },
	3390	+ { 0x1111c0, 0x0 },
	3391	+ { 0x2111c0, 0x0 },
	3392	+ { 0x112c0, 0x0 },
	3393	+ { 0x1112c0, 0x0 },
	3394	+ { 0x2112c0, 0x0 },
	3395	+ { 0x113c0, 0x0 },
	3396	+ { 0x1113c0, 0x0 },
	3397	+ { 0x2113c0, 0x0 },
	3398	+ { 0x114c0, 0x0 },
	3399	+ { 0x1114c0, 0x0 },
	3400	+ { 0x2114c0, 0x0 },
	3401	+ { 0x115c0, 0x0 },
	3402	+ { 0x1115c0, 0x0 },
	3403	+ { 0x2115c0, 0x0 },
	3404	+ { 0x116c0, 0x0 },
	3405	+ { 0x1116c0, 0x0 },
	3406	+ { 0x2116c0, 0x0 },
	3407	+ { 0x117c0, 0x0 },
	3408	+ { 0x1117c0, 0x0 },
	3409	+ { 0x2117c0, 0x0 },
	3410	+ { 0x118c0, 0x0 },
	3411	+ { 0x1118c0, 0x0 },
	3412	+ { 0x2118c0, 0x0 },
	3413	+ { 0x120c0, 0x0 },
	3414	+ { 0x1120c0, 0x0 },
	3415	+ { 0x2120c0, 0x0 },
	3416	+ { 0x121c0, 0x0 },
	3417	+ { 0x1121c0, 0x0 },
	3418	+ { 0x2121c0, 0x0 },
	3419	+ { 0x122c0, 0x0 },
	3420	+ { 0x1122c0, 0x0 },
	3421	+ { 0x2122c0, 0x0 },
	3422	+ { 0x123c0, 0x0 },
	3423	+ { 0x1123c0, 0x0 },
	3424	+ { 0x2123c0, 0x0 },
	3425	+ { 0x124c0, 0x0 },
	3426	+ { 0x1124c0, 0x0 },
	3427	+ { 0x2124c0, 0x0 },
	3428	+ { 0x125c0, 0x0 },
	3429	+ { 0x1125c0, 0x0 },
	3430	+ { 0x2125c0, 0x0 },
	3431	+ { 0x126c0, 0x0 },
	3432	+ { 0x1126c0, 0x0 },
	3433	+ { 0x2126c0, 0x0 },
	3434	+ { 0x127c0, 0x0 },
	3435	+ { 0x1127c0, 0x0 },
	3436	+ { 0x2127c0, 0x0 },
	3437	+ { 0x128c0, 0x0 },
	3438	+ { 0x1128c0, 0x0 },
	3439	+ { 0x2128c0, 0x0 },
	3440	+ { 0x130c0, 0x0 },
	3441	+ { 0x1130c0, 0x0 },
	3442	+ { 0x2130c0, 0x0 },
	3443	+ { 0x131c0, 0x0 },
	3444	+ { 0x1131c0, 0x0 },
	3445	+ { 0x2131c0, 0x0 },
	3446	+ { 0x132c0, 0x0 },
	3447	+ { 0x1132c0, 0x0 },
	3448	+ { 0x2132c0, 0x0 },
	3449	+ { 0x133c0, 0x0 },
	3450	+ { 0x1133c0, 0x0 },
	3451	+ { 0x2133c0, 0x0 },
	3452	+ { 0x134c0, 0x0 },
	3453	+ { 0x1134c0, 0x0 },
	3454	+ { 0x2134c0, 0x0 },
	3455	+ { 0x135c0, 0x0 },
	3456	+ { 0x1135c0, 0x0 },
	3457	+ { 0x2135c0, 0x0 },
	3458	+ { 0x136c0, 0x0 },
	3459	+ { 0x1136c0, 0x0 },
	3460	+ { 0x2136c0, 0x0 },
	3461	+ { 0x137c0, 0x0 },
	3462	+ { 0x1137c0, 0x0 },
	3463	+ { 0x2137c0, 0x0 },
	3464	+ { 0x138c0, 0x0 },
	3465	+ { 0x1138c0, 0x0 },
	3466	+ { 0x2138c0, 0x0 },
	3467	+ { 0x100c1, 0x0 },
	3468	+ { 0x1100c1, 0x0 },
	3469	+ { 0x2100c1, 0x0 },
	3470	+ { 0x101c1, 0x0 },
	3471	+ { 0x1101c1, 0x0 },
	3472	+ { 0x2101c1, 0x0 },
	3473	+ { 0x102c1, 0x0 },
	3474	+ { 0x1102c1, 0x0 },
	3475	+ { 0x2102c1, 0x0 },
	3476	+ { 0x103c1, 0x0 },
	3477	+ { 0x1103c1, 0x0 },
	3478	+ { 0x2103c1, 0x0 },
	3479	+ { 0x104c1, 0x0 },
	3480	+ { 0x1104c1, 0x0 },
	3481	+ { 0x2104c1, 0x0 },
	3482	+ { 0x105c1, 0x0 },
	3483	+ { 0x1105c1, 0x0 },
	3484	+ { 0x2105c1, 0x0 },
	3485	+ { 0x106c1, 0x0 },
	3486	+ { 0x1106c1, 0x0 },
	3487	+ { 0x2106c1, 0x0 },
	3488	+ { 0x107c1, 0x0 },
	3489	+ { 0x1107c1, 0x0 },
	3490	+ { 0x2107c1, 0x0 },
	3491	+ { 0x108c1, 0x0 },
	3492	+ { 0x1108c1, 0x0 },
	3493	+ { 0x2108c1, 0x0 },
	3494	+ { 0x110c1, 0x0 },
	3495	+ { 0x1110c1, 0x0 },
	3496	+ { 0x2110c1, 0x0 },
	3497	+ { 0x111c1, 0x0 },
	3498	+ { 0x1111c1, 0x0 },
	3499	+ { 0x2111c1, 0x0 },
	3500	+ { 0x112c1, 0x0 },
	3501	+ { 0x1112c1, 0x0 },
	3502	+ { 0x2112c1, 0x0 },
	3503	+ { 0x113c1, 0x0 },
	3504	+ { 0x1113c1, 0x0 },
	3505	+ { 0x2113c1, 0x0 },
	3506	+ { 0x114c1, 0x0 },
	3507	+ { 0x1114c1, 0x0 },
	3508	+ { 0x2114c1, 0x0 },
	3509	+ { 0x115c1, 0x0 },
	3510	+ { 0x1115c1, 0x0 },
	3511	+ { 0x2115c1, 0x0 },
	3512	+ { 0x116c1, 0x0 },
	3513	+ { 0x1116c1, 0x0 },
	3514	+ { 0x2116c1, 0x0 },
	3515	+ { 0x117c1, 0x0 },
	3516	+ { 0x1117c1, 0x0 },
	3517	+ { 0x2117c1, 0x0 },
	3518	+ { 0x118c1, 0x0 },
	3519	+ { 0x1118c1, 0x0 },
	3520	+ { 0x2118c1, 0x0 },
	3521	+ { 0x120c1, 0x0 },
	3522	+ { 0x1120c1, 0x0 },
	3523	+ { 0x2120c1, 0x0 },
	3524	+ { 0x121c1, 0x0 },
	3525	+ { 0x1121c1, 0x0 },
	3526	+ { 0x2121c1, 0x0 },
	3527	+ { 0x122c1, 0x0 },
	3528	+ { 0x1122c1, 0x0 },
	3529	+ { 0x2122c1, 0x0 },
	3530	+ { 0x123c1, 0x0 },
	3531	+ { 0x1123c1, 0x0 },
	3532	+ { 0x2123c1, 0x0 },
	3533	+ { 0x124c1, 0x0 },
	3534	+ { 0x1124c1, 0x0 },
	3535	+ { 0x2124c1, 0x0 },
	3536	+ { 0x125c1, 0x0 },
	3537	+ { 0x1125c1, 0x0 },
	3538	+ { 0x2125c1, 0x0 },
	3539	+ { 0x126c1, 0x0 },
	3540	+ { 0x1126c1, 0x0 },
	3541	+ { 0x2126c1, 0x0 },
	3542	+ { 0x127c1, 0x0 },
	3543	+ { 0x1127c1, 0x0 },
	3544	+ { 0x2127c1, 0x0 },
	3545	+ { 0x128c1, 0x0 },
	3546	+ { 0x1128c1, 0x0 },
	3547	+ { 0x2128c1, 0x0 },
	3548	+ { 0x130c1, 0x0 },
	3549	+ { 0x1130c1, 0x0 },
	3550	+ { 0x2130c1, 0x0 },
	3551	+ { 0x131c1, 0x0 },
	3552	+ { 0x1131c1, 0x0 },
	3553	+ { 0x2131c1, 0x0 },
	3554	+ { 0x132c1, 0x0 },
	3555	+ { 0x1132c1, 0x0 },
	3556	+ { 0x2132c1, 0x0 },
	3557	+ { 0x133c1, 0x0 },
	3558	+ { 0x1133c1, 0x0 },
	3559	+ { 0x2133c1, 0x0 },
	3560	+ { 0x134c1, 0x0 },
	3561	+ { 0x1134c1, 0x0 },
	3562	+ { 0x2134c1, 0x0 },
	3563	+ { 0x135c1, 0x0 },
	3564	+ { 0x1135c1, 0x0 },
	3565	+ { 0x2135c1, 0x0 },
	3566	+ { 0x136c1, 0x0 },
	3567	+ { 0x1136c1, 0x0 },
	3568	+ { 0x2136c1, 0x0 },
	3569	+ { 0x137c1, 0x0 },
	3570	+ { 0x1137c1, 0x0 },
	3571	+ { 0x2137c1, 0x0 },
	3572	+ { 0x138c1, 0x0 },
	3573	+ { 0x1138c1, 0x0 },
	3574	+ { 0x2138c1, 0x0 },
	3575	+ { 0x10020, 0x0 },
	3576	+ { 0x110020, 0x0 },
	3577	+ { 0x210020, 0x0 },
	3578	+ { 0x11020, 0x0 },
	3579	+ { 0x111020, 0x0 },
	3580	+ { 0x211020, 0x0 },
	3581	+ { 0x12020, 0x0 },
	3582	+ { 0x112020, 0x0 },
	3583	+ { 0x212020, 0x0 },
	3584	+ { 0x13020, 0x0 },
	3585	+ { 0x113020, 0x0 },
	3586	+ { 0x213020, 0x0 },
	3587	+ { 0x20072, 0x0 },
	3588	+ { 0x20073, 0x0 },
	3589	+ { 0x20074, 0x0 },
	3590	+ { 0x100aa, 0x0 },
	3591	+ { 0x110aa, 0x0 },
	3592	+ { 0x120aa, 0x0 },
	3593	+ { 0x130aa, 0x0 },
	3594	+ { 0x20010, 0x0 },
	3595	+ { 0x120010, 0x0 },
	3596	+ { 0x220010, 0x0 },
	3597	+ { 0x20011, 0x0 },
	3598	+ { 0x120011, 0x0 },
	3599	+ { 0x220011, 0x0 },
	3600	+ { 0x100ae, 0x0 },
	3601	+ { 0x1100ae, 0x0 },
	3602	+ { 0x2100ae, 0x0 },
	3603	+ { 0x100af, 0x0 },
	3604	+ { 0x1100af, 0x0 },
	3605	+ { 0x2100af, 0x0 },
	3606	+ { 0x110ae, 0x0 },
	3607	+ { 0x1110ae, 0x0 },
	3608	+ { 0x2110ae, 0x0 },
	3609	+ { 0x110af, 0x0 },
	3610	+ { 0x1110af, 0x0 },
	3611	+ { 0x2110af, 0x0 },
	3612	+ { 0x120ae, 0x0 },
	3613	+ { 0x1120ae, 0x0 },
	3614	+ { 0x2120ae, 0x0 },
	3615	+ { 0x120af, 0x0 },
	3616	+ { 0x1120af, 0x0 },
	3617	+ { 0x2120af, 0x0 },
	3618	+ { 0x130ae, 0x0 },
	3619	+ { 0x1130ae, 0x0 },
	3620	+ { 0x2130ae, 0x0 },
	3621	+ { 0x130af, 0x0 },
	3622	+ { 0x1130af, 0x0 },
	3623	+ { 0x2130af, 0x0 },
	3624	+ { 0x20020, 0x0 },
	3625	+ { 0x120020, 0x0 },
	3626	+ { 0x220020, 0x0 },
	3627	+ { 0x100a0, 0x0 },
	3628	+ { 0x100a1, 0x0 },
	3629	+ { 0x100a2, 0x0 },
	3630	+ { 0x100a3, 0x0 },
	3631	+ { 0x100a4, 0x0 },
	3632	+ { 0x100a5, 0x0 },
	3633	+ { 0x100a6, 0x0 },
	3634	+ { 0x100a7, 0x0 },
	3635	+ { 0x110a0, 0x0 },
	3636	+ { 0x110a1, 0x0 },
	3637	+ { 0x110a2, 0x0 },
	3638	+ { 0x110a3, 0x0 },
	3639	+ { 0x110a4, 0x0 },
	3640	+ { 0x110a5, 0x0 },
	3641	+ { 0x110a6, 0x0 },
	3642	+ { 0x110a7, 0x0 },
	3643	+ { 0x120a0, 0x0 },
	3644	+ { 0x120a1, 0x0 },
	3645	+ { 0x120a2, 0x0 },
	3646	+ { 0x120a3, 0x0 },
	3647	+ { 0x120a4, 0x0 },
	3648	+ { 0x120a5, 0x0 },
	3649	+ { 0x120a6, 0x0 },
	3650	+ { 0x120a7, 0x0 },
	3651	+ { 0x130a0, 0x0 },
	3652	+ { 0x130a1, 0x0 },
	3653	+ { 0x130a2, 0x0 },
	3654	+ { 0x130a3, 0x0 },
	3655	+ { 0x130a4, 0x0 },
	3656	+ { 0x130a5, 0x0 },
	3657	+ { 0x130a6, 0x0 },
	3658	+ { 0x130a7, 0x0 },
	3659	+ { 0x2007c, 0x0 },
	3660	+ { 0x12007c, 0x0 },
	3661	+ { 0x22007c, 0x0 },
	3662	+ { 0x2007d, 0x0 },
	3663	+ { 0x12007d, 0x0 },
	3664	+ { 0x22007d, 0x0 },
	3665	+ { 0x400fd, 0x0 },
	3666	+ { 0x400c0, 0x0 },
	3667	+ { 0x90201, 0x0 },
	3668	+ { 0x190201, 0x0 },
	3669	+ { 0x290201, 0x0 },
	3670	+ { 0x90202, 0x0 },
	3671	+ { 0x190202, 0x0 },
	3672	+ { 0x290202, 0x0 },
	3673	+ { 0x90203, 0x0 },
	3674	+ { 0x190203, 0x0 },
	3675	+ { 0x290203, 0x0 },
	3676	+ { 0x90204, 0x0 },
	3677	+ { 0x190204, 0x0 },
	3678	+ { 0x290204, 0x0 },
	3679	+ { 0x90205, 0x0 },
	3680	+ { 0x190205, 0x0 },
	3681	+ { 0x290205, 0x0 },
	3682	+ { 0x90206, 0x0 },
	3683	+ { 0x190206, 0x0 },
	3684	+ { 0x290206, 0x0 },
	3685	+ { 0x90207, 0x0 },
	3686	+ { 0x190207, 0x0 },
	3687	+ { 0x290207, 0x0 },
	3688	+ { 0x90208, 0x0 },
	3689	+ { 0x190208, 0x0 },
	3690	+ { 0x290208, 0x0 },
	3691	+ { 0x10062, 0x0 },
	3692	+ { 0x10162, 0x0 },
	3693	+ { 0x10262, 0x0 },
	3694	+ { 0x10362, 0x0 },
	3695	+ { 0x10462, 0x0 },
	3696	+ { 0x10562, 0x0 },
	3697	+ { 0x10662, 0x0 },
	3698	+ { 0x10762, 0x0 },
	3699	+ { 0x10862, 0x0 },
	3700	+ { 0x11062, 0x0 },
	3701	+ { 0x11162, 0x0 },
	3702	+ { 0x11262, 0x0 },
	3703	+ { 0x11362, 0x0 },
	3704	+ { 0x11462, 0x0 },
	3705	+ { 0x11562, 0x0 },
	3706	+ { 0x11662, 0x0 },
	3707	+ { 0x11762, 0x0 },
	3708	+ { 0x11862, 0x0 },
	3709	+ { 0x12062, 0x0 },
	3710	+ { 0x12162, 0x0 },
	3711	+ { 0x12262, 0x0 },
	3712	+ { 0x12362, 0x0 },
	3713	+ { 0x12462, 0x0 },
	3714	+ { 0x12562, 0x0 },
	3715	+ { 0x12662, 0x0 },
	3716	+ { 0x12762, 0x0 },
	3717	+ { 0x12862, 0x0 },
	3718	+ { 0x13062, 0x0 },
	3719	+ { 0x13162, 0x0 },
	3720	+ { 0x13262, 0x0 },
	3721	+ { 0x13362, 0x0 },
	3722	+ { 0x13462, 0x0 },
	3723	+ { 0x13562, 0x0 },
	3724	+ { 0x13662, 0x0 },
	3725	+ { 0x13762, 0x0 },
	3726	+ { 0x13862, 0x0 },
	3727	+ { 0x20077, 0x0 },
	3728	+ { 0x10001, 0x0 },
	3729	+ { 0x11001, 0x0 },
	3730	+ { 0x12001, 0x0 },
	3731	+ { 0x13001, 0x0 },
	3732	+ { 0x10040, 0x0 },
	3733	+ { 0x10140, 0x0 },
	3734	+ { 0x10240, 0x0 },
	3735	+ { 0x10340, 0x0 },
	3736	+ { 0x10440, 0x0 },
	3737	+ { 0x10540, 0x0 },
	3738	+ { 0x10640, 0x0 },
	3739	+ { 0x10740, 0x0 },
	3740	+ { 0x10840, 0x0 },
	3741	+ { 0x10030, 0x0 },
	3742	+ { 0x10130, 0x0 },
	3743	+ { 0x10230, 0x0 },
	3744	+ { 0x10330, 0x0 },
	3745	+ { 0x10430, 0x0 },
	3746	+ { 0x10530, 0x0 },
	3747	+ { 0x10630, 0x0 },
	3748	+ { 0x10730, 0x0 },
	3749	+ { 0x10830, 0x0 },
	3750	+ { 0x11040, 0x0 },
	3751	+ { 0x11140, 0x0 },
	3752	+ { 0x11240, 0x0 },
	3753	+ { 0x11340, 0x0 },
	3754	+ { 0x11440, 0x0 },
	3755	+ { 0x11540, 0x0 },
	3756	+ { 0x11640, 0x0 },
	3757	+ { 0x11740, 0x0 },
	3758	+ { 0x11840, 0x0 },
	3759	+ { 0x11030, 0x0 },
	3760	+ { 0x11130, 0x0 },
	3761	+ { 0x11230, 0x0 },
	3762	+ { 0x11330, 0x0 },
	3763	+ { 0x11430, 0x0 },
	3764	+ { 0x11530, 0x0 },
	3765	+ { 0x11630, 0x0 },
	3766	+ { 0x11730, 0x0 },
	3767	+ { 0x11830, 0x0 },
	3768	+ { 0x12040, 0x0 },
	3769	+ { 0x12140, 0x0 },
	3770	+ { 0x12240, 0x0 },
	3771	+ { 0x12340, 0x0 },
	3772	+ { 0x12440, 0x0 },
	3773	+ { 0x12540, 0x0 },
	3774	+ { 0x12640, 0x0 },
	3775	+ { 0x12740, 0x0 },
	3776	+ { 0x12840, 0x0 },
	3777	+ { 0x12030, 0x0 },
	3778	+ { 0x12130, 0x0 },
	3779	+ { 0x12230, 0x0 },
	3780	+ { 0x12330, 0x0 },
	3781	+ { 0x12430, 0x0 },
	3782	+ { 0x12530, 0x0 },
	3783	+ { 0x12630, 0x0 },
	3784	+ { 0x12730, 0x0 },
	3785	+ { 0x12830, 0x0 },
	3786	+ { 0x13040, 0x0 },
	3787	+ { 0x13140, 0x0 },
	3788	+ { 0x13240, 0x0 },
	3789	+ { 0x13340, 0x0 },
	3790	+ { 0x13440, 0x0 },
	3791	+ { 0x13540, 0x0 },
	3792	+ { 0x13640, 0x0 },
	3793	+ { 0x13740, 0x0 },
	3794	+ { 0x13840, 0x0 },
	3795	+ { 0x13030, 0x0 },
	3796	+ { 0x13130, 0x0 },
	3797	+ { 0x13230, 0x0 },
	3798	+ { 0x13330, 0x0 },
	3799	+ { 0x13430, 0x0 },
	3800	+ { 0x13530, 0x0 },
	3801	+ { 0x13630, 0x0 },
	3802	+ { 0x13730, 0x0 },
	3803	+ { 0x13830, 0x0 },
	3804	+};
	3805	+
	3806	+/* P0 message block paremeter for training firmware */
	3807	+struct dram_cfg_param ddr_fsp0_cfg[] = {
	3808	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	3809	+ { 0xd0000, 0x0 },
	3810	+ { 0x54003, 0x960 },
	3811	+ { 0x54004, 0x2 },
	3812	+ { 0x54005, 0x2228 },
	3813	+ { 0x54006, 0x14 },
	3814	+ { 0x54008, 0x131f },
	3815	+ { 0x54009, 0xc8 },
	3816	+ { 0x5400b, 0x2 },
	3817	+ { 0x5400f, 0x100 },
	3818	+ { 0x54012, 0x310 },
	3819	+ { 0x54019, 0x24c4 },
	3820	+ { 0x5401a, 0x33 },
	3821	+ { 0x5401b, 0x4866 },
	3822	+ { 0x5401c, 0x4800 },
	3823	+ { 0x5401e, 0x16 },
	3824	+ { 0x5401f, 0x24c4 },
	3825	+ { 0x54020, 0x33 },
	3826	+ { 0x54021, 0x4866 },
	3827	+ { 0x54022, 0x4800 },
	3828	+ { 0x54024, 0x16 },
	3829	+ { 0x5402b, 0x1000 },
	3830	+ { 0x5402c, 0x3 },
	3831	+ { 0x54032, 0xc400 },
	3832	+ { 0x54033, 0x3324 },
	3833	+ { 0x54034, 0x6600 },
	3834	+ { 0x54035, 0x48 },
	3835	+ { 0x54036, 0x48 },
	3836	+ { 0x54037, 0x1600 },
	3837	+ { 0x54038, 0xc400 },
	3838	+ { 0x54039, 0x3324 },
	3839	+#else
	3840	+ { 0xd0000, 0x0 },
	3841	+ { 0x54003, 0xfa0 },
	3842	+ { 0x54004, 0x2 },
	3843	+ { 0x54005, 0x2228 },
	3844	+ { 0x54006, 0x14 },
	3845	+ { 0x54008, 0x131f },
	3846	+ { 0x54009, 0xc8 },
	3847	+ { 0x5400b, 0x2 },
	3848	+ { 0x5400f, 0x100 },
	3849	+ { 0x54012, 0x310 },
	3850	+ { 0x54019, 0x3ff4 },
	3851	+ { 0x5401a, 0x33 },
	3852	+ { 0x5401b, 0x4866 },
	3853	+ { 0x5401c, 0x4800 },
	3854	+ { 0x5401e, 0x16 },
	3855	+ { 0x5401f, 0x3ff4 },
	3856	+ { 0x54020, 0x33 },
	3857	+ { 0x54021, 0x4866 },
	3858	+ { 0x54022, 0x4800 },
	3859	+ { 0x54024, 0x16 },
	3860	+ { 0x5402b, 0x1000 },
	3861	+ { 0x5402c, 0x3 },
	3862	+ { 0x54032, 0xf400 },
	3863	+ { 0x54033, 0x333f },
	3864	+ { 0x54034, 0x6600 },
	3865	+ { 0x54035, 0x48 },
	3866	+ { 0x54036, 0x48 },
	3867	+ { 0x54037, 0x1600 },
	3868	+ { 0x54038, 0xf400 },
	3869	+ { 0x54039, 0x333f },
	3870	+#endif
	3871	+ { 0x5403a, 0x6600 },
	3872	+ { 0x5403b, 0x48 },
	3873	+ { 0x5403c, 0x48 },
	3874	+ { 0x5403d, 0x1600 },
	3875	+ { 0xd0000, 0x1 },
	3876	+};
	3877	+
	3878	+/* P1 message block paremeter for training firmware */
	3879	+struct dram_cfg_param ddr_fsp1_cfg[] = {
	3880	+ { 0xd0000, 0x0 },
	3881	+ { 0x54002, 0x101 },
	3882	+ { 0x54003, 0x190 },
	3883	+ { 0x54004, 0x2 },
	3884	+ { 0x54005, 0x2228 },
	3885	+ { 0x54006, 0x14 },
	3886	+ { 0x54008, 0x121f },
	3887	+ { 0x54009, 0xc8 },
	3888	+ { 0x5400b, 0x2 },
	3889	+ { 0x5400f, 0x100 },
	3890	+ { 0x54012, 0x310 },
	3891	+ { 0x54019, 0x84 },
	3892	+ { 0x5401a, 0x33 },
	3893	+ { 0x5401b, 0x4866 },
	3894	+ { 0x5401c, 0x4800 },
	3895	+ { 0x5401e, 0x16 },
	3896	+ { 0x5401f, 0x84 },
	3897	+ { 0x54020, 0x33 },
	3898	+ { 0x54021, 0x4866 },
	3899	+ { 0x54022, 0x4800 },
	3900	+ { 0x54024, 0x16 },
	3901	+ { 0x5402b, 0x1000 },
	3902	+ { 0x5402c, 0x3 },
	3903	+ { 0x54032, 0x8400 },
	3904	+ { 0x54033, 0x3300 },
	3905	+ { 0x54034, 0x6600 },
	3906	+ { 0x54035, 0x48 },
	3907	+ { 0x54036, 0x48 },
	3908	+ { 0x54037, 0x1600 },
	3909	+ { 0x54038, 0x8400 },
	3910	+ { 0x54039, 0x3300 },
	3911	+ { 0x5403a, 0x6600 },
	3912	+ { 0x5403b, 0x48 },
	3913	+ { 0x5403c, 0x48 },
	3914	+ { 0x5403d, 0x1600 },
	3915	+ { 0xd0000, 0x1 },
	3916	+};
	3917	+
	3918	+/* P2 message block paremeter for training firmware */
	3919	+struct dram_cfg_param ddr_fsp2_cfg[] = {
	3920	+ { 0xd0000, 0x0 },
	3921	+ { 0x54002, 0x102 },
	3922	+ { 0x54003, 0x64 },
	3923	+ { 0x54004, 0x2 },
	3924	+ { 0x54005, 0x2228 },
	3925	+ { 0x54006, 0x14 },
	3926	+ { 0x54008, 0x121f },
	3927	+ { 0x54009, 0xc8 },
	3928	+ { 0x5400b, 0x2 },
	3929	+ { 0x5400f, 0x100 },
	3930	+ { 0x54012, 0x310 },
	3931	+ { 0x54019, 0x84 },
	3932	+ { 0x5401a, 0x33 },
	3933	+ { 0x5401b, 0x4866 },
	3934	+ { 0x5401c, 0x4800 },
	3935	+ { 0x5401e, 0x16 },
	3936	+ { 0x5401f, 0x84 },
	3937	+ { 0x54020, 0x33 },
	3938	+ { 0x54021, 0x4866 },
	3939	+ { 0x54022, 0x4800 },
	3940	+ { 0x54024, 0x16 },
	3941	+ { 0x5402b, 0x1000 },
	3942	+ { 0x5402c, 0x3 },
	3943	+ { 0x54032, 0x8400 },
	3944	+ { 0x54033, 0x3300 },
	3945	+ { 0x54034, 0x6600 },
	3946	+ { 0x54035, 0x48 },
	3947	+ { 0x54036, 0x48 },
	3948	+ { 0x54037, 0x1600 },
	3949	+ { 0x54038, 0x8400 },
	3950	+ { 0x54039, 0x3300 },
	3951	+ { 0x5403a, 0x6600 },
	3952	+ { 0x5403b, 0x48 },
	3953	+ { 0x5403c, 0x48 },
	3954	+ { 0x5403d, 0x1600 },
	3955	+ { 0xd0000, 0x1 },
	3956	+};
	3957	+
	3958	+/* P0 2D message block paremeter for training firmware */
	3959	+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
	3960	+ { 0xd0000, 0x0 },
	3961	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	3962	+ { 0x54003, 0x960 },
	3963	+ { 0x54004, 0x2 },
	3964	+ { 0x54005, 0x2228 },
	3965	+ { 0x54006, 0x14 },
	3966	+ { 0x54008, 0x61 },
	3967	+ { 0x54009, 0xc8 },
	3968	+ { 0x5400b, 0x2 },
	3969	+ { 0x5400f, 0x100 },
	3970	+ { 0x54010, 0x1f7f },
	3971	+ { 0x54012, 0x310 },
	3972	+ { 0x54019, 0x24c4 },
	3973	+ { 0x5401a, 0x33 },
	3974	+ { 0x5401b, 0x4866 },
	3975	+ { 0x5401c, 0x4800 },
	3976	+ { 0x5401e, 0x16 },
	3977	+ { 0x5401f, 0x24c4 },
	3978	+ { 0x54020, 0x33 },
	3979	+ { 0x54021, 0x4866 },
	3980	+ { 0x54022, 0x4800 },
	3981	+ { 0x54024, 0x16 },
	3982	+ { 0x5402b, 0x1000 },
	3983	+ { 0x5402c, 0x3 },
	3984	+ { 0x54032, 0xc400 },
	3985	+ { 0x54033, 0x3324 },
	3986	+ { 0x54034, 0x6600 },
	3987	+ { 0x54035, 0x48 },
	3988	+ { 0x54036, 0x48 },
	3989	+ { 0x54037, 0x1600 },
	3990	+ { 0x54038, 0xc400 },
	3991	+ { 0x54039, 0x3324 },
	3992	+#else
	3993	+ { 0x54003, 0xfa0 },
	3994	+ { 0x54004, 0x2 },
	3995	+ { 0x54005, 0x2228 },
	3996	+ { 0x54006, 0x14 },
	3997	+ { 0x54008, 0x61 },
	3998	+ { 0x54009, 0xc8 },
	3999	+ { 0x5400b, 0x2 },
	4000	+ { 0x5400f, 0x100 },
	4001	+ { 0x54010, 0x1f7f },
	4002	+ { 0x54012, 0x310 },
	4003	+ { 0x54019, 0x3ff4 },
	4004	+ { 0x5401a, 0x33 },
	4005	+ { 0x5401b, 0x4866 },
	4006	+ { 0x5401c, 0x4800 },
	4007	+ { 0x5401e, 0x16 },
	4008	+ { 0x5401f, 0x3ff4 },
	4009	+ { 0x54020, 0x33 },
	4010	+ { 0x54021, 0x4866 },
	4011	+ { 0x54022, 0x4800 },
	4012	+ { 0x54024, 0x16 },
	4013	+ { 0x5402b, 0x1000 },
	4014	+ { 0x5402c, 0x3 },
	4015	+ { 0x54032, 0xf400 },
	4016	+ { 0x54033, 0x333f },
	4017	+ { 0x54034, 0x6600 },
	4018	+ { 0x54035, 0x48 },
	4019	+ { 0x54036, 0x48 },
	4020	+ { 0x54037, 0x1600 },
	4021	+ { 0x54038, 0xf400 },
	4022	+ { 0x54039, 0x333f },
	4023	+#endif
	4024	+ { 0x5403a, 0x6600 },
	4025	+ { 0x5403b, 0x48 },
	4026	+ { 0x5403c, 0x48 },
	4027	+ { 0x5403d, 0x1600 },
	4028	+ { 0xd0000, 0x1 },
	4029	+};
	4030	+
	4031	+/* DRAM PHY init engine image */
	4032	+struct dram_cfg_param ddr_phy_pie[] = {
	4033	+ { 0xd0000, 0x0 },
	4034	+ { 0x90000, 0x10 },
	4035	+ { 0x90001, 0x400 },
	4036	+ { 0x90002, 0x10e },
	4037	+ { 0x90003, 0x0 },
	4038	+ { 0x90004, 0x0 },
	4039	+ { 0x90005, 0x8 },
	4040	+ { 0x90029, 0xb },
	4041	+ { 0x9002a, 0x480 },
	4042	+ { 0x9002b, 0x109 },
	4043	+ { 0x9002c, 0x8 },
	4044	+ { 0x9002d, 0x448 },
	4045	+ { 0x9002e, 0x139 },
	4046	+ { 0x9002f, 0x8 },
	4047	+ { 0x90030, 0x478 },
	4048	+ { 0x90031, 0x109 },
	4049	+ { 0x90032, 0x0 },
	4050	+ { 0x90033, 0xe8 },
	4051	+ { 0x90034, 0x109 },
	4052	+ { 0x90035, 0x2 },
	4053	+ { 0x90036, 0x10 },
	4054	+ { 0x90037, 0x139 },
	4055	+ { 0x90038, 0xb },
	4056	+ { 0x90039, 0x7c0 },
	4057	+ { 0x9003a, 0x139 },
	4058	+ { 0x9003b, 0x44 },
	4059	+ { 0x9003c, 0x633 },
	4060	+ { 0x9003d, 0x159 },
	4061	+ { 0x9003e, 0x14f },
	4062	+ { 0x9003f, 0x630 },
	4063	+ { 0x90040, 0x159 },
	4064	+ { 0x90041, 0x47 },
	4065	+ { 0x90042, 0x633 },
	4066	+ { 0x90043, 0x149 },
	4067	+ { 0x90044, 0x4f },
	4068	+ { 0x90045, 0x633 },
	4069	+ { 0x90046, 0x179 },
	4070	+ { 0x90047, 0x8 },
	4071	+ { 0x90048, 0xe0 },
	4072	+ { 0x90049, 0x109 },
	4073	+ { 0x9004a, 0x0 },
	4074	+ { 0x9004b, 0x7c8 },
	4075	+ { 0x9004c, 0x109 },
	4076	+ { 0x9004d, 0x0 },
	4077	+ { 0x9004e, 0x1 },
	4078	+ { 0x9004f, 0x8 },
	4079	+ { 0x90050, 0x0 },
	4080	+ { 0x90051, 0x45a },
	4081	+ { 0x90052, 0x9 },
	4082	+ { 0x90053, 0x0 },
	4083	+ { 0x90054, 0x448 },
	4084	+ { 0x90055, 0x109 },
	4085	+ { 0x90056, 0x40 },
	4086	+ { 0x90057, 0x633 },
	4087	+ { 0x90058, 0x179 },
	4088	+ { 0x90059, 0x1 },
	4089	+ { 0x9005a, 0x618 },
	4090	+ { 0x9005b, 0x109 },
	4091	+ { 0x9005c, 0x40c0 },
	4092	+ { 0x9005d, 0x633 },
	4093	+ { 0x9005e, 0x149 },
	4094	+ { 0x9005f, 0x8 },
	4095	+ { 0x90060, 0x4 },
	4096	+ { 0x90061, 0x48 },
	4097	+ { 0x90062, 0x4040 },
	4098	+ { 0x90063, 0x633 },
	4099	+ { 0x90064, 0x149 },
	4100	+ { 0x90065, 0x0 },
	4101	+ { 0x90066, 0x4 },
	4102	+ { 0x90067, 0x48 },
	4103	+ { 0x90068, 0x40 },
	4104	+ { 0x90069, 0x633 },
	4105	+ { 0x9006a, 0x149 },
	4106	+ { 0x9006b, 0x10 },
	4107	+ { 0x9006c, 0x4 },
	4108	+ { 0x9006d, 0x18 },
	4109	+ { 0x9006e, 0x0 },
	4110	+ { 0x9006f, 0x4 },
	4111	+ { 0x90070, 0x78 },
	4112	+ { 0x90071, 0x549 },
	4113	+ { 0x90072, 0x633 },
	4114	+ { 0x90073, 0x159 },
	4115	+ { 0x90074, 0xd49 },
	4116	+ { 0x90075, 0x633 },
	4117	+ { 0x90076, 0x159 },
	4118	+ { 0x90077, 0x94a },
	4119	+ { 0x90078, 0x633 },
	4120	+ { 0x90079, 0x159 },
	4121	+ { 0x9007a, 0x441 },
	4122	+ { 0x9007b, 0x633 },
	4123	+ { 0x9007c, 0x149 },
	4124	+ { 0x9007d, 0x42 },
	4125	+ { 0x9007e, 0x633 },
	4126	+ { 0x9007f, 0x149 },
	4127	+ { 0x90080, 0x1 },
	4128	+ { 0x90081, 0x633 },
	4129	+ { 0x90082, 0x149 },
	4130	+ { 0x90083, 0x0 },
	4131	+ { 0x90084, 0xe0 },
	4132	+ { 0x90085, 0x109 },
	4133	+ { 0x90086, 0xa },
	4134	+ { 0x90087, 0x10 },
	4135	+ { 0x90088, 0x109 },
	4136	+ { 0x90089, 0x9 },
	4137	+ { 0x9008a, 0x3c0 },
	4138	+ { 0x9008b, 0x149 },
	4139	+ { 0x9008c, 0x9 },
	4140	+ { 0x9008d, 0x3c0 },
	4141	+ { 0x9008e, 0x159 },
	4142	+ { 0x9008f, 0x18 },
	4143	+ { 0x90090, 0x10 },
	4144	+ { 0x90091, 0x109 },
	4145	+ { 0x90092, 0x0 },
	4146	+ { 0x90093, 0x3c0 },
	4147	+ { 0x90094, 0x109 },
	4148	+ { 0x90095, 0x18 },
	4149	+ { 0x90096, 0x4 },
	4150	+ { 0x90097, 0x48 },
	4151	+ { 0x90098, 0x18 },
	4152	+ { 0x90099, 0x4 },
	4153	+ { 0x9009a, 0x58 },
	4154	+ { 0x9009b, 0xb },
	4155	+ { 0x9009c, 0x10 },
	4156	+ { 0x9009d, 0x109 },
	4157	+ { 0x9009e, 0x1 },
	4158	+ { 0x9009f, 0x10 },
	4159	+ { 0x900a0, 0x109 },
	4160	+ { 0x900a1, 0x5 },
	4161	+ { 0x900a2, 0x7c0 },
	4162	+ { 0x900a3, 0x109 },
	4163	+ { 0x40000, 0x811 },
	4164	+ { 0x40020, 0x880 },
	4165	+ { 0x40040, 0x0 },
	4166	+ { 0x40060, 0x0 },
	4167	+ { 0x40001, 0x4008 },
	4168	+ { 0x40021, 0x83 },
	4169	+ { 0x40041, 0x4f },
	4170	+ { 0x40061, 0x0 },
	4171	+ { 0x40002, 0x4040 },
	4172	+ { 0x40022, 0x83 },
	4173	+ { 0x40042, 0x51 },
	4174	+ { 0x40062, 0x0 },
	4175	+ { 0x40003, 0x811 },
	4176	+ { 0x40023, 0x880 },
	4177	+ { 0x40043, 0x0 },
	4178	+ { 0x40063, 0x0 },
	4179	+ { 0x40004, 0x720 },
	4180	+ { 0x40024, 0xf },
	4181	+ { 0x40044, 0x1740 },
	4182	+ { 0x40064, 0x0 },
	4183	+ { 0x40005, 0x16 },
	4184	+ { 0x40025, 0x83 },
	4185	+ { 0x40045, 0x4b },
	4186	+ { 0x40065, 0x0 },
	4187	+ { 0x40006, 0x716 },
	4188	+ { 0x40026, 0xf },
	4189	+ { 0x40046, 0x2001 },
	4190	+ { 0x40066, 0x0 },
	4191	+ { 0x40007, 0x716 },
	4192	+ { 0x40027, 0xf },
	4193	+ { 0x40047, 0x2800 },
	4194	+ { 0x40067, 0x0 },
	4195	+ { 0x40008, 0x716 },
	4196	+ { 0x40028, 0xf },
	4197	+ { 0x40048, 0xf00 },
	4198	+ { 0x40068, 0x0 },
	4199	+ { 0x40009, 0x720 },
	4200	+ { 0x40029, 0xf },
	4201	+ { 0x40049, 0x1400 },
	4202	+ { 0x40069, 0x0 },
	4203	+ { 0x4000a, 0xe08 },
	4204	+ { 0x4002a, 0xc15 },
	4205	+ { 0x4004a, 0x0 },
	4206	+ { 0x4006a, 0x0 },
	4207	+ { 0x4000b, 0x625 },
	4208	+ { 0x4002b, 0x15 },
	4209	+ { 0x4004b, 0x0 },
	4210	+ { 0x4006b, 0x0 },
	4211	+ { 0x4000c, 0x4028 },
	4212	+ { 0x4002c, 0x80 },
	4213	+ { 0x4004c, 0x0 },
	4214	+ { 0x4006c, 0x0 },
	4215	+ { 0x4000d, 0xe08 },
	4216	+ { 0x4002d, 0xc1a },
	4217	+ { 0x4004d, 0x0 },
	4218	+ { 0x4006d, 0x0 },
	4219	+ { 0x4000e, 0x625 },
	4220	+ { 0x4002e, 0x1a },
	4221	+ { 0x4004e, 0x0 },
	4222	+ { 0x4006e, 0x0 },
	4223	+ { 0x4000f, 0x4040 },
	4224	+ { 0x4002f, 0x80 },
	4225	+ { 0x4004f, 0x0 },
	4226	+ { 0x4006f, 0x0 },
	4227	+ { 0x40010, 0x2604 },
	4228	+ { 0x40030, 0x15 },
	4229	+ { 0x40050, 0x0 },
	4230	+ { 0x40070, 0x0 },
	4231	+ { 0x40011, 0x708 },
	4232	+ { 0x40031, 0x5 },
	4233	+ { 0x40051, 0x0 },
	4234	+ { 0x40071, 0x2002 },
	4235	+ { 0x40012, 0x8 },
	4236	+ { 0x40032, 0x80 },
	4237	+ { 0x40052, 0x0 },
	4238	+ { 0x40072, 0x0 },
	4239	+ { 0x40013, 0x2604 },
	4240	+ { 0x40033, 0x1a },
	4241	+ { 0x40053, 0x0 },
	4242	+ { 0x40073, 0x0 },
	4243	+ { 0x40014, 0x708 },
	4244	+ { 0x40034, 0xa },
	4245	+ { 0x40054, 0x0 },
	4246	+ { 0x40074, 0x2002 },
	4247	+ { 0x40015, 0x4040 },
	4248	+ { 0x40035, 0x80 },
	4249	+ { 0x40055, 0x0 },
	4250	+ { 0x40075, 0x0 },
	4251	+ { 0x40016, 0x60a },
	4252	+ { 0x40036, 0x15 },
	4253	+ { 0x40056, 0x1200 },
	4254	+ { 0x40076, 0x0 },
	4255	+ { 0x40017, 0x61a },
	4256	+ { 0x40037, 0x15 },
	4257	+ { 0x40057, 0x1300 },
	4258	+ { 0x40077, 0x0 },
	4259	+ { 0x40018, 0x60a },
	4260	+ { 0x40038, 0x1a },
	4261	+ { 0x40058, 0x1200 },
	4262	+ { 0x40078, 0x0 },
	4263	+ { 0x40019, 0x642 },
	4264	+ { 0x40039, 0x1a },
	4265	+ { 0x40059, 0x1300 },
	4266	+ { 0x40079, 0x0 },
	4267	+ { 0x4001a, 0x4808 },
	4268	+ { 0x4003a, 0x880 },
	4269	+ { 0x4005a, 0x0 },
	4270	+ { 0x4007a, 0x0 },
	4271	+ { 0x900a4, 0x0 },
	4272	+ { 0x900a5, 0x790 },
	4273	+ { 0x900a6, 0x11a },
	4274	+ { 0x900a7, 0x8 },
	4275	+ { 0x900a8, 0x7aa },
	4276	+ { 0x900a9, 0x2a },
	4277	+ { 0x900aa, 0x10 },
	4278	+ { 0x900ab, 0x7b2 },
	4279	+ { 0x900ac, 0x2a },
	4280	+ { 0x900ad, 0x0 },
	4281	+ { 0x900ae, 0x7c8 },
	4282	+ { 0x900af, 0x109 },
	4283	+ { 0x900b0, 0x10 },
	4284	+ { 0x900b1, 0x10 },
	4285	+ { 0x900b2, 0x109 },
	4286	+ { 0x900b3, 0x10 },
	4287	+ { 0x900b4, 0x2a8 },
	4288	+ { 0x900b5, 0x129 },
	4289	+ { 0x900b6, 0x8 },
	4290	+ { 0x900b7, 0x370 },
	4291	+ { 0x900b8, 0x129 },
	4292	+ { 0x900b9, 0xa },
	4293	+ { 0x900ba, 0x3c8 },
	4294	+ { 0x900bb, 0x1a9 },
	4295	+ { 0x900bc, 0xc },
	4296	+ { 0x900bd, 0x408 },
	4297	+ { 0x900be, 0x199 },
	4298	+ { 0x900bf, 0x14 },
	4299	+ { 0x900c0, 0x790 },
	4300	+ { 0x900c1, 0x11a },
	4301	+ { 0x900c2, 0x8 },
	4302	+ { 0x900c3, 0x4 },
	4303	+ { 0x900c4, 0x18 },
	4304	+ { 0x900c5, 0xe },
	4305	+ { 0x900c6, 0x408 },
	4306	+ { 0x900c7, 0x199 },
	4307	+ { 0x900c8, 0x8 },
	4308	+ { 0x900c9, 0x8568 },
	4309	+ { 0x900ca, 0x108 },
	4310	+ { 0x900cb, 0x18 },
	4311	+ { 0x900cc, 0x790 },
	4312	+ { 0x900cd, 0x16a },
	4313	+ { 0x900ce, 0x8 },
	4314	+ { 0x900cf, 0x1d8 },
	4315	+ { 0x900d0, 0x169 },
	4316	+ { 0x900d1, 0x10 },
	4317	+ { 0x900d2, 0x8558 },
	4318	+ { 0x900d3, 0x168 },
	4319	+ { 0x900d4, 0x70 },
	4320	+ { 0x900d5, 0x788 },
	4321	+ { 0x900d6, 0x16a },
	4322	+ { 0x900d7, 0x1ff8 },
	4323	+ { 0x900d8, 0x85a8 },
	4324	+ { 0x900d9, 0x1e8 },
	4325	+ { 0x900da, 0x50 },
	4326	+ { 0x900db, 0x798 },
	4327	+ { 0x900dc, 0x16a },
	4328	+ { 0x900dd, 0x60 },
	4329	+ { 0x900de, 0x7a0 },
	4330	+ { 0x900df, 0x16a },
	4331	+ { 0x900e0, 0x8 },
	4332	+ { 0x900e1, 0x8310 },
	4333	+ { 0x900e2, 0x168 },
	4334	+ { 0x900e3, 0x8 },
	4335	+ { 0x900e4, 0xa310 },
	4336	+ { 0x900e5, 0x168 },
	4337	+ { 0x900e6, 0xa },
	4338	+ { 0x900e7, 0x408 },
	4339	+ { 0x900e8, 0x169 },
	4340	+ { 0x900e9, 0x6e },
	4341	+ { 0x900ea, 0x0 },
	4342	+ { 0x900eb, 0x68 },
	4343	+ { 0x900ec, 0x0 },
	4344	+ { 0x900ed, 0x408 },
	4345	+ { 0x900ee, 0x169 },
	4346	+ { 0x900ef, 0x0 },
	4347	+ { 0x900f0, 0x8310 },
	4348	+ { 0x900f1, 0x168 },
	4349	+ { 0x900f2, 0x0 },
	4350	+ { 0x900f3, 0xa310 },
	4351	+ { 0x900f4, 0x168 },
	4352	+ { 0x900f5, 0x1ff8 },
	4353	+ { 0x900f6, 0x85a8 },
	4354	+ { 0x900f7, 0x1e8 },
	4355	+ { 0x900f8, 0x68 },
	4356	+ { 0x900f9, 0x798 },
	4357	+ { 0x900fa, 0x16a },
	4358	+ { 0x900fb, 0x78 },
	4359	+ { 0x900fc, 0x7a0 },
	4360	+ { 0x900fd, 0x16a },
	4361	+ { 0x900fe, 0x68 },
	4362	+ { 0x900ff, 0x790 },
	4363	+ { 0x90100, 0x16a },
	4364	+ { 0x90101, 0x8 },
	4365	+ { 0x90102, 0x8b10 },
	4366	+ { 0x90103, 0x168 },
	4367	+ { 0x90104, 0x8 },
	4368	+ { 0x90105, 0xab10 },
	4369	+ { 0x90106, 0x168 },
	4370	+ { 0x90107, 0xa },
	4371	+ { 0x90108, 0x408 },
	4372	+ { 0x90109, 0x169 },
	4373	+ { 0x9010a, 0x58 },
	4374	+ { 0x9010b, 0x0 },
	4375	+ { 0x9010c, 0x68 },
	4376	+ { 0x9010d, 0x0 },
	4377	+ { 0x9010e, 0x408 },
	4378	+ { 0x9010f, 0x169 },
	4379	+ { 0x90110, 0x0 },
	4380	+ { 0x90111, 0x8b10 },
	4381	+ { 0x90112, 0x168 },
	4382	+ { 0x90113, 0x1 },
	4383	+ { 0x90114, 0xab10 },
	4384	+ { 0x90115, 0x168 },
	4385	+ { 0x90116, 0x0 },
	4386	+ { 0x90117, 0x1d8 },
	4387	+ { 0x90118, 0x169 },
	4388	+ { 0x90119, 0x80 },
	4389	+ { 0x9011a, 0x790 },
	4390	+ { 0x9011b, 0x16a },
	4391	+ { 0x9011c, 0x18 },
	4392	+ { 0x9011d, 0x7aa },
	4393	+ { 0x9011e, 0x6a },
	4394	+ { 0x9011f, 0xa },
	4395	+ { 0x90120, 0x0 },
	4396	+ { 0x90121, 0x1e9 },
	4397	+ { 0x90122, 0x8 },
	4398	+ { 0x90123, 0x8080 },
	4399	+ { 0x90124, 0x108 },
	4400	+ { 0x90125, 0xf },
	4401	+ { 0x90126, 0x408 },
	4402	+ { 0x90127, 0x169 },
	4403	+ { 0x90128, 0xc },
	4404	+ { 0x90129, 0x0 },
	4405	+ { 0x9012a, 0x68 },
	4406	+ { 0x9012b, 0x9 },
	4407	+ { 0x9012c, 0x0 },
	4408	+ { 0x9012d, 0x1a9 },
	4409	+ { 0x9012e, 0x0 },
	4410	+ { 0x9012f, 0x408 },
	4411	+ { 0x90130, 0x169 },
	4412	+ { 0x90131, 0x0 },
	4413	+ { 0x90132, 0x8080 },
	4414	+ { 0x90133, 0x108 },
	4415	+ { 0x90134, 0x8 },
	4416	+ { 0x90135, 0x7aa },
	4417	+ { 0x90136, 0x6a },
	4418	+ { 0x90137, 0x0 },
	4419	+ { 0x90138, 0x8568 },
	4420	+ { 0x90139, 0x108 },
	4421	+ { 0x9013a, 0xb7 },
	4422	+ { 0x9013b, 0x790 },
	4423	+ { 0x9013c, 0x16a },
	4424	+ { 0x9013d, 0x1f },
	4425	+ { 0x9013e, 0x0 },
	4426	+ { 0x9013f, 0x68 },
	4427	+ { 0x90140, 0x8 },
	4428	+ { 0x90141, 0x8558 },
	4429	+ { 0x90142, 0x168 },
	4430	+ { 0x90143, 0xf },
	4431	+ { 0x90144, 0x408 },
	4432	+ { 0x90145, 0x169 },
	4433	+ { 0x90146, 0xd },
	4434	+ { 0x90147, 0x0 },
	4435	+ { 0x90148, 0x68 },
	4436	+ { 0x90149, 0x0 },
	4437	+ { 0x9014a, 0x408 },
	4438	+ { 0x9014b, 0x169 },
	4439	+ { 0x9014c, 0x0 },
	4440	+ { 0x9014d, 0x8558 },
	4441	+ { 0x9014e, 0x168 },
	4442	+ { 0x9014f, 0x8 },
	4443	+ { 0x90150, 0x3c8 },
	4444	+ { 0x90151, 0x1a9 },
	4445	+ { 0x90152, 0x3 },
	4446	+ { 0x90153, 0x370 },
	4447	+ { 0x90154, 0x129 },
	4448	+ { 0x90155, 0x20 },
	4449	+ { 0x90156, 0x2aa },
	4450	+ { 0x90157, 0x9 },
	4451	+ { 0x90158, 0x8 },
	4452	+ { 0x90159, 0xe8 },
	4453	+ { 0x9015a, 0x109 },
	4454	+ { 0x9015b, 0x0 },
	4455	+ { 0x9015c, 0x8140 },
	4456	+ { 0x9015d, 0x10c },
	4457	+ { 0x9015e, 0x10 },
	4458	+ { 0x9015f, 0x8138 },
	4459	+ { 0x90160, 0x104 },
	4460	+ { 0x90161, 0x8 },
	4461	+ { 0x90162, 0x448 },
	4462	+ { 0x90163, 0x109 },
	4463	+ { 0x90164, 0xf },
	4464	+ { 0x90165, 0x7c0 },
	4465	+ { 0x90166, 0x109 },
	4466	+ { 0x90167, 0x0 },
	4467	+ { 0x90168, 0xe8 },
	4468	+ { 0x90169, 0x109 },
	4469	+ { 0x9016a, 0x47 },
	4470	+ { 0x9016b, 0x630 },
	4471	+ { 0x9016c, 0x109 },
	4472	+ { 0x9016d, 0x8 },
	4473	+ { 0x9016e, 0x618 },
	4474	+ { 0x9016f, 0x109 },
	4475	+ { 0x90170, 0x8 },
	4476	+ { 0x90171, 0xe0 },
	4477	+ { 0x90172, 0x109 },
	4478	+ { 0x90173, 0x0 },
	4479	+ { 0x90174, 0x7c8 },
	4480	+ { 0x90175, 0x109 },
	4481	+ { 0x90176, 0x8 },
	4482	+ { 0x90177, 0x8140 },
	4483	+ { 0x90178, 0x10c },
	4484	+ { 0x90179, 0x0 },
	4485	+ { 0x9017a, 0x478 },
	4486	+ { 0x9017b, 0x109 },
	4487	+ { 0x9017c, 0x0 },
	4488	+ { 0x9017d, 0x1 },
	4489	+ { 0x9017e, 0x8 },
	4490	+ { 0x9017f, 0x8 },
	4491	+ { 0x90180, 0x4 },
	4492	+ { 0x90181, 0x0 },
	4493	+ { 0x90006, 0x8 },
	4494	+ { 0x90007, 0x7c8 },
	4495	+ { 0x90008, 0x109 },
	4496	+ { 0x90009, 0x0 },
	4497	+ { 0x9000a, 0x400 },
	4498	+ { 0x9000b, 0x106 },
	4499	+ { 0xd00e7, 0x400 },
	4500	+ { 0x90017, 0x0 },
	4501	+ { 0x9001f, 0x29 },
	4502	+ { 0x90026, 0x68 },
	4503	+ { 0x400d0, 0x0 },
	4504	+ { 0x400d1, 0x101 },
	4505	+ { 0x400d2, 0x105 },
	4506	+ { 0x400d3, 0x107 },
	4507	+ { 0x400d4, 0x10f },
	4508	+ { 0x400d5, 0x202 },
	4509	+ { 0x400d6, 0x20a },
	4510	+ { 0x400d7, 0x20b },
	4511	+ { 0x2003a, 0x2 },
	4512	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	4513	+ { 0x2000b, 0x4b },
	4514	+ { 0x2000c, 0x96 },
	4515	+ { 0x2000d, 0x5dc },
	4516	+#else
	4517	+ { 0x200be, 0x3 },
	4518	+ { 0x2000b, 0x7d },
	4519	+ { 0x2000c, 0xfa },
	4520	+ { 0x2000d, 0x9c4 },
	4521	+#endif
	4522	+ { 0x2000e, 0x2c },
	4523	+ { 0x12000b, 0xc },
	4524	+ { 0x12000c, 0x19 },
	4525	+ { 0x12000d, 0xfa },
	4526	+ { 0x12000e, 0x10 },
	4527	+ { 0x22000b, 0x3 },
	4528	+ { 0x22000c, 0x6 },
	4529	+ { 0x22000d, 0x3e },
	4530	+ { 0x22000e, 0x10 },
	4531	+ { 0x9000c, 0x0 },
	4532	+ { 0x9000d, 0x173 },
	4533	+ { 0x9000e, 0x60 },
	4534	+ { 0x9000f, 0x6110 },
	4535	+ { 0x90010, 0x2152 },
	4536	+ { 0x90011, 0xdfbd },
	4537	+ { 0x90012, 0x2060 },
	4538	+ { 0x90013, 0x6152 },
	4539	+ { 0x20010, 0x5a },
	4540	+ { 0x20011, 0x3 },
	4541	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	4542	+ { 0x120010, 0x5a },
	4543	+ { 0x120011, 0x3 },
	4544	+ { 0x220010, 0x5a },
	4545	+ { 0x220011, 0x3 },
	4546	+#endif
	4547	+ { 0x40080, 0xe0 },
	4548	+ { 0x40081, 0x12 },
	4549	+ { 0x40082, 0xe0 },
	4550	+ { 0x40083, 0x12 },
	4551	+ { 0x40084, 0xe0 },
	4552	+ { 0x40085, 0x12 },
	4553	+ { 0x140080, 0xe0 },
	4554	+ { 0x140081, 0x12 },
	4555	+ { 0x140082, 0xe0 },
	4556	+ { 0x140083, 0x12 },
	4557	+ { 0x140084, 0xe0 },
	4558	+ { 0x140085, 0x12 },
	4559	+ { 0x240080, 0xe0 },
	4560	+ { 0x240081, 0x12 },
	4561	+ { 0x240082, 0xe0 },
	4562	+ { 0x240083, 0x12 },
	4563	+ { 0x240084, 0xe0 },
	4564	+ { 0x240085, 0x12 },
	4565	+ { 0x400fd, 0xf },
	4566	+ { 0x10011, 0x1 },
	4567	+ { 0x10012, 0x1 },
	4568	+ { 0x10013, 0x180 },
	4569	+ { 0x10018, 0x1 },
	4570	+ { 0x10002, 0x6209 },
	4571	+ { 0x100b2, 0x1 },
	4572	+ { 0x101b4, 0x1 },
	4573	+ { 0x102b4, 0x1 },
	4574	+ { 0x103b4, 0x1 },
	4575	+ { 0x104b4, 0x1 },
	4576	+ { 0x105b4, 0x1 },
	4577	+ { 0x106b4, 0x1 },
	4578	+ { 0x107b4, 0x1 },
	4579	+ { 0x108b4, 0x1 },
	4580	+ { 0x11011, 0x1 },
	4581	+ { 0x11012, 0x1 },
	4582	+ { 0x11013, 0x180 },
	4583	+ { 0x11018, 0x1 },
	4584	+ { 0x11002, 0x6209 },
	4585	+ { 0x110b2, 0x1 },
	4586	+ { 0x111b4, 0x1 },
	4587	+ { 0x112b4, 0x1 },
	4588	+ { 0x113b4, 0x1 },
	4589	+ { 0x114b4, 0x1 },
	4590	+ { 0x115b4, 0x1 },
	4591	+ { 0x116b4, 0x1 },
	4592	+ { 0x117b4, 0x1 },
	4593	+ { 0x118b4, 0x1 },
	4594	+ { 0x12011, 0x1 },
	4595	+ { 0x12012, 0x1 },
	4596	+ { 0x12013, 0x180 },
	4597	+ { 0x12018, 0x1 },
	4598	+ { 0x12002, 0x6209 },
	4599	+ { 0x120b2, 0x1 },
	4600	+ { 0x121b4, 0x1 },
	4601	+ { 0x122b4, 0x1 },
	4602	+ { 0x123b4, 0x1 },
	4603	+ { 0x124b4, 0x1 },
	4604	+ { 0x125b4, 0x1 },
	4605	+ { 0x126b4, 0x1 },
	4606	+ { 0x127b4, 0x1 },
	4607	+ { 0x128b4, 0x1 },
	4608	+ { 0x13011, 0x1 },
	4609	+ { 0x13012, 0x1 },
	4610	+ { 0x13013, 0x180 },
	4611	+ { 0x13018, 0x1 },
	4612	+ { 0x13002, 0x6209 },
	4613	+ { 0x130b2, 0x1 },
	4614	+ { 0x131b4, 0x1 },
	4615	+ { 0x132b4, 0x1 },
	4616	+ { 0x133b4, 0x1 },
	4617	+ { 0x134b4, 0x1 },
	4618	+ { 0x135b4, 0x1 },
	4619	+ { 0x136b4, 0x1 },
	4620	+ { 0x137b4, 0x1 },
	4621	+ { 0x138b4, 0x1 },
	4622	+ { 0x20089, 0x1 },
	4623	+ { 0x20088, 0x19 },
	4624	+ { 0xc0080, 0x2 },
	4625	+ { 0xd0000, 0x1 }
	4626	+};
	4627	+
	4628	+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
	4629	+ {
	4630	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	4631	+ /* P0 2400mts 1D */
	4632	+ .drate = 2400,
	4633	+#else
	4634	+ /* P0 4000mts 1D */
	4635	+ .drate = 4000,
	4636	+#endif
	4637	+ .fw_type = FW_1D_IMAGE,
	4638	+ .fsp_cfg = ddr_fsp0_cfg,
	4639	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
	4640	+ },
	4641	+ {
	4642	+ /* P1 400mts 1D */
	4643	+ .drate = 400,
	4644	+ .fw_type = FW_1D_IMAGE,
	4645	+ .fsp_cfg = ddr_fsp1_cfg,
	4646	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
	4647	+ },
	4648	+ {
	4649	+ /* P2 100mts 1D */
	4650	+ .drate = 100,
	4651	+ .fw_type = FW_1D_IMAGE,
	4652	+ .fsp_cfg = ddr_fsp2_cfg,
	4653	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
	4654	+ },
	4655	+ {
	4656	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	4657	+ /* P0 2400mts 2D */
	4658	+ .drate = 2400,
	4659	+#else
	4660	+ /* P0 4000mts 2D */
	4661	+ .drate = 4000,
	4662	+#endif
	4663	+ .fw_type = FW_2D_IMAGE,
	4664	+ .fsp_cfg = ddr_fsp0_2d_cfg,
	4665	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
	4666	+ },
	4667	+};
	4668	+
	4669	+/* ddr timing config params */
	4670	+struct dram_timing_info dram_timing = {
	4671	+ .ddrc_cfg = ddr_ddrc_cfg,
	4672	+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
	4673	+ .ddrphy_cfg = ddr_ddrphy_cfg,
	4674	+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
	4675	+ .fsp_msg = ddr_dram_fsp_msg,
	4676	+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
	4677	+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
	4678	+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
	4679	+ .ddrphy_pie = ddr_phy_pie,
	4680	+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
	4681	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	4682	+ .fsp_table = { 2400, 400, 100, },
	4683	+#else
	4684	+ .fsp_table = { 4000, 400, 100, },
	4685	+#endif
	4686	+};
	4687	+
	4688	+#ifndef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	4689	+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
	4690	+void board_dram_ecc_scrub(void)
	4691	+{
	4692	+ ddrc_inline_ecc_scrub(0x0, 0x3ffffff);
	4693	+ ddrc_inline_ecc_scrub(0x20000000, 0x23ffffff);
	4694	+ ddrc_inline_ecc_scrub(0x40000000, 0x43ffffff);
	4695	+ ddrc_inline_ecc_scrub(0x4000000, 0x7ffffff);
	4696	+ ddrc_inline_ecc_scrub(0x24000000, 0x27ffffff);
	4697	+ ddrc_inline_ecc_scrub(0x44000000, 0x47ffffff);
	4698	+ ddrc_inline_ecc_scrub(0x8000000, 0xbffffff);
	4699	+ ddrc_inline_ecc_scrub(0x28000000, 0x2bffffff);
	4700	+ ddrc_inline_ecc_scrub(0x48000000, 0x4bffffff);
	4701	+ ddrc_inline_ecc_scrub(0xc000000, 0xfffffff);
	4702	+ ddrc_inline_ecc_scrub(0x2c000000, 0x2fffffff);
	4703	+ ddrc_inline_ecc_scrub(0x4c000000, 0x4fffffff);
	4704	+ ddrc_inline_ecc_scrub(0x10000000, 0x13ffffff);
	4705	+ ddrc_inline_ecc_scrub(0x30000000, 0x33ffffff);
	4706	+ ddrc_inline_ecc_scrub(0x50000000, 0x53ffffff);
	4707	+ ddrc_inline_ecc_scrub(0x14000000, 0x17ffffff);
	4708	+ ddrc_inline_ecc_scrub(0x34000000, 0x37ffffff);
	4709	+ ddrc_inline_ecc_scrub(0x54000000, 0x57ffffff);
	4710	+ ddrc_inline_ecc_scrub(0x18000000, 0x1bffffff);
	4711	+ ddrc_inline_ecc_scrub(0x38000000, 0x3bffffff);
	4712	+ ddrc_inline_ecc_scrub(0x58000000, 0x5bffffff);
	4713	+ ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff);
	4714	+}
	4715	+#endif
	4716	+#endif
	4717	diff --git a/board/freescale/gauguin-imx8mp/lpddr4_timing_ndm.c b/board/freescale/gauguin-imx8mp/lpddr4_timing_ndm.c
	4718	new file mode 100644
	4719	index 00000000..4765618a
	4720	--- /dev/null
	4721	+++ b/board/freescale/gauguin-imx8mp/lpddr4_timing_ndm.c
	4722	@@ -0,0 +1,1853 @@
	4723	+/*
	4724	+ * Copyright 2021 NXP
	4725	+ *
	4726	+ * SPDX-License-Identifier: GPL-2.0+
	4727	+ *
	4728	+ * Generated code from MX8M_DDR_tool
	4729	+ *
	4730	+ * Align with uboot version:
	4731	+ * imx_v2019.04_5.4.x and above version
	4732	+ * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
	4733	+ * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h>
	4734	+ */
	4735	+
	4736	+#include <linux/kernel.h>
	4737	+#include <asm/arch/ddr.h>
	4738	+
	4739	+struct dram_cfg_param ddr_ddrc_cfg[] = {
	4740	+ / Initialize DDRC registers /
	4741	+ { 0x3d400304, 0x1 },
	4742	+ { 0x3d400030, 0x1 },
	4743	+ { 0x3d400000, 0xa3080020 },
	4744	+ { 0x3d400020, 0x1223 },
	4745	+ { 0x3d400024, 0x186a000 },
	4746	+ { 0x3d400064, 0x610130 },
	4747	+ { 0x3d400070, 0x1027f10 },
	4748	+ { 0x3d400074, 0x7b0 },
	4749	+ { 0x3d4000d0, 0xc003061c },
	4750	+ { 0x3d4000d4, 0x9e0000 },
	4751	+ { 0x3d4000dc, 0xd4002d },
	4752	+ { 0x3d4000e0, 0x330000 },
	4753	+ { 0x3d4000e8, 0x660048 },
	4754	+ { 0x3d4000ec, 0x160048 },
	4755	+ { 0x3d400100, 0x1a201b22 },
	4756	+ { 0x3d400104, 0x60633 },
	4757	+ { 0x3d40010c, 0xc0c000 },
	4758	+ { 0x3d400110, 0xf04080f },
	4759	+ { 0x3d400114, 0x2040c0c },
	4760	+ { 0x3d400118, 0x1010007 },
	4761	+ { 0x3d40011c, 0x401 },
	4762	+ { 0x3d400130, 0x20600 },
	4763	+ { 0x3d400134, 0xe100002 },
	4764	+ { 0x3d400138, 0x136 },
	4765	+ { 0x3d400144, 0xa00050 },
	4766	+ { 0x3d400180, 0x3200018 },
	4767	+ { 0x3d400184, 0x28061a8 },
	4768	+ { 0x3d400188, 0x0 },
	4769	+ { 0x3d400190, 0x497820a },
	4770	+ { 0x3d400194, 0x80303 },
	4771	+ { 0x3d4001b4, 0x170a },
	4772	+ { 0x3d4001a0, 0xe0400018 },
	4773	+ { 0x3d4001a4, 0xdf00e4 },
	4774	+ { 0x3d4001a8, 0x80000000 },
	4775	+ { 0x3d4001b0, 0x11 },
	4776	+ { 0x3d4001c0, 0x1 },
	4777	+ { 0x3d4001c4, 0x1 },
	4778	+ { 0x3d4000f4, 0xc99 },
	4779	+ { 0x3d400108, 0x70e1617 },
	4780	+ { 0x3d400200, 0x16 },
	4781	+ { 0x3d40020c, 0x0 },
	4782	+ { 0x3d400210, 0x1f1f },
	4783	+ { 0x3d400204, 0x80808 },
	4784	+ { 0x3d400214, 0x7070707 },
	4785	+ { 0x3d400218, 0x68070707 },
	4786	+ { 0x3d40021c, 0xf08 },
	4787	+ { 0x3d400250, 0x1705 },
	4788	+ { 0x3d400254, 0x2c },
	4789	+ { 0x3d40025c, 0x4000030 },
	4790	+ { 0x3d400264, 0x900093e7 },
	4791	+ { 0x3d40026c, 0x2005574 },
	4792	+ { 0x3d400400, 0x111 },
	4793	+ { 0x3d400404, 0x72ff },
	4794	+ { 0x3d400408, 0x72ff },
	4795	+ { 0x3d400494, 0x2100e07 },
	4796	+ { 0x3d400498, 0x620096 },
	4797	+ { 0x3d40049c, 0x1100e07 },
	4798	+ { 0x3d4004a0, 0xc8012c },
	4799	+ { 0x3d402020, 0x1021 },
	4800	+ { 0x3d402024, 0x30d400 },
	4801	+ { 0x3d402050, 0x20d000 },
	4802	+ { 0x3d402064, 0xc0026 },
	4803	+ { 0x3d4020dc, 0x840000 },
	4804	+ { 0x3d4020e0, 0x330000 },
	4805	+ { 0x3d4020e8, 0x660048 },
	4806	+ { 0x3d4020ec, 0x160048 },
	4807	+ { 0x3d402100, 0xa040305 },
	4808	+ { 0x3d402104, 0x30407 },
	4809	+ { 0x3d402108, 0x203060b },
	4810	+ { 0x3d40210c, 0x505000 },
	4811	+ { 0x3d402110, 0x2040202 },
	4812	+ { 0x3d402114, 0x2030202 },
	4813	+ { 0x3d402118, 0x1010004 },
	4814	+ { 0x3d40211c, 0x301 },
	4815	+ { 0x3d402130, 0x20300 },
	4816	+ { 0x3d402134, 0xa100002 },
	4817	+ { 0x3d402138, 0x27 },
	4818	+ { 0x3d402144, 0x14000a },
	4819	+ { 0x3d402180, 0x640004 },
	4820	+ { 0x3d402190, 0x3818200 },
	4821	+ { 0x3d402194, 0x80303 },
	4822	+ { 0x3d4021b4, 0x100 },
	4823	+ { 0x3d4020f4, 0xc99 },
	4824	+ { 0x3d403020, 0x1021 },
	4825	+ { 0x3d403024, 0xc3500 },
	4826	+ { 0x3d403050, 0x20d000 },
	4827	+ { 0x3d403064, 0x3000a },
	4828	+ { 0x3d4030dc, 0x840000 },
	4829	+ { 0x3d4030e0, 0x330000 },
	4830	+ { 0x3d4030e8, 0x660048 },
	4831	+ { 0x3d4030ec, 0x160048 },
	4832	+ { 0x3d403100, 0xa010102 },
	4833	+ { 0x3d403104, 0x30404 },
	4834	+ { 0x3d403108, 0x203060b },
	4835	+ { 0x3d40310c, 0x505000 },
	4836	+ { 0x3d403110, 0x2040202 },
	4837	+ { 0x3d403114, 0x2030202 },
	4838	+ { 0x3d403118, 0x1010004 },
	4839	+ { 0x3d40311c, 0x301 },
	4840	+ { 0x3d403130, 0x20300 },
	4841	+ { 0x3d403134, 0xa100002 },
	4842	+ { 0x3d403138, 0xa },
	4843	+ { 0x3d403144, 0x50003 },
	4844	+ { 0x3d403180, 0x190004 },
	4845	+ { 0x3d403190, 0x3818200 },
	4846	+ { 0x3d403194, 0x80303 },
	4847	+ { 0x3d4031b4, 0x100 },
	4848	+ { 0x3d4030f4, 0xc99 },
	4849	+ { 0x3d400028, 0x0 },
	4850	+};
	4851	+
	4852	+/* PHY Initialize Configuration */
	4853	+struct dram_cfg_param ddr_ddrphy_cfg[] = {
	4854	+ { 0x100a0, 0x0 },
	4855	+ { 0x100a1, 0x1 },
	4856	+ { 0x100a2, 0x2 },
	4857	+ { 0x100a3, 0x3 },
	4858	+ { 0x100a4, 0x4 },
	4859	+ { 0x100a5, 0x5 },
	4860	+ { 0x100a6, 0x6 },
	4861	+ { 0x100a7, 0x7 },
	4862	+ { 0x110a0, 0x0 },
	4863	+ { 0x110a1, 0x1 },
	4864	+ { 0x110a2, 0x3 },
	4865	+ { 0x110a3, 0x4 },
	4866	+ { 0x110a4, 0x5 },
	4867	+ { 0x110a5, 0x2 },
	4868	+ { 0x110a6, 0x7 },
	4869	+ { 0x110a7, 0x6 },
	4870	+ { 0x120a0, 0x0 },
	4871	+ { 0x120a1, 0x1 },
	4872	+ { 0x120a2, 0x3 },
	4873	+ { 0x120a3, 0x2 },
	4874	+ { 0x120a4, 0x5 },
	4875	+ { 0x120a5, 0x4 },
	4876	+ { 0x120a6, 0x7 },
	4877	+ { 0x120a7, 0x6 },
	4878	+ { 0x130a0, 0x0 },
	4879	+ { 0x130a1, 0x1 },
	4880	+ { 0x130a2, 0x2 },
	4881	+ { 0x130a3, 0x3 },
	4882	+ { 0x130a4, 0x4 },
	4883	+ { 0x130a5, 0x5 },
	4884	+ { 0x130a6, 0x6 },
	4885	+ { 0x130a7, 0x7 },
	4886	+ { 0x1005f, 0x1ff },
	4887	+ { 0x1015f, 0x1ff },
	4888	+ { 0x1105f, 0x1ff },
	4889	+ { 0x1115f, 0x1ff },
	4890	+ { 0x1205f, 0x1ff },
	4891	+ { 0x1215f, 0x1ff },
	4892	+ { 0x1305f, 0x1ff },
	4893	+ { 0x1315f, 0x1ff },
	4894	+ { 0x11005f, 0x1ff },
	4895	+ { 0x11015f, 0x1ff },
	4896	+ { 0x11105f, 0x1ff },
	4897	+ { 0x11115f, 0x1ff },
	4898	+ { 0x11205f, 0x1ff },
	4899	+ { 0x11215f, 0x1ff },
	4900	+ { 0x11305f, 0x1ff },
	4901	+ { 0x11315f, 0x1ff },
	4902	+ { 0x21005f, 0x1ff },
	4903	+ { 0x21015f, 0x1ff },
	4904	+ { 0x21105f, 0x1ff },
	4905	+ { 0x21115f, 0x1ff },
	4906	+ { 0x21205f, 0x1ff },
	4907	+ { 0x21215f, 0x1ff },
	4908	+ { 0x21305f, 0x1ff },
	4909	+ { 0x21315f, 0x1ff },
	4910	+ { 0x55, 0x1ff },
	4911	+ { 0x1055, 0x1ff },
	4912	+ { 0x2055, 0x1ff },
	4913	+ { 0x3055, 0x1ff },
	4914	+ { 0x4055, 0x1ff },
	4915	+ { 0x5055, 0x1ff },
	4916	+ { 0x6055, 0x1ff },
	4917	+ { 0x7055, 0x1ff },
	4918	+ { 0x8055, 0x1ff },
	4919	+ { 0x9055, 0x1ff },
	4920	+ { 0x200c5, 0x19 },
	4921	+ { 0x1200c5, 0x7 },
	4922	+ { 0x2200c5, 0x7 },
	4923	+ { 0x2002e, 0x2 },
	4924	+ { 0x12002e, 0x2 },
	4925	+ { 0x22002e, 0x2 },
	4926	+ { 0x90204, 0x0 },
	4927	+ { 0x190204, 0x0 },
	4928	+ { 0x290204, 0x0 },
	4929	+ { 0x20024, 0x1e3 },
	4930	+ { 0x2003a, 0x2 },
	4931	+ { 0x120024, 0x1e3 },
	4932	+ { 0x2003a, 0x2 },
	4933	+ { 0x220024, 0x1e3 },
	4934	+ { 0x2003a, 0x2 },
	4935	+ { 0x20056, 0x3 },
	4936	+ { 0x120056, 0x3 },
	4937	+ { 0x220056, 0x3 },
	4938	+ { 0x1004d, 0xe00 },
	4939	+ { 0x1014d, 0xe00 },
	4940	+ { 0x1104d, 0xe00 },
	4941	+ { 0x1114d, 0xe00 },
	4942	+ { 0x1204d, 0xe00 },
	4943	+ { 0x1214d, 0xe00 },
	4944	+ { 0x1304d, 0xe00 },
	4945	+ { 0x1314d, 0xe00 },
	4946	+ { 0x11004d, 0xe00 },
	4947	+ { 0x11014d, 0xe00 },
	4948	+ { 0x11104d, 0xe00 },
	4949	+ { 0x11114d, 0xe00 },
	4950	+ { 0x11204d, 0xe00 },
	4951	+ { 0x11214d, 0xe00 },
	4952	+ { 0x11304d, 0xe00 },
	4953	+ { 0x11314d, 0xe00 },
	4954	+ { 0x21004d, 0xe00 },
	4955	+ { 0x21014d, 0xe00 },
	4956	+ { 0x21104d, 0xe00 },
	4957	+ { 0x21114d, 0xe00 },
	4958	+ { 0x21204d, 0xe00 },
	4959	+ { 0x21214d, 0xe00 },
	4960	+ { 0x21304d, 0xe00 },
	4961	+ { 0x21314d, 0xe00 },
	4962	+ { 0x10049, 0xeba },
	4963	+ { 0x10149, 0xeba },
	4964	+ { 0x11049, 0xeba },
	4965	+ { 0x11149, 0xeba },
	4966	+ { 0x12049, 0xeba },
	4967	+ { 0x12149, 0xeba },
	4968	+ { 0x13049, 0xeba },
	4969	+ { 0x13149, 0xeba },
	4970	+ { 0x110049, 0xeba },
	4971	+ { 0x110149, 0xeba },
	4972	+ { 0x111049, 0xeba },
	4973	+ { 0x111149, 0xeba },
	4974	+ { 0x112049, 0xeba },
	4975	+ { 0x112149, 0xeba },
	4976	+ { 0x113049, 0xeba },
	4977	+ { 0x113149, 0xeba },
	4978	+ { 0x210049, 0xeba },
	4979	+ { 0x210149, 0xeba },
	4980	+ { 0x211049, 0xeba },
	4981	+ { 0x211149, 0xeba },
	4982	+ { 0x212049, 0xeba },
	4983	+ { 0x212149, 0xeba },
	4984	+ { 0x213049, 0xeba },
	4985	+ { 0x213149, 0xeba },
	4986	+ { 0x43, 0x63 },
	4987	+ { 0x1043, 0x63 },
	4988	+ { 0x2043, 0x63 },
	4989	+ { 0x3043, 0x63 },
	4990	+ { 0x4043, 0x63 },
	4991	+ { 0x5043, 0x63 },
	4992	+ { 0x6043, 0x63 },
	4993	+ { 0x7043, 0x63 },
	4994	+ { 0x8043, 0x63 },
	4995	+ { 0x9043, 0x63 },
	4996	+ { 0x20018, 0x3 },
	4997	+ { 0x20075, 0x4 },
	4998	+ { 0x20050, 0x0 },
	4999	+ { 0x20008, 0x320 },
	5000	+ { 0x120008, 0x64 },
	5001	+ { 0x220008, 0x19 },
	5002	+ { 0x20088, 0x9 },
	5003	+ { 0x200b2, 0x104 },
	5004	+ { 0x10043, 0x5a1 },
	5005	+ { 0x10143, 0x5a1 },
	5006	+ { 0x11043, 0x5a1 },
	5007	+ { 0x11143, 0x5a1 },
	5008	+ { 0x12043, 0x5a1 },
	5009	+ { 0x12143, 0x5a1 },
	5010	+ { 0x13043, 0x5a1 },
	5011	+ { 0x13143, 0x5a1 },
	5012	+ { 0x1200b2, 0x104 },
	5013	+ { 0x110043, 0x5a1 },
	5014	+ { 0x110143, 0x5a1 },
	5015	+ { 0x111043, 0x5a1 },
	5016	+ { 0x111143, 0x5a1 },
	5017	+ { 0x112043, 0x5a1 },
	5018	+ { 0x112143, 0x5a1 },
	5019	+ { 0x113043, 0x5a1 },
	5020	+ { 0x113143, 0x5a1 },
	5021	+ { 0x2200b2, 0x104 },
	5022	+ { 0x210043, 0x5a1 },
	5023	+ { 0x210143, 0x5a1 },
	5024	+ { 0x211043, 0x5a1 },
	5025	+ { 0x211143, 0x5a1 },
	5026	+ { 0x212043, 0x5a1 },
	5027	+ { 0x212143, 0x5a1 },
	5028	+ { 0x213043, 0x5a1 },
	5029	+ { 0x213143, 0x5a1 },
	5030	+ { 0x200fa, 0x1 },
	5031	+ { 0x1200fa, 0x1 },
	5032	+ { 0x2200fa, 0x1 },
	5033	+ { 0x20019, 0x1 },
	5034	+ { 0x120019, 0x1 },
	5035	+ { 0x220019, 0x1 },
	5036	+ { 0x200f0, 0x660 },
	5037	+ { 0x200f1, 0x0 },
	5038	+ { 0x200f2, 0x4444 },
	5039	+ { 0x200f3, 0x8888 },
	5040	+ { 0x200f4, 0x5665 },
	5041	+ { 0x200f5, 0x0 },
	5042	+ { 0x200f6, 0x0 },
	5043	+ { 0x200f7, 0xf000 },
	5044	+ { 0x20025, 0x0 },
	5045	+ { 0x2002d, 0x0 },
	5046	+ { 0x12002d, 0x0 },
	5047	+ { 0x22002d, 0x0 },
	5048	+ { 0x2007d, 0x212 },
	5049	+ { 0x12007d, 0x212 },
	5050	+ { 0x22007d, 0x212 },
	5051	+ { 0x2007c, 0x61 },
	5052	+ { 0x12007c, 0x61 },
	5053	+ { 0x22007c, 0x61 },
	5054	+ { 0x1004a, 0x500 },
	5055	+ { 0x1104a, 0x500 },
	5056	+ { 0x1204a, 0x500 },
	5057	+ { 0x1304a, 0x500 },
	5058	+ { 0x2002c, 0x0 },
	5059	+};
	5060	+
	5061	+/* ddr phy trained csr */
	5062	+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
	5063	+ { 0x200b2, 0x0 },
	5064	+ { 0x1200b2, 0x0 },
	5065	+ { 0x2200b2, 0x0 },
	5066	+ { 0x200cb, 0x0 },
	5067	+ { 0x10043, 0x0 },
	5068	+ { 0x110043, 0x0 },
	5069	+ { 0x210043, 0x0 },
	5070	+ { 0x10143, 0x0 },
	5071	+ { 0x110143, 0x0 },
	5072	+ { 0x210143, 0x0 },
	5073	+ { 0x11043, 0x0 },
	5074	+ { 0x111043, 0x0 },
	5075	+ { 0x211043, 0x0 },
	5076	+ { 0x11143, 0x0 },
	5077	+ { 0x111143, 0x0 },
	5078	+ { 0x211143, 0x0 },
	5079	+ { 0x12043, 0x0 },
	5080	+ { 0x112043, 0x0 },
	5081	+ { 0x212043, 0x0 },
	5082	+ { 0x12143, 0x0 },
	5083	+ { 0x112143, 0x0 },
	5084	+ { 0x212143, 0x0 },
	5085	+ { 0x13043, 0x0 },
	5086	+ { 0x113043, 0x0 },
	5087	+ { 0x213043, 0x0 },
	5088	+ { 0x13143, 0x0 },
	5089	+ { 0x113143, 0x0 },
	5090	+ { 0x213143, 0x0 },
	5091	+ { 0x80, 0x0 },
	5092	+ { 0x100080, 0x0 },
	5093	+ { 0x200080, 0x0 },
	5094	+ { 0x1080, 0x0 },
	5095	+ { 0x101080, 0x0 },
	5096	+ { 0x201080, 0x0 },
	5097	+ { 0x2080, 0x0 },
	5098	+ { 0x102080, 0x0 },
	5099	+ { 0x202080, 0x0 },
	5100	+ { 0x3080, 0x0 },
	5101	+ { 0x103080, 0x0 },
	5102	+ { 0x203080, 0x0 },
	5103	+ { 0x4080, 0x0 },
	5104	+ { 0x104080, 0x0 },
	5105	+ { 0x204080, 0x0 },
	5106	+ { 0x5080, 0x0 },
	5107	+ { 0x105080, 0x0 },
	5108	+ { 0x205080, 0x0 },
	5109	+ { 0x6080, 0x0 },
	5110	+ { 0x106080, 0x0 },
	5111	+ { 0x206080, 0x0 },
	5112	+ { 0x7080, 0x0 },
	5113	+ { 0x107080, 0x0 },
	5114	+ { 0x207080, 0x0 },
	5115	+ { 0x8080, 0x0 },
	5116	+ { 0x108080, 0x0 },
	5117	+ { 0x208080, 0x0 },
	5118	+ { 0x9080, 0x0 },
	5119	+ { 0x109080, 0x0 },
	5120	+ { 0x209080, 0x0 },
	5121	+ { 0x10080, 0x0 },
	5122	+ { 0x110080, 0x0 },
	5123	+ { 0x210080, 0x0 },
	5124	+ { 0x10180, 0x0 },
	5125	+ { 0x110180, 0x0 },
	5126	+ { 0x210180, 0x0 },
	5127	+ { 0x11080, 0x0 },
	5128	+ { 0x111080, 0x0 },
	5129	+ { 0x211080, 0x0 },
	5130	+ { 0x11180, 0x0 },
	5131	+ { 0x111180, 0x0 },
	5132	+ { 0x211180, 0x0 },
	5133	+ { 0x12080, 0x0 },
	5134	+ { 0x112080, 0x0 },
	5135	+ { 0x212080, 0x0 },
	5136	+ { 0x12180, 0x0 },
	5137	+ { 0x112180, 0x0 },
	5138	+ { 0x212180, 0x0 },
	5139	+ { 0x13080, 0x0 },
	5140	+ { 0x113080, 0x0 },
	5141	+ { 0x213080, 0x0 },
	5142	+ { 0x13180, 0x0 },
	5143	+ { 0x113180, 0x0 },
	5144	+ { 0x213180, 0x0 },
	5145	+ { 0x10081, 0x0 },
	5146	+ { 0x110081, 0x0 },
	5147	+ { 0x210081, 0x0 },
	5148	+ { 0x10181, 0x0 },
	5149	+ { 0x110181, 0x0 },
	5150	+ { 0x210181, 0x0 },
	5151	+ { 0x11081, 0x0 },
	5152	+ { 0x111081, 0x0 },
	5153	+ { 0x211081, 0x0 },
	5154	+ { 0x11181, 0x0 },
	5155	+ { 0x111181, 0x0 },
	5156	+ { 0x211181, 0x0 },
	5157	+ { 0x12081, 0x0 },
	5158	+ { 0x112081, 0x0 },
	5159	+ { 0x212081, 0x0 },
	5160	+ { 0x12181, 0x0 },
	5161	+ { 0x112181, 0x0 },
	5162	+ { 0x212181, 0x0 },
	5163	+ { 0x13081, 0x0 },
	5164	+ { 0x113081, 0x0 },
	5165	+ { 0x213081, 0x0 },
	5166	+ { 0x13181, 0x0 },
	5167	+ { 0x113181, 0x0 },
	5168	+ { 0x213181, 0x0 },
	5169	+ { 0x100d0, 0x0 },
	5170	+ { 0x1100d0, 0x0 },
	5171	+ { 0x2100d0, 0x0 },
	5172	+ { 0x101d0, 0x0 },
	5173	+ { 0x1101d0, 0x0 },
	5174	+ { 0x2101d0, 0x0 },
	5175	+ { 0x110d0, 0x0 },
	5176	+ { 0x1110d0, 0x0 },
	5177	+ { 0x2110d0, 0x0 },
	5178	+ { 0x111d0, 0x0 },
	5179	+ { 0x1111d0, 0x0 },
	5180	+ { 0x2111d0, 0x0 },
	5181	+ { 0x120d0, 0x0 },
	5182	+ { 0x1120d0, 0x0 },
	5183	+ { 0x2120d0, 0x0 },
	5184	+ { 0x121d0, 0x0 },
	5185	+ { 0x1121d0, 0x0 },
	5186	+ { 0x2121d0, 0x0 },
	5187	+ { 0x130d0, 0x0 },
	5188	+ { 0x1130d0, 0x0 },
	5189	+ { 0x2130d0, 0x0 },
	5190	+ { 0x131d0, 0x0 },
	5191	+ { 0x1131d0, 0x0 },
	5192	+ { 0x2131d0, 0x0 },
	5193	+ { 0x100d1, 0x0 },
	5194	+ { 0x1100d1, 0x0 },
	5195	+ { 0x2100d1, 0x0 },
	5196	+ { 0x101d1, 0x0 },
	5197	+ { 0x1101d1, 0x0 },
	5198	+ { 0x2101d1, 0x0 },
	5199	+ { 0x110d1, 0x0 },
	5200	+ { 0x1110d1, 0x0 },
	5201	+ { 0x2110d1, 0x0 },
	5202	+ { 0x111d1, 0x0 },
	5203	+ { 0x1111d1, 0x0 },
	5204	+ { 0x2111d1, 0x0 },
	5205	+ { 0x120d1, 0x0 },
	5206	+ { 0x1120d1, 0x0 },
	5207	+ { 0x2120d1, 0x0 },
	5208	+ { 0x121d1, 0x0 },
	5209	+ { 0x1121d1, 0x0 },
	5210	+ { 0x2121d1, 0x0 },
	5211	+ { 0x130d1, 0x0 },
	5212	+ { 0x1130d1, 0x0 },
	5213	+ { 0x2130d1, 0x0 },
	5214	+ { 0x131d1, 0x0 },
	5215	+ { 0x1131d1, 0x0 },
	5216	+ { 0x2131d1, 0x0 },
	5217	+ { 0x10068, 0x0 },
	5218	+ { 0x10168, 0x0 },
	5219	+ { 0x10268, 0x0 },
	5220	+ { 0x10368, 0x0 },
	5221	+ { 0x10468, 0x0 },
	5222	+ { 0x10568, 0x0 },
	5223	+ { 0x10668, 0x0 },
	5224	+ { 0x10768, 0x0 },
	5225	+ { 0x10868, 0x0 },
	5226	+ { 0x11068, 0x0 },
	5227	+ { 0x11168, 0x0 },
	5228	+ { 0x11268, 0x0 },
	5229	+ { 0x11368, 0x0 },
	5230	+ { 0x11468, 0x0 },
	5231	+ { 0x11568, 0x0 },
	5232	+ { 0x11668, 0x0 },
	5233	+ { 0x11768, 0x0 },
	5234	+ { 0x11868, 0x0 },
	5235	+ { 0x12068, 0x0 },
	5236	+ { 0x12168, 0x0 },
	5237	+ { 0x12268, 0x0 },
	5238	+ { 0x12368, 0x0 },
	5239	+ { 0x12468, 0x0 },
	5240	+ { 0x12568, 0x0 },
	5241	+ { 0x12668, 0x0 },
	5242	+ { 0x12768, 0x0 },
	5243	+ { 0x12868, 0x0 },
	5244	+ { 0x13068, 0x0 },
	5245	+ { 0x13168, 0x0 },
	5246	+ { 0x13268, 0x0 },
	5247	+ { 0x13368, 0x0 },
	5248	+ { 0x13468, 0x0 },
	5249	+ { 0x13568, 0x0 },
	5250	+ { 0x13668, 0x0 },
	5251	+ { 0x13768, 0x0 },
	5252	+ { 0x13868, 0x0 },
	5253	+ { 0x10069, 0x0 },
	5254	+ { 0x10169, 0x0 },
	5255	+ { 0x10269, 0x0 },
	5256	+ { 0x10369, 0x0 },
	5257	+ { 0x10469, 0x0 },
	5258	+ { 0x10569, 0x0 },
	5259	+ { 0x10669, 0x0 },
	5260	+ { 0x10769, 0x0 },
	5261	+ { 0x10869, 0x0 },
	5262	+ { 0x11069, 0x0 },
	5263	+ { 0x11169, 0x0 },
	5264	+ { 0x11269, 0x0 },
	5265	+ { 0x11369, 0x0 },
	5266	+ { 0x11469, 0x0 },
	5267	+ { 0x11569, 0x0 },
	5268	+ { 0x11669, 0x0 },
	5269	+ { 0x11769, 0x0 },
	5270	+ { 0x11869, 0x0 },
	5271	+ { 0x12069, 0x0 },
	5272	+ { 0x12169, 0x0 },
	5273	+ { 0x12269, 0x0 },
	5274	+ { 0x12369, 0x0 },
	5275	+ { 0x12469, 0x0 },
	5276	+ { 0x12569, 0x0 },
	5277	+ { 0x12669, 0x0 },
	5278	+ { 0x12769, 0x0 },
	5279	+ { 0x12869, 0x0 },
	5280	+ { 0x13069, 0x0 },
	5281	+ { 0x13169, 0x0 },
	5282	+ { 0x13269, 0x0 },
	5283	+ { 0x13369, 0x0 },
	5284	+ { 0x13469, 0x0 },
	5285	+ { 0x13569, 0x0 },
	5286	+ { 0x13669, 0x0 },
	5287	+ { 0x13769, 0x0 },
	5288	+ { 0x13869, 0x0 },
	5289	+ { 0x1008c, 0x0 },
	5290	+ { 0x11008c, 0x0 },
	5291	+ { 0x21008c, 0x0 },
	5292	+ { 0x1018c, 0x0 },
	5293	+ { 0x11018c, 0x0 },
	5294	+ { 0x21018c, 0x0 },
	5295	+ { 0x1108c, 0x0 },
	5296	+ { 0x11108c, 0x0 },
	5297	+ { 0x21108c, 0x0 },
	5298	+ { 0x1118c, 0x0 },
	5299	+ { 0x11118c, 0x0 },
	5300	+ { 0x21118c, 0x0 },
	5301	+ { 0x1208c, 0x0 },
	5302	+ { 0x11208c, 0x0 },
	5303	+ { 0x21208c, 0x0 },
	5304	+ { 0x1218c, 0x0 },
	5305	+ { 0x11218c, 0x0 },
	5306	+ { 0x21218c, 0x0 },
	5307	+ { 0x1308c, 0x0 },
	5308	+ { 0x11308c, 0x0 },
	5309	+ { 0x21308c, 0x0 },
	5310	+ { 0x1318c, 0x0 },
	5311	+ { 0x11318c, 0x0 },
	5312	+ { 0x21318c, 0x0 },
	5313	+ { 0x1008d, 0x0 },
	5314	+ { 0x11008d, 0x0 },
	5315	+ { 0x21008d, 0x0 },
	5316	+ { 0x1018d, 0x0 },
	5317	+ { 0x11018d, 0x0 },
	5318	+ { 0x21018d, 0x0 },
	5319	+ { 0x1108d, 0x0 },
	5320	+ { 0x11108d, 0x0 },
	5321	+ { 0x21108d, 0x0 },
	5322	+ { 0x1118d, 0x0 },
	5323	+ { 0x11118d, 0x0 },
	5324	+ { 0x21118d, 0x0 },
	5325	+ { 0x1208d, 0x0 },
	5326	+ { 0x11208d, 0x0 },
	5327	+ { 0x21208d, 0x0 },
	5328	+ { 0x1218d, 0x0 },
	5329	+ { 0x11218d, 0x0 },
	5330	+ { 0x21218d, 0x0 },
	5331	+ { 0x1308d, 0x0 },
	5332	+ { 0x11308d, 0x0 },
	5333	+ { 0x21308d, 0x0 },
	5334	+ { 0x1318d, 0x0 },
	5335	+ { 0x11318d, 0x0 },
	5336	+ { 0x21318d, 0x0 },
	5337	+ { 0x100c0, 0x0 },
	5338	+ { 0x1100c0, 0x0 },
	5339	+ { 0x2100c0, 0x0 },
	5340	+ { 0x101c0, 0x0 },
	5341	+ { 0x1101c0, 0x0 },
	5342	+ { 0x2101c0, 0x0 },
	5343	+ { 0x102c0, 0x0 },
	5344	+ { 0x1102c0, 0x0 },
	5345	+ { 0x2102c0, 0x0 },
	5346	+ { 0x103c0, 0x0 },
	5347	+ { 0x1103c0, 0x0 },
	5348	+ { 0x2103c0, 0x0 },
	5349	+ { 0x104c0, 0x0 },
	5350	+ { 0x1104c0, 0x0 },
	5351	+ { 0x2104c0, 0x0 },
	5352	+ { 0x105c0, 0x0 },
	5353	+ { 0x1105c0, 0x0 },
	5354	+ { 0x2105c0, 0x0 },
	5355	+ { 0x106c0, 0x0 },
	5356	+ { 0x1106c0, 0x0 },
	5357	+ { 0x2106c0, 0x0 },
	5358	+ { 0x107c0, 0x0 },
	5359	+ { 0x1107c0, 0x0 },
	5360	+ { 0x2107c0, 0x0 },
	5361	+ { 0x108c0, 0x0 },
	5362	+ { 0x1108c0, 0x0 },
	5363	+ { 0x2108c0, 0x0 },
	5364	+ { 0x110c0, 0x0 },
	5365	+ { 0x1110c0, 0x0 },
	5366	+ { 0x2110c0, 0x0 },
	5367	+ { 0x111c0, 0x0 },
	5368	+ { 0x1111c0, 0x0 },
	5369	+ { 0x2111c0, 0x0 },
	5370	+ { 0x112c0, 0x0 },
	5371	+ { 0x1112c0, 0x0 },
	5372	+ { 0x2112c0, 0x0 },
	5373	+ { 0x113c0, 0x0 },
	5374	+ { 0x1113c0, 0x0 },
	5375	+ { 0x2113c0, 0x0 },
	5376	+ { 0x114c0, 0x0 },
	5377	+ { 0x1114c0, 0x0 },
	5378	+ { 0x2114c0, 0x0 },
	5379	+ { 0x115c0, 0x0 },
	5380	+ { 0x1115c0, 0x0 },
	5381	+ { 0x2115c0, 0x0 },
	5382	+ { 0x116c0, 0x0 },
	5383	+ { 0x1116c0, 0x0 },
	5384	+ { 0x2116c0, 0x0 },
	5385	+ { 0x117c0, 0x0 },
	5386	+ { 0x1117c0, 0x0 },
	5387	+ { 0x2117c0, 0x0 },
	5388	+ { 0x118c0, 0x0 },
	5389	+ { 0x1118c0, 0x0 },
	5390	+ { 0x2118c0, 0x0 },
	5391	+ { 0x120c0, 0x0 },
	5392	+ { 0x1120c0, 0x0 },
	5393	+ { 0x2120c0, 0x0 },
	5394	+ { 0x121c0, 0x0 },
	5395	+ { 0x1121c0, 0x0 },
	5396	+ { 0x2121c0, 0x0 },
	5397	+ { 0x122c0, 0x0 },
	5398	+ { 0x1122c0, 0x0 },
	5399	+ { 0x2122c0, 0x0 },
	5400	+ { 0x123c0, 0x0 },
	5401	+ { 0x1123c0, 0x0 },
	5402	+ { 0x2123c0, 0x0 },
	5403	+ { 0x124c0, 0x0 },
	5404	+ { 0x1124c0, 0x0 },
	5405	+ { 0x2124c0, 0x0 },
	5406	+ { 0x125c0, 0x0 },
	5407	+ { 0x1125c0, 0x0 },
	5408	+ { 0x2125c0, 0x0 },
	5409	+ { 0x126c0, 0x0 },
	5410	+ { 0x1126c0, 0x0 },
	5411	+ { 0x2126c0, 0x0 },
	5412	+ { 0x127c0, 0x0 },
	5413	+ { 0x1127c0, 0x0 },
	5414	+ { 0x2127c0, 0x0 },
	5415	+ { 0x128c0, 0x0 },
	5416	+ { 0x1128c0, 0x0 },
	5417	+ { 0x2128c0, 0x0 },
	5418	+ { 0x130c0, 0x0 },
	5419	+ { 0x1130c0, 0x0 },
	5420	+ { 0x2130c0, 0x0 },
	5421	+ { 0x131c0, 0x0 },
	5422	+ { 0x1131c0, 0x0 },
	5423	+ { 0x2131c0, 0x0 },
	5424	+ { 0x132c0, 0x0 },
	5425	+ { 0x1132c0, 0x0 },
	5426	+ { 0x2132c0, 0x0 },
	5427	+ { 0x133c0, 0x0 },
	5428	+ { 0x1133c0, 0x0 },
	5429	+ { 0x2133c0, 0x0 },
	5430	+ { 0x134c0, 0x0 },
	5431	+ { 0x1134c0, 0x0 },
	5432	+ { 0x2134c0, 0x0 },
	5433	+ { 0x135c0, 0x0 },
	5434	+ { 0x1135c0, 0x0 },
	5435	+ { 0x2135c0, 0x0 },
	5436	+ { 0x136c0, 0x0 },
	5437	+ { 0x1136c0, 0x0 },
	5438	+ { 0x2136c0, 0x0 },
	5439	+ { 0x137c0, 0x0 },
	5440	+ { 0x1137c0, 0x0 },
	5441	+ { 0x2137c0, 0x0 },
	5442	+ { 0x138c0, 0x0 },
	5443	+ { 0x1138c0, 0x0 },
	5444	+ { 0x2138c0, 0x0 },
	5445	+ { 0x100c1, 0x0 },
	5446	+ { 0x1100c1, 0x0 },
	5447	+ { 0x2100c1, 0x0 },
	5448	+ { 0x101c1, 0x0 },
	5449	+ { 0x1101c1, 0x0 },
	5450	+ { 0x2101c1, 0x0 },
	5451	+ { 0x102c1, 0x0 },
	5452	+ { 0x1102c1, 0x0 },
	5453	+ { 0x2102c1, 0x0 },
	5454	+ { 0x103c1, 0x0 },
	5455	+ { 0x1103c1, 0x0 },
	5456	+ { 0x2103c1, 0x0 },
	5457	+ { 0x104c1, 0x0 },
	5458	+ { 0x1104c1, 0x0 },
	5459	+ { 0x2104c1, 0x0 },
	5460	+ { 0x105c1, 0x0 },
	5461	+ { 0x1105c1, 0x0 },
	5462	+ { 0x2105c1, 0x0 },
	5463	+ { 0x106c1, 0x0 },
	5464	+ { 0x1106c1, 0x0 },
	5465	+ { 0x2106c1, 0x0 },
	5466	+ { 0x107c1, 0x0 },
	5467	+ { 0x1107c1, 0x0 },
	5468	+ { 0x2107c1, 0x0 },
	5469	+ { 0x108c1, 0x0 },
	5470	+ { 0x1108c1, 0x0 },
	5471	+ { 0x2108c1, 0x0 },
	5472	+ { 0x110c1, 0x0 },
	5473	+ { 0x1110c1, 0x0 },
	5474	+ { 0x2110c1, 0x0 },
	5475	+ { 0x111c1, 0x0 },
	5476	+ { 0x1111c1, 0x0 },
	5477	+ { 0x2111c1, 0x0 },
	5478	+ { 0x112c1, 0x0 },
	5479	+ { 0x1112c1, 0x0 },
	5480	+ { 0x2112c1, 0x0 },
	5481	+ { 0x113c1, 0x0 },
	5482	+ { 0x1113c1, 0x0 },
	5483	+ { 0x2113c1, 0x0 },
	5484	+ { 0x114c1, 0x0 },
	5485	+ { 0x1114c1, 0x0 },
	5486	+ { 0x2114c1, 0x0 },
	5487	+ { 0x115c1, 0x0 },
	5488	+ { 0x1115c1, 0x0 },
	5489	+ { 0x2115c1, 0x0 },
	5490	+ { 0x116c1, 0x0 },
	5491	+ { 0x1116c1, 0x0 },
	5492	+ { 0x2116c1, 0x0 },
	5493	+ { 0x117c1, 0x0 },
	5494	+ { 0x1117c1, 0x0 },
	5495	+ { 0x2117c1, 0x0 },
	5496	+ { 0x118c1, 0x0 },
	5497	+ { 0x1118c1, 0x0 },
	5498	+ { 0x2118c1, 0x0 },
	5499	+ { 0x120c1, 0x0 },
	5500	+ { 0x1120c1, 0x0 },
	5501	+ { 0x2120c1, 0x0 },
	5502	+ { 0x121c1, 0x0 },
	5503	+ { 0x1121c1, 0x0 },
	5504	+ { 0x2121c1, 0x0 },
	5505	+ { 0x122c1, 0x0 },
	5506	+ { 0x1122c1, 0x0 },
	5507	+ { 0x2122c1, 0x0 },
	5508	+ { 0x123c1, 0x0 },
	5509	+ { 0x1123c1, 0x0 },
	5510	+ { 0x2123c1, 0x0 },
	5511	+ { 0x124c1, 0x0 },
	5512	+ { 0x1124c1, 0x0 },
	5513	+ { 0x2124c1, 0x0 },
	5514	+ { 0x125c1, 0x0 },
	5515	+ { 0x1125c1, 0x0 },
	5516	+ { 0x2125c1, 0x0 },
	5517	+ { 0x126c1, 0x0 },
	5518	+ { 0x1126c1, 0x0 },
	5519	+ { 0x2126c1, 0x0 },
	5520	+ { 0x127c1, 0x0 },
	5521	+ { 0x1127c1, 0x0 },
	5522	+ { 0x2127c1, 0x0 },
	5523	+ { 0x128c1, 0x0 },
	5524	+ { 0x1128c1, 0x0 },
	5525	+ { 0x2128c1, 0x0 },
	5526	+ { 0x130c1, 0x0 },
	5527	+ { 0x1130c1, 0x0 },
	5528	+ { 0x2130c1, 0x0 },
	5529	+ { 0x131c1, 0x0 },
	5530	+ { 0x1131c1, 0x0 },
	5531	+ { 0x2131c1, 0x0 },
	5532	+ { 0x132c1, 0x0 },
	5533	+ { 0x1132c1, 0x0 },
	5534	+ { 0x2132c1, 0x0 },
	5535	+ { 0x133c1, 0x0 },
	5536	+ { 0x1133c1, 0x0 },
	5537	+ { 0x2133c1, 0x0 },
	5538	+ { 0x134c1, 0x0 },
	5539	+ { 0x1134c1, 0x0 },
	5540	+ { 0x2134c1, 0x0 },
	5541	+ { 0x135c1, 0x0 },
	5542	+ { 0x1135c1, 0x0 },
	5543	+ { 0x2135c1, 0x0 },
	5544	+ { 0x136c1, 0x0 },
	5545	+ { 0x1136c1, 0x0 },
	5546	+ { 0x2136c1, 0x0 },
	5547	+ { 0x137c1, 0x0 },
	5548	+ { 0x1137c1, 0x0 },
	5549	+ { 0x2137c1, 0x0 },
	5550	+ { 0x138c1, 0x0 },
	5551	+ { 0x1138c1, 0x0 },
	5552	+ { 0x2138c1, 0x0 },
	5553	+ { 0x10020, 0x0 },
	5554	+ { 0x110020, 0x0 },
	5555	+ { 0x210020, 0x0 },
	5556	+ { 0x11020, 0x0 },
	5557	+ { 0x111020, 0x0 },
	5558	+ { 0x211020, 0x0 },
	5559	+ { 0x12020, 0x0 },
	5560	+ { 0x112020, 0x0 },
	5561	+ { 0x212020, 0x0 },
	5562	+ { 0x13020, 0x0 },
	5563	+ { 0x113020, 0x0 },
	5564	+ { 0x213020, 0x0 },
	5565	+ { 0x20072, 0x0 },
	5566	+ { 0x20073, 0x0 },
	5567	+ { 0x20074, 0x0 },
	5568	+ { 0x100aa, 0x0 },
	5569	+ { 0x110aa, 0x0 },
	5570	+ { 0x120aa, 0x0 },
	5571	+ { 0x130aa, 0x0 },
	5572	+ { 0x20010, 0x0 },
	5573	+ { 0x120010, 0x0 },
	5574	+ { 0x220010, 0x0 },
	5575	+ { 0x20011, 0x0 },
	5576	+ { 0x120011, 0x0 },
	5577	+ { 0x220011, 0x0 },
	5578	+ { 0x100ae, 0x0 },
	5579	+ { 0x1100ae, 0x0 },
	5580	+ { 0x2100ae, 0x0 },
	5581	+ { 0x100af, 0x0 },
	5582	+ { 0x1100af, 0x0 },
	5583	+ { 0x2100af, 0x0 },
	5584	+ { 0x110ae, 0x0 },
	5585	+ { 0x1110ae, 0x0 },
	5586	+ { 0x2110ae, 0x0 },
	5587	+ { 0x110af, 0x0 },
	5588	+ { 0x1110af, 0x0 },
	5589	+ { 0x2110af, 0x0 },
	5590	+ { 0x120ae, 0x0 },
	5591	+ { 0x1120ae, 0x0 },
	5592	+ { 0x2120ae, 0x0 },
	5593	+ { 0x120af, 0x0 },
	5594	+ { 0x1120af, 0x0 },
	5595	+ { 0x2120af, 0x0 },
	5596	+ { 0x130ae, 0x0 },
	5597	+ { 0x1130ae, 0x0 },
	5598	+ { 0x2130ae, 0x0 },
	5599	+ { 0x130af, 0x0 },
	5600	+ { 0x1130af, 0x0 },
	5601	+ { 0x2130af, 0x0 },
	5602	+ { 0x20020, 0x0 },
	5603	+ { 0x120020, 0x0 },
	5604	+ { 0x220020, 0x0 },
	5605	+ { 0x100a0, 0x0 },
	5606	+ { 0x100a1, 0x0 },
	5607	+ { 0x100a2, 0x0 },
	5608	+ { 0x100a3, 0x0 },
	5609	+ { 0x100a4, 0x0 },
	5610	+ { 0x100a5, 0x0 },
	5611	+ { 0x100a6, 0x0 },
	5612	+ { 0x100a7, 0x0 },
	5613	+ { 0x110a0, 0x0 },
	5614	+ { 0x110a1, 0x0 },
	5615	+ { 0x110a2, 0x0 },
	5616	+ { 0x110a3, 0x0 },
	5617	+ { 0x110a4, 0x0 },
	5618	+ { 0x110a5, 0x0 },
	5619	+ { 0x110a6, 0x0 },
	5620	+ { 0x110a7, 0x0 },
	5621	+ { 0x120a0, 0x0 },
	5622	+ { 0x120a1, 0x0 },
	5623	+ { 0x120a2, 0x0 },
	5624	+ { 0x120a3, 0x0 },
	5625	+ { 0x120a4, 0x0 },
	5626	+ { 0x120a5, 0x0 },
	5627	+ { 0x120a6, 0x0 },
	5628	+ { 0x120a7, 0x0 },
	5629	+ { 0x130a0, 0x0 },
	5630	+ { 0x130a1, 0x0 },
	5631	+ { 0x130a2, 0x0 },
	5632	+ { 0x130a3, 0x0 },
	5633	+ { 0x130a4, 0x0 },
	5634	+ { 0x130a5, 0x0 },
	5635	+ { 0x130a6, 0x0 },
	5636	+ { 0x130a7, 0x0 },
	5637	+ { 0x2007c, 0x0 },
	5638	+ { 0x12007c, 0x0 },
	5639	+ { 0x22007c, 0x0 },
	5640	+ { 0x2007d, 0x0 },
	5641	+ { 0x12007d, 0x0 },
	5642	+ { 0x22007d, 0x0 },
	5643	+ { 0x400fd, 0x0 },
	5644	+ { 0x400c0, 0x0 },
	5645	+ { 0x90201, 0x0 },
	5646	+ { 0x190201, 0x0 },
	5647	+ { 0x290201, 0x0 },
	5648	+ { 0x90202, 0x0 },
	5649	+ { 0x190202, 0x0 },
	5650	+ { 0x290202, 0x0 },
	5651	+ { 0x90203, 0x0 },
	5652	+ { 0x190203, 0x0 },
	5653	+ { 0x290203, 0x0 },
	5654	+ { 0x90204, 0x0 },
	5655	+ { 0x190204, 0x0 },
	5656	+ { 0x290204, 0x0 },
	5657	+ { 0x90205, 0x0 },
	5658	+ { 0x190205, 0x0 },
	5659	+ { 0x290205, 0x0 },
	5660	+ { 0x90206, 0x0 },
	5661	+ { 0x190206, 0x0 },
	5662	+ { 0x290206, 0x0 },
	5663	+ { 0x90207, 0x0 },
	5664	+ { 0x190207, 0x0 },
	5665	+ { 0x290207, 0x0 },
	5666	+ { 0x90208, 0x0 },
	5667	+ { 0x190208, 0x0 },
	5668	+ { 0x290208, 0x0 },
	5669	+ { 0x10062, 0x0 },
	5670	+ { 0x10162, 0x0 },
	5671	+ { 0x10262, 0x0 },
	5672	+ { 0x10362, 0x0 },
	5673	+ { 0x10462, 0x0 },
	5674	+ { 0x10562, 0x0 },
	5675	+ { 0x10662, 0x0 },
	5676	+ { 0x10762, 0x0 },
	5677	+ { 0x10862, 0x0 },
	5678	+ { 0x11062, 0x0 },
	5679	+ { 0x11162, 0x0 },
	5680	+ { 0x11262, 0x0 },
	5681	+ { 0x11362, 0x0 },
	5682	+ { 0x11462, 0x0 },
	5683	+ { 0x11562, 0x0 },
	5684	+ { 0x11662, 0x0 },
	5685	+ { 0x11762, 0x0 },
	5686	+ { 0x11862, 0x0 },
	5687	+ { 0x12062, 0x0 },
	5688	+ { 0x12162, 0x0 },
	5689	+ { 0x12262, 0x0 },
	5690	+ { 0x12362, 0x0 },
	5691	+ { 0x12462, 0x0 },
	5692	+ { 0x12562, 0x0 },
	5693	+ { 0x12662, 0x0 },
	5694	+ { 0x12762, 0x0 },
	5695	+ { 0x12862, 0x0 },
	5696	+ { 0x13062, 0x0 },
	5697	+ { 0x13162, 0x0 },
	5698	+ { 0x13262, 0x0 },
	5699	+ { 0x13362, 0x0 },
	5700	+ { 0x13462, 0x0 },
	5701	+ { 0x13562, 0x0 },
	5702	+ { 0x13662, 0x0 },
	5703	+ { 0x13762, 0x0 },
	5704	+ { 0x13862, 0x0 },
	5705	+ { 0x20077, 0x0 },
	5706	+ { 0x10001, 0x0 },
	5707	+ { 0x11001, 0x0 },
	5708	+ { 0x12001, 0x0 },
	5709	+ { 0x13001, 0x0 },
	5710	+ { 0x10040, 0x0 },
	5711	+ { 0x10140, 0x0 },
	5712	+ { 0x10240, 0x0 },
	5713	+ { 0x10340, 0x0 },
	5714	+ { 0x10440, 0x0 },
	5715	+ { 0x10540, 0x0 },
	5716	+ { 0x10640, 0x0 },
	5717	+ { 0x10740, 0x0 },
	5718	+ { 0x10840, 0x0 },
	5719	+ { 0x10030, 0x0 },
	5720	+ { 0x10130, 0x0 },
	5721	+ { 0x10230, 0x0 },
	5722	+ { 0x10330, 0x0 },
	5723	+ { 0x10430, 0x0 },
	5724	+ { 0x10530, 0x0 },
	5725	+ { 0x10630, 0x0 },
	5726	+ { 0x10730, 0x0 },
	5727	+ { 0x10830, 0x0 },
	5728	+ { 0x11040, 0x0 },
	5729	+ { 0x11140, 0x0 },
	5730	+ { 0x11240, 0x0 },
	5731	+ { 0x11340, 0x0 },
	5732	+ { 0x11440, 0x0 },
	5733	+ { 0x11540, 0x0 },
	5734	+ { 0x11640, 0x0 },
	5735	+ { 0x11740, 0x0 },
	5736	+ { 0x11840, 0x0 },
	5737	+ { 0x11030, 0x0 },
	5738	+ { 0x11130, 0x0 },
	5739	+ { 0x11230, 0x0 },
	5740	+ { 0x11330, 0x0 },
	5741	+ { 0x11430, 0x0 },
	5742	+ { 0x11530, 0x0 },
	5743	+ { 0x11630, 0x0 },
	5744	+ { 0x11730, 0x0 },
	5745	+ { 0x11830, 0x0 },
	5746	+ { 0x12040, 0x0 },
	5747	+ { 0x12140, 0x0 },
	5748	+ { 0x12240, 0x0 },
	5749	+ { 0x12340, 0x0 },
	5750	+ { 0x12440, 0x0 },
	5751	+ { 0x12540, 0x0 },
	5752	+ { 0x12640, 0x0 },
	5753	+ { 0x12740, 0x0 },
	5754	+ { 0x12840, 0x0 },
	5755	+ { 0x12030, 0x0 },
	5756	+ { 0x12130, 0x0 },
	5757	+ { 0x12230, 0x0 },
	5758	+ { 0x12330, 0x0 },
	5759	+ { 0x12430, 0x0 },
	5760	+ { 0x12530, 0x0 },
	5761	+ { 0x12630, 0x0 },
	5762	+ { 0x12730, 0x0 },
	5763	+ { 0x12830, 0x0 },
	5764	+ { 0x13040, 0x0 },
	5765	+ { 0x13140, 0x0 },
	5766	+ { 0x13240, 0x0 },
	5767	+ { 0x13340, 0x0 },
	5768	+ { 0x13440, 0x0 },
	5769	+ { 0x13540, 0x0 },
	5770	+ { 0x13640, 0x0 },
	5771	+ { 0x13740, 0x0 },
	5772	+ { 0x13840, 0x0 },
	5773	+ { 0x13030, 0x0 },
	5774	+ { 0x13130, 0x0 },
	5775	+ { 0x13230, 0x0 },
	5776	+ { 0x13330, 0x0 },
	5777	+ { 0x13430, 0x0 },
	5778	+ { 0x13530, 0x0 },
	5779	+ { 0x13630, 0x0 },
	5780	+ { 0x13730, 0x0 },
	5781	+ { 0x13830, 0x0 },
	5782	+};
	5783	+/* P0 message block paremeter for training firmware */
	5784	+struct dram_cfg_param ddr_fsp0_cfg[] = {
	5785	+ { 0xd0000, 0x0 },
	5786	+ { 0x54003, 0xc80 },
	5787	+ { 0x54004, 0x2 },
	5788	+ { 0x54005, 0x2228 },
	5789	+ { 0x54006, 0x14 },
	5790	+ { 0x54008, 0x131f },
	5791	+ { 0x54009, 0xc8 },
	5792	+ { 0x5400b, 0x2 },
	5793	+ { 0x5400f, 0x100 },
	5794	+ { 0x54012, 0x310 },
	5795	+ { 0x54019, 0x2dd4 },
	5796	+ { 0x5401a, 0x33 },
	5797	+ { 0x5401b, 0x4866 },
	5798	+ { 0x5401c, 0x4800 },
	5799	+ { 0x5401e, 0x16 },
	5800	+ { 0x5401f, 0x2dd4 },
	5801	+ { 0x54020, 0x33 },
	5802	+ { 0x54021, 0x4866 },
	5803	+ { 0x54022, 0x4800 },
	5804	+ { 0x54024, 0x16 },
	5805	+ { 0x5402b, 0x1000 },
	5806	+ { 0x5402c, 0x3 },
	5807	+ { 0x54032, 0xd400 },
	5808	+ { 0x54033, 0x332d },
	5809	+ { 0x54034, 0x6600 },
	5810	+ { 0x54035, 0x48 },
	5811	+ { 0x54036, 0x48 },
	5812	+ { 0x54037, 0x1600 },
	5813	+ { 0x54038, 0xd400 },
	5814	+ { 0x54039, 0x332d },
	5815	+ { 0x5403a, 0x6600 },
	5816	+ { 0x5403b, 0x48 },
	5817	+ { 0x5403c, 0x48 },
	5818	+ { 0x5403d, 0x1600 },
	5819	+ { 0xd0000, 0x1 },
	5820	+};
	5821	+
	5822	+
	5823	+/* P1 message block paremeter for training firmware */
	5824	+struct dram_cfg_param ddr_fsp1_cfg[] = {
	5825	+ { 0xd0000, 0x0 },
	5826	+ { 0x54002, 0x101 },
	5827	+ { 0x54003, 0x190 },
	5828	+ { 0x54004, 0x2 },
	5829	+ { 0x54005, 0x2228 },
	5830	+ { 0x54006, 0x14 },
	5831	+ { 0x54008, 0x121f },
	5832	+ { 0x54009, 0xc8 },
	5833	+ { 0x5400b, 0x2 },
	5834	+ { 0x5400f, 0x100 },
	5835	+ { 0x54012, 0x310 },
	5836	+ { 0x54019, 0x84 },
	5837	+ { 0x5401a, 0x33 },
	5838	+ { 0x5401b, 0x4866 },
	5839	+ { 0x5401c, 0x4800 },
	5840	+ { 0x5401e, 0x16 },
	5841	+ { 0x5401f, 0x84 },
	5842	+ { 0x54020, 0x33 },
	5843	+ { 0x54021, 0x4866 },
	5844	+ { 0x54022, 0x4800 },
	5845	+ { 0x54024, 0x16 },
	5846	+ { 0x5402b, 0x1000 },
	5847	+ { 0x5402c, 0x3 },
	5848	+ { 0x54032, 0x8400 },
	5849	+ { 0x54033, 0x3300 },
	5850	+ { 0x54034, 0x6600 },
	5851	+ { 0x54035, 0x48 },
	5852	+ { 0x54036, 0x48 },
	5853	+ { 0x54037, 0x1600 },
	5854	+ { 0x54038, 0x8400 },
	5855	+ { 0x54039, 0x3300 },
	5856	+ { 0x5403a, 0x6600 },
	5857	+ { 0x5403b, 0x48 },
	5858	+ { 0x5403c, 0x48 },
	5859	+ { 0x5403d, 0x1600 },
	5860	+ { 0xd0000, 0x1 },
	5861	+};
	5862	+
	5863	+
	5864	+/* P2 message block paremeter for training firmware */
	5865	+struct dram_cfg_param ddr_fsp2_cfg[] = {
	5866	+ { 0xd0000, 0x0 },
	5867	+ { 0x54002, 0x102 },
	5868	+ { 0x54003, 0x64 },
	5869	+ { 0x54004, 0x2 },
	5870	+ { 0x54005, 0x2228 },
	5871	+ { 0x54006, 0x14 },
	5872	+ { 0x54008, 0x121f },
	5873	+ { 0x54009, 0xc8 },
	5874	+ { 0x5400b, 0x2 },
	5875	+ { 0x5400f, 0x100 },
	5876	+ { 0x54012, 0x310 },
	5877	+ { 0x54019, 0x84 },
	5878	+ { 0x5401a, 0x33 },
	5879	+ { 0x5401b, 0x4866 },
	5880	+ { 0x5401c, 0x4800 },
	5881	+ { 0x5401e, 0x16 },
	5882	+ { 0x5401f, 0x84 },
	5883	+ { 0x54020, 0x33 },
	5884	+ { 0x54021, 0x4866 },
	5885	+ { 0x54022, 0x4800 },
	5886	+ { 0x54024, 0x16 },
	5887	+ { 0x5402b, 0x1000 },
	5888	+ { 0x5402c, 0x3 },
	5889	+ { 0x54032, 0x8400 },
	5890	+ { 0x54033, 0x3300 },
	5891	+ { 0x54034, 0x6600 },
	5892	+ { 0x54035, 0x48 },
	5893	+ { 0x54036, 0x48 },
	5894	+ { 0x54037, 0x1600 },
	5895	+ { 0x54038, 0x8400 },
	5896	+ { 0x54039, 0x3300 },
	5897	+ { 0x5403a, 0x6600 },
	5898	+ { 0x5403b, 0x48 },
	5899	+ { 0x5403c, 0x48 },
	5900	+ { 0x5403d, 0x1600 },
	5901	+ { 0xd0000, 0x1 },
	5902	+};
	5903	+
	5904	+
	5905	+/* P0 2D message block paremeter for training firmware */
	5906	+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
	5907	+ { 0xd0000, 0x0 },
	5908	+ { 0x54003, 0xc80 },
	5909	+ { 0x54004, 0x2 },
	5910	+ { 0x54005, 0x2228 },
	5911	+ { 0x54006, 0x14 },
	5912	+ { 0x54008, 0x61 },
	5913	+ { 0x54009, 0xc8 },
	5914	+ { 0x5400b, 0x2 },
	5915	+ { 0x5400d, 0x100 },
	5916	+ { 0x5400f, 0x100 },
	5917	+ { 0x54010, 0x1f7f },
	5918	+ { 0x54012, 0x310 },
	5919	+ { 0x54019, 0x2dd4 },
	5920	+ { 0x5401a, 0x33 },
	5921	+ { 0x5401b, 0x4866 },
	5922	+ { 0x5401c, 0x4800 },
	5923	+ { 0x5401e, 0x16 },
	5924	+ { 0x5401f, 0x2dd4 },
	5925	+ { 0x54020, 0x33 },
	5926	+ { 0x54021, 0x4866 },
	5927	+ { 0x54022, 0x4800 },
	5928	+ { 0x54024, 0x16 },
	5929	+ { 0x5402b, 0x1000 },
	5930	+ { 0x5402c, 0x3 },
	5931	+ { 0x54032, 0xd400 },
	5932	+ { 0x54033, 0x332d },
	5933	+ { 0x54034, 0x6600 },
	5934	+ { 0x54035, 0x48 },
	5935	+ { 0x54036, 0x48 },
	5936	+ { 0x54037, 0x1600 },
	5937	+ { 0x54038, 0xd400 },
	5938	+ { 0x54039, 0x332d },
	5939	+ { 0x5403a, 0x6600 },
	5940	+ { 0x5403b, 0x48 },
	5941	+ { 0x5403c, 0x48 },
	5942	+ { 0x5403d, 0x1600 },
	5943	+ { 0xd0000, 0x1 },
	5944	+};
	5945	+
	5946	+/* DRAM PHY init engine image */
	5947	+struct dram_cfg_param ddr_phy_pie[] = {
	5948	+ { 0xd0000, 0x0 },
	5949	+ { 0x90000, 0x10 },
	5950	+ { 0x90001, 0x400 },
	5951	+ { 0x90002, 0x10e },
	5952	+ { 0x90003, 0x0 },
	5953	+ { 0x90004, 0x0 },
	5954	+ { 0x90005, 0x8 },
	5955	+ { 0x90029, 0xb },
	5956	+ { 0x9002a, 0x480 },
	5957	+ { 0x9002b, 0x109 },
	5958	+ { 0x9002c, 0x8 },
	5959	+ { 0x9002d, 0x448 },
	5960	+ { 0x9002e, 0x139 },
	5961	+ { 0x9002f, 0x8 },
	5962	+ { 0x90030, 0x478 },
	5963	+ { 0x90031, 0x109 },
	5964	+ { 0x90032, 0x0 },
	5965	+ { 0x90033, 0xe8 },
	5966	+ { 0x90034, 0x109 },
	5967	+ { 0x90035, 0x2 },
	5968	+ { 0x90036, 0x10 },
	5969	+ { 0x90037, 0x139 },
	5970	+ { 0x90038, 0xb },
	5971	+ { 0x90039, 0x7c0 },
	5972	+ { 0x9003a, 0x139 },
	5973	+ { 0x9003b, 0x44 },
	5974	+ { 0x9003c, 0x633 },
	5975	+ { 0x9003d, 0x159 },
	5976	+ { 0x9003e, 0x14f },
	5977	+ { 0x9003f, 0x630 },
	5978	+ { 0x90040, 0x159 },
	5979	+ { 0x90041, 0x47 },
	5980	+ { 0x90042, 0x633 },
	5981	+ { 0x90043, 0x149 },
	5982	+ { 0x90044, 0x4f },
	5983	+ { 0x90045, 0x633 },
	5984	+ { 0x90046, 0x179 },
	5985	+ { 0x90047, 0x8 },
	5986	+ { 0x90048, 0xe0 },
	5987	+ { 0x90049, 0x109 },
	5988	+ { 0x9004a, 0x0 },
	5989	+ { 0x9004b, 0x7c8 },
	5990	+ { 0x9004c, 0x109 },
	5991	+ { 0x9004d, 0x0 },
	5992	+ { 0x9004e, 0x1 },
	5993	+ { 0x9004f, 0x8 },
	5994	+ { 0x90050, 0x0 },
	5995	+ { 0x90051, 0x45a },
	5996	+ { 0x90052, 0x9 },
	5997	+ { 0x90053, 0x0 },
	5998	+ { 0x90054, 0x448 },
	5999	+ { 0x90055, 0x109 },
	6000	+ { 0x90056, 0x40 },
	6001	+ { 0x90057, 0x633 },
	6002	+ { 0x90058, 0x179 },
	6003	+ { 0x90059, 0x1 },
	6004	+ { 0x9005a, 0x618 },
	6005	+ { 0x9005b, 0x109 },
	6006	+ { 0x9005c, 0x40c0 },
	6007	+ { 0x9005d, 0x633 },
	6008	+ { 0x9005e, 0x149 },
	6009	+ { 0x9005f, 0x8 },
	6010	+ { 0x90060, 0x4 },
	6011	+ { 0x90061, 0x48 },
	6012	+ { 0x90062, 0x4040 },
	6013	+ { 0x90063, 0x633 },
	6014	+ { 0x90064, 0x149 },
	6015	+ { 0x90065, 0x0 },
	6016	+ { 0x90066, 0x4 },
	6017	+ { 0x90067, 0x48 },
	6018	+ { 0x90068, 0x40 },
	6019	+ { 0x90069, 0x633 },
	6020	+ { 0x9006a, 0x149 },
	6021	+ { 0x9006b, 0x10 },
	6022	+ { 0x9006c, 0x4 },
	6023	+ { 0x9006d, 0x18 },
	6024	+ { 0x9006e, 0x0 },
	6025	+ { 0x9006f, 0x4 },
	6026	+ { 0x90070, 0x78 },
	6027	+ { 0x90071, 0x549 },
	6028	+ { 0x90072, 0x633 },
	6029	+ { 0x90073, 0x159 },
	6030	+ { 0x90074, 0xd49 },
	6031	+ { 0x90075, 0x633 },
	6032	+ { 0x90076, 0x159 },
	6033	+ { 0x90077, 0x94a },
	6034	+ { 0x90078, 0x633 },
	6035	+ { 0x90079, 0x159 },
	6036	+ { 0x9007a, 0x441 },
	6037	+ { 0x9007b, 0x633 },
	6038	+ { 0x9007c, 0x149 },
	6039	+ { 0x9007d, 0x42 },
	6040	+ { 0x9007e, 0x633 },
	6041	+ { 0x9007f, 0x149 },
	6042	+ { 0x90080, 0x1 },
	6043	+ { 0x90081, 0x633 },
	6044	+ { 0x90082, 0x149 },
	6045	+ { 0x90083, 0x0 },
	6046	+ { 0x90084, 0xe0 },
	6047	+ { 0x90085, 0x109 },
	6048	+ { 0x90086, 0xa },
	6049	+ { 0x90087, 0x10 },
	6050	+ { 0x90088, 0x109 },
	6051	+ { 0x90089, 0x9 },
	6052	+ { 0x9008a, 0x3c0 },
	6053	+ { 0x9008b, 0x149 },
	6054	+ { 0x9008c, 0x9 },
	6055	+ { 0x9008d, 0x3c0 },
	6056	+ { 0x9008e, 0x159 },
	6057	+ { 0x9008f, 0x18 },
	6058	+ { 0x90090, 0x10 },
	6059	+ { 0x90091, 0x109 },
	6060	+ { 0x90092, 0x0 },
	6061	+ { 0x90093, 0x3c0 },
	6062	+ { 0x90094, 0x109 },
	6063	+ { 0x90095, 0x18 },
	6064	+ { 0x90096, 0x4 },
	6065	+ { 0x90097, 0x48 },
	6066	+ { 0x90098, 0x18 },
	6067	+ { 0x90099, 0x4 },
	6068	+ { 0x9009a, 0x58 },
	6069	+ { 0x9009b, 0xb },
	6070	+ { 0x9009c, 0x10 },
	6071	+ { 0x9009d, 0x109 },
	6072	+ { 0x9009e, 0x1 },
	6073	+ { 0x9009f, 0x10 },
	6074	+ { 0x900a0, 0x109 },
	6075	+ { 0x900a1, 0x5 },
	6076	+ { 0x900a2, 0x7c0 },
	6077	+ { 0x900a3, 0x109 },
	6078	+ { 0x40000, 0x811 },
	6079	+ { 0x40020, 0x880 },
	6080	+ { 0x40040, 0x0 },
	6081	+ { 0x40060, 0x0 },
	6082	+ { 0x40001, 0x4008 },
	6083	+ { 0x40021, 0x83 },
	6084	+ { 0x40041, 0x4f },
	6085	+ { 0x40061, 0x0 },
	6086	+ { 0x40002, 0x4040 },
	6087	+ { 0x40022, 0x83 },
	6088	+ { 0x40042, 0x51 },
	6089	+ { 0x40062, 0x0 },
	6090	+ { 0x40003, 0x811 },
	6091	+ { 0x40023, 0x880 },
	6092	+ { 0x40043, 0x0 },
	6093	+ { 0x40063, 0x0 },
	6094	+ { 0x40004, 0x720 },
	6095	+ { 0x40024, 0xf },
	6096	+ { 0x40044, 0x1740 },
	6097	+ { 0x40064, 0x0 },
	6098	+ { 0x40005, 0x16 },
	6099	+ { 0x40025, 0x83 },
	6100	+ { 0x40045, 0x4b },
	6101	+ { 0x40065, 0x0 },
	6102	+ { 0x40006, 0x716 },
	6103	+ { 0x40026, 0xf },
	6104	+ { 0x40046, 0x2001 },
	6105	+ { 0x40066, 0x0 },
	6106	+ { 0x40007, 0x716 },
	6107	+ { 0x40027, 0xf },
	6108	+ { 0x40047, 0x2800 },
	6109	+ { 0x40067, 0x0 },
	6110	+ { 0x40008, 0x716 },
	6111	+ { 0x40028, 0xf },
	6112	+ { 0x40048, 0xf00 },
	6113	+ { 0x40068, 0x0 },
	6114	+ { 0x40009, 0x720 },
	6115	+ { 0x40029, 0xf },
	6116	+ { 0x40049, 0x1400 },
	6117	+ { 0x40069, 0x0 },
	6118	+ { 0x4000a, 0xe08 },
	6119	+ { 0x4002a, 0xc15 },
	6120	+ { 0x4004a, 0x0 },
	6121	+ { 0x4006a, 0x0 },
	6122	+ { 0x4000b, 0x625 },
	6123	+ { 0x4002b, 0x15 },
	6124	+ { 0x4004b, 0x0 },
	6125	+ { 0x4006b, 0x0 },
	6126	+ { 0x4000c, 0x4028 },
	6127	+ { 0x4002c, 0x80 },
	6128	+ { 0x4004c, 0x0 },
	6129	+ { 0x4006c, 0x0 },
	6130	+ { 0x4000d, 0xe08 },
	6131	+ { 0x4002d, 0xc1a },
	6132	+ { 0x4004d, 0x0 },
	6133	+ { 0x4006d, 0x0 },
	6134	+ { 0x4000e, 0x625 },
	6135	+ { 0x4002e, 0x1a },
	6136	+ { 0x4004e, 0x0 },
	6137	+ { 0x4006e, 0x0 },
	6138	+ { 0x4000f, 0x4040 },
	6139	+ { 0x4002f, 0x80 },
	6140	+ { 0x4004f, 0x0 },
	6141	+ { 0x4006f, 0x0 },
	6142	+ { 0x40010, 0x2604 },
	6143	+ { 0x40030, 0x15 },
	6144	+ { 0x40050, 0x0 },
	6145	+ { 0x40070, 0x0 },
	6146	+ { 0x40011, 0x708 },
	6147	+ { 0x40031, 0x5 },
	6148	+ { 0x40051, 0x0 },
	6149	+ { 0x40071, 0x2002 },
	6150	+ { 0x40012, 0x8 },
	6151	+ { 0x40032, 0x80 },
	6152	+ { 0x40052, 0x0 },
	6153	+ { 0x40072, 0x0 },
	6154	+ { 0x40013, 0x2604 },
	6155	+ { 0x40033, 0x1a },
	6156	+ { 0x40053, 0x0 },
	6157	+ { 0x40073, 0x0 },
	6158	+ { 0x40014, 0x708 },
	6159	+ { 0x40034, 0xa },
	6160	+ { 0x40054, 0x0 },
	6161	+ { 0x40074, 0x2002 },
	6162	+ { 0x40015, 0x4040 },
	6163	+ { 0x40035, 0x80 },
	6164	+ { 0x40055, 0x0 },
	6165	+ { 0x40075, 0x0 },
	6166	+ { 0x40016, 0x60a },
	6167	+ { 0x40036, 0x15 },
	6168	+ { 0x40056, 0x1200 },
	6169	+ { 0x40076, 0x0 },
	6170	+ { 0x40017, 0x61a },
	6171	+ { 0x40037, 0x15 },
	6172	+ { 0x40057, 0x1300 },
	6173	+ { 0x40077, 0x0 },
	6174	+ { 0x40018, 0x60a },
	6175	+ { 0x40038, 0x1a },
	6176	+ { 0x40058, 0x1200 },
	6177	+ { 0x40078, 0x0 },
	6178	+ { 0x40019, 0x642 },
	6179	+ { 0x40039, 0x1a },
	6180	+ { 0x40059, 0x1300 },
	6181	+ { 0x40079, 0x0 },
	6182	+ { 0x4001a, 0x4808 },
	6183	+ { 0x4003a, 0x880 },
	6184	+ { 0x4005a, 0x0 },
	6185	+ { 0x4007a, 0x0 },
	6186	+ { 0x900a4, 0x0 },
	6187	+ { 0x900a5, 0x790 },
	6188	+ { 0x900a6, 0x11a },
	6189	+ { 0x900a7, 0x8 },
	6190	+ { 0x900a8, 0x7aa },
	6191	+ { 0x900a9, 0x2a },
	6192	+ { 0x900aa, 0x10 },
	6193	+ { 0x900ab, 0x7b2 },
	6194	+ { 0x900ac, 0x2a },
	6195	+ { 0x900ad, 0x0 },
	6196	+ { 0x900ae, 0x7c8 },
	6197	+ { 0x900af, 0x109 },
	6198	+ { 0x900b0, 0x10 },
	6199	+ { 0x900b1, 0x10 },
	6200	+ { 0x900b2, 0x109 },
	6201	+ { 0x900b3, 0x10 },
	6202	+ { 0x900b4, 0x2a8 },
	6203	+ { 0x900b5, 0x129 },
	6204	+ { 0x900b6, 0x8 },
	6205	+ { 0x900b7, 0x370 },
	6206	+ { 0x900b8, 0x129 },
	6207	+ { 0x900b9, 0xa },
	6208	+ { 0x900ba, 0x3c8 },
	6209	+ { 0x900bb, 0x1a9 },
	6210	+ { 0x900bc, 0xc },
	6211	+ { 0x900bd, 0x408 },
	6212	+ { 0x900be, 0x199 },
	6213	+ { 0x900bf, 0x14 },
	6214	+ { 0x900c0, 0x790 },
	6215	+ { 0x900c1, 0x11a },
	6216	+ { 0x900c2, 0x8 },
	6217	+ { 0x900c3, 0x4 },
	6218	+ { 0x900c4, 0x18 },
	6219	+ { 0x900c5, 0xe },
	6220	+ { 0x900c6, 0x408 },
	6221	+ { 0x900c7, 0x199 },
	6222	+ { 0x900c8, 0x8 },
	6223	+ { 0x900c9, 0x8568 },
	6224	+ { 0x900ca, 0x108 },
	6225	+ { 0x900cb, 0x18 },
	6226	+ { 0x900cc, 0x790 },
	6227	+ { 0x900cd, 0x16a },
	6228	+ { 0x900ce, 0x8 },
	6229	+ { 0x900cf, 0x1d8 },
	6230	+ { 0x900d0, 0x169 },
	6231	+ { 0x900d1, 0x10 },
	6232	+ { 0x900d2, 0x8558 },
	6233	+ { 0x900d3, 0x168 },
	6234	+ { 0x900d4, 0x70 },
	6235	+ { 0x900d5, 0x788 },
	6236	+ { 0x900d6, 0x16a },
	6237	+ { 0x900d7, 0x1ff8 },
	6238	+ { 0x900d8, 0x85a8 },
	6239	+ { 0x900d9, 0x1e8 },
	6240	+ { 0x900da, 0x50 },
	6241	+ { 0x900db, 0x798 },
	6242	+ { 0x900dc, 0x16a },
	6243	+ { 0x900dd, 0x60 },
	6244	+ { 0x900de, 0x7a0 },
	6245	+ { 0x900df, 0x16a },
	6246	+ { 0x900e0, 0x8 },
	6247	+ { 0x900e1, 0x8310 },
	6248	+ { 0x900e2, 0x168 },
	6249	+ { 0x900e3, 0x8 },
	6250	+ { 0x900e4, 0xa310 },
	6251	+ { 0x900e5, 0x168 },
	6252	+ { 0x900e6, 0xa },
	6253	+ { 0x900e7, 0x408 },
	6254	+ { 0x900e8, 0x169 },
	6255	+ { 0x900e9, 0x6e },
	6256	+ { 0x900ea, 0x0 },
	6257	+ { 0x900eb, 0x68 },
	6258	+ { 0x900ec, 0x0 },
	6259	+ { 0x900ed, 0x408 },
	6260	+ { 0x900ee, 0x169 },
	6261	+ { 0x900ef, 0x0 },
	6262	+ { 0x900f0, 0x8310 },
	6263	+ { 0x900f1, 0x168 },
	6264	+ { 0x900f2, 0x0 },
	6265	+ { 0x900f3, 0xa310 },
	6266	+ { 0x900f4, 0x168 },
	6267	+ { 0x900f5, 0x1ff8 },
	6268	+ { 0x900f6, 0x85a8 },
	6269	+ { 0x900f7, 0x1e8 },
	6270	+ { 0x900f8, 0x68 },
	6271	+ { 0x900f9, 0x798 },
	6272	+ { 0x900fa, 0x16a },
	6273	+ { 0x900fb, 0x78 },
	6274	+ { 0x900fc, 0x7a0 },
	6275	+ { 0x900fd, 0x16a },
	6276	+ { 0x900fe, 0x68 },
	6277	+ { 0x900ff, 0x790 },
	6278	+ { 0x90100, 0x16a },
	6279	+ { 0x90101, 0x8 },
	6280	+ { 0x90102, 0x8b10 },
	6281	+ { 0x90103, 0x168 },
	6282	+ { 0x90104, 0x8 },
	6283	+ { 0x90105, 0xab10 },
	6284	+ { 0x90106, 0x168 },
	6285	+ { 0x90107, 0xa },
	6286	+ { 0x90108, 0x408 },
	6287	+ { 0x90109, 0x169 },
	6288	+ { 0x9010a, 0x58 },
	6289	+ { 0x9010b, 0x0 },
	6290	+ { 0x9010c, 0x68 },
	6291	+ { 0x9010d, 0x0 },
	6292	+ { 0x9010e, 0x408 },
	6293	+ { 0x9010f, 0x169 },
	6294	+ { 0x90110, 0x0 },
	6295	+ { 0x90111, 0x8b10 },
	6296	+ { 0x90112, 0x168 },
	6297	+ { 0x90113, 0x1 },
	6298	+ { 0x90114, 0xab10 },
	6299	+ { 0x90115, 0x168 },
	6300	+ { 0x90116, 0x0 },
	6301	+ { 0x90117, 0x1d8 },
	6302	+ { 0x90118, 0x169 },
	6303	+ { 0x90119, 0x80 },
	6304	+ { 0x9011a, 0x790 },
	6305	+ { 0x9011b, 0x16a },
	6306	+ { 0x9011c, 0x18 },
	6307	+ { 0x9011d, 0x7aa },
	6308	+ { 0x9011e, 0x6a },
	6309	+ { 0x9011f, 0xa },
	6310	+ { 0x90120, 0x0 },
	6311	+ { 0x90121, 0x1e9 },
	6312	+ { 0x90122, 0x8 },
	6313	+ { 0x90123, 0x8080 },
	6314	+ { 0x90124, 0x108 },
	6315	+ { 0x90125, 0xf },
	6316	+ { 0x90126, 0x408 },
	6317	+ { 0x90127, 0x169 },
	6318	+ { 0x90128, 0xc },
	6319	+ { 0x90129, 0x0 },
	6320	+ { 0x9012a, 0x68 },
	6321	+ { 0x9012b, 0x9 },
	6322	+ { 0x9012c, 0x0 },
	6323	+ { 0x9012d, 0x1a9 },
	6324	+ { 0x9012e, 0x0 },
	6325	+ { 0x9012f, 0x408 },
	6326	+ { 0x90130, 0x169 },
	6327	+ { 0x90131, 0x0 },
	6328	+ { 0x90132, 0x8080 },
	6329	+ { 0x90133, 0x108 },
	6330	+ { 0x90134, 0x8 },
	6331	+ { 0x90135, 0x7aa },
	6332	+ { 0x90136, 0x6a },
	6333	+ { 0x90137, 0x0 },
	6334	+ { 0x90138, 0x8568 },
	6335	+ { 0x90139, 0x108 },
	6336	+ { 0x9013a, 0xb7 },
	6337	+ { 0x9013b, 0x790 },
	6338	+ { 0x9013c, 0x16a },
	6339	+ { 0x9013d, 0x1f },
	6340	+ { 0x9013e, 0x0 },
	6341	+ { 0x9013f, 0x68 },
	6342	+ { 0x90140, 0x8 },
	6343	+ { 0x90141, 0x8558 },
	6344	+ { 0x90142, 0x168 },
	6345	+ { 0x90143, 0xf },
	6346	+ { 0x90144, 0x408 },
	6347	+ { 0x90145, 0x169 },
	6348	+ { 0x90146, 0xd },
	6349	+ { 0x90147, 0x0 },
	6350	+ { 0x90148, 0x68 },
	6351	+ { 0x90149, 0x0 },
	6352	+ { 0x9014a, 0x408 },
	6353	+ { 0x9014b, 0x169 },
	6354	+ { 0x9014c, 0x0 },
	6355	+ { 0x9014d, 0x8558 },
	6356	+ { 0x9014e, 0x168 },
	6357	+ { 0x9014f, 0x8 },
	6358	+ { 0x90150, 0x3c8 },
	6359	+ { 0x90151, 0x1a9 },
	6360	+ { 0x90152, 0x3 },
	6361	+ { 0x90153, 0x370 },
	6362	+ { 0x90154, 0x129 },
	6363	+ { 0x90155, 0x20 },
	6364	+ { 0x90156, 0x2aa },
	6365	+ { 0x90157, 0x9 },
	6366	+ { 0x90158, 0x8 },
	6367	+ { 0x90159, 0xe8 },
	6368	+ { 0x9015a, 0x109 },
	6369	+ { 0x9015b, 0x0 },
	6370	+ { 0x9015c, 0x8140 },
	6371	+ { 0x9015d, 0x10c },
	6372	+ { 0x9015e, 0x10 },
	6373	+ { 0x9015f, 0x8138 },
	6374	+ { 0x90160, 0x104 },
	6375	+ { 0x90161, 0x8 },
	6376	+ { 0x90162, 0x448 },
	6377	+ { 0x90163, 0x109 },
	6378	+ { 0x90164, 0xf },
	6379	+ { 0x90165, 0x7c0 },
	6380	+ { 0x90166, 0x109 },
	6381	+ { 0x90167, 0x0 },
	6382	+ { 0x90168, 0xe8 },
	6383	+ { 0x90169, 0x109 },
	6384	+ { 0x9016a, 0x47 },
	6385	+ { 0x9016b, 0x630 },
	6386	+ { 0x9016c, 0x109 },
	6387	+ { 0x9016d, 0x8 },
	6388	+ { 0x9016e, 0x618 },
	6389	+ { 0x9016f, 0x109 },
	6390	+ { 0x90170, 0x8 },
	6391	+ { 0x90171, 0xe0 },
	6392	+ { 0x90172, 0x109 },
	6393	+ { 0x90173, 0x0 },
	6394	+ { 0x90174, 0x7c8 },
	6395	+ { 0x90175, 0x109 },
	6396	+ { 0x90176, 0x8 },
	6397	+ { 0x90177, 0x8140 },
	6398	+ { 0x90178, 0x10c },
	6399	+ { 0x90179, 0x0 },
	6400	+ { 0x9017a, 0x478 },
	6401	+ { 0x9017b, 0x109 },
	6402	+ { 0x9017c, 0x0 },
	6403	+ { 0x9017d, 0x1 },
	6404	+ { 0x9017e, 0x8 },
	6405	+ { 0x9017f, 0x8 },
	6406	+ { 0x90180, 0x4 },
	6407	+ { 0x90181, 0x0 },
	6408	+ { 0x90006, 0x8 },
	6409	+ { 0x90007, 0x7c8 },
	6410	+ { 0x90008, 0x109 },
	6411	+ { 0x90009, 0x0 },
	6412	+ { 0x9000a, 0x400 },
	6413	+ { 0x9000b, 0x106 },
	6414	+ { 0xd00e7, 0x400 },
	6415	+ { 0x90017, 0x0 },
	6416	+ { 0x9001f, 0x29 },
	6417	+ { 0x90026, 0x68 },
	6418	+ { 0x400d0, 0x0 },
	6419	+ { 0x400d1, 0x101 },
	6420	+ { 0x400d2, 0x105 },
	6421	+ { 0x400d3, 0x107 },
	6422	+ { 0x400d4, 0x10f },
	6423	+ { 0x400d5, 0x202 },
	6424	+ { 0x400d6, 0x20a },
	6425	+ { 0x400d7, 0x20b },
	6426	+ { 0x2003a, 0x2 },
	6427	+ { 0x200be, 0x3 },
	6428	+ { 0x2000b, 0x64 },
	6429	+ { 0x2000c, 0xc8 },
	6430	+ { 0x2000d, 0x7d0 },
	6431	+ { 0x2000e, 0x2c },
	6432	+ { 0x12000b, 0xc },
	6433	+ { 0x12000c, 0x19 },
	6434	+ { 0x12000d, 0xfa },
	6435	+ { 0x12000e, 0x10 },
	6436	+ { 0x22000b, 0x3 },
	6437	+ { 0x22000c, 0x6 },
	6438	+ { 0x22000d, 0x3e },
	6439	+ { 0x22000e, 0x10 },
	6440	+ { 0x9000c, 0x0 },
	6441	+ { 0x9000d, 0x173 },
	6442	+ { 0x9000e, 0x60 },
	6443	+ { 0x9000f, 0x6110 },
	6444	+ { 0x90010, 0x2152 },
	6445	+ { 0x90011, 0xdfbd },
	6446	+ { 0x90012, 0x2060 },
	6447	+ { 0x90013, 0x6152 },
	6448	+ { 0x20010, 0x5a },
	6449	+ { 0x20011, 0x3 },
	6450	+ { 0x40080, 0xe0 },
	6451	+ { 0x40081, 0x12 },
	6452	+ { 0x40082, 0xe0 },
	6453	+ { 0x40083, 0x12 },
	6454	+ { 0x40084, 0xe0 },
	6455	+ { 0x40085, 0x12 },
	6456	+ { 0x140080, 0xe0 },
	6457	+ { 0x140081, 0x12 },
	6458	+ { 0x140082, 0xe0 },
	6459	+ { 0x140083, 0x12 },
	6460	+ { 0x140084, 0xe0 },
	6461	+ { 0x140085, 0x12 },
	6462	+ { 0x240080, 0xe0 },
	6463	+ { 0x240081, 0x12 },
	6464	+ { 0x240082, 0xe0 },
	6465	+ { 0x240083, 0x12 },
	6466	+ { 0x240084, 0xe0 },
	6467	+ { 0x240085, 0x12 },
	6468	+ { 0x400fd, 0xf },
	6469	+ { 0x10011, 0x1 },
	6470	+ { 0x10012, 0x1 },
	6471	+ { 0x10013, 0x180 },
	6472	+ { 0x10018, 0x1 },
	6473	+ { 0x10002, 0x6209 },
	6474	+ { 0x100b2, 0x1 },
	6475	+ { 0x101b4, 0x1 },
	6476	+ { 0x102b4, 0x1 },
	6477	+ { 0x103b4, 0x1 },
	6478	+ { 0x104b4, 0x1 },
	6479	+ { 0x105b4, 0x1 },
	6480	+ { 0x106b4, 0x1 },
	6481	+ { 0x107b4, 0x1 },
	6482	+ { 0x108b4, 0x1 },
	6483	+ { 0x11011, 0x1 },
	6484	+ { 0x11012, 0x1 },
	6485	+ { 0x11013, 0x180 },
	6486	+ { 0x11018, 0x1 },
	6487	+ { 0x11002, 0x6209 },
	6488	+ { 0x110b2, 0x1 },
	6489	+ { 0x111b4, 0x1 },
	6490	+ { 0x112b4, 0x1 },
	6491	+ { 0x113b4, 0x1 },
	6492	+ { 0x114b4, 0x1 },
	6493	+ { 0x115b4, 0x1 },
	6494	+ { 0x116b4, 0x1 },
	6495	+ { 0x117b4, 0x1 },
	6496	+ { 0x118b4, 0x1 },
	6497	+ { 0x12011, 0x1 },
	6498	+ { 0x12012, 0x1 },
	6499	+ { 0x12013, 0x180 },
	6500	+ { 0x12018, 0x1 },
	6501	+ { 0x12002, 0x6209 },
	6502	+ { 0x120b2, 0x1 },
	6503	+ { 0x121b4, 0x1 },
	6504	+ { 0x122b4, 0x1 },
	6505	+ { 0x123b4, 0x1 },
	6506	+ { 0x124b4, 0x1 },
	6507	+ { 0x125b4, 0x1 },
	6508	+ { 0x126b4, 0x1 },
	6509	+ { 0x127b4, 0x1 },
	6510	+ { 0x128b4, 0x1 },
	6511	+ { 0x13011, 0x1 },
	6512	+ { 0x13012, 0x1 },
	6513	+ { 0x13013, 0x180 },
	6514	+ { 0x13018, 0x1 },
	6515	+ { 0x13002, 0x6209 },
	6516	+ { 0x130b2, 0x1 },
	6517	+ { 0x131b4, 0x1 },
	6518	+ { 0x132b4, 0x1 },
	6519	+ { 0x133b4, 0x1 },
	6520	+ { 0x134b4, 0x1 },
	6521	+ { 0x135b4, 0x1 },
	6522	+ { 0x136b4, 0x1 },
	6523	+ { 0x137b4, 0x1 },
	6524	+ { 0x138b4, 0x1 },
	6525	+ { 0x20089, 0x1 },
	6526	+ { 0x20088, 0x19 },
	6527	+ { 0xc0080, 0x2 },
	6528	+ { 0xd0000, 0x1 }
	6529	+};
	6530	+
	6531	+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
	6532	+ {
	6533	+ /* P0 3200mts 1D */
	6534	+ .drate = 3200,
	6535	+ .fw_type = FW_1D_IMAGE,
	6536	+ .fsp_cfg = ddr_fsp0_cfg,
	6537	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
	6538	+ },
	6539	+ {
	6540	+ /* P1 400mts 1D */
	6541	+ .drate = 400,
	6542	+ .fw_type = FW_1D_IMAGE,
	6543	+ .fsp_cfg = ddr_fsp1_cfg,
	6544	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
	6545	+ },
	6546	+ {
	6547	+ /* P2 100mts 1D */
	6548	+ .drate = 100,
	6549	+ .fw_type = FW_1D_IMAGE,
	6550	+ .fsp_cfg = ddr_fsp2_cfg,
	6551	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
	6552	+ },
	6553	+ {
	6554	+ /* P0 3200mts 2D */
	6555	+ .drate = 3200,
	6556	+ .fw_type = FW_2D_IMAGE,
	6557	+ .fsp_cfg = ddr_fsp0_2d_cfg,
	6558	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
	6559	+ },
	6560	+};
	6561	+
	6562	+/* ddr timing config params */
	6563	+struct dram_timing_info dram_timing = {
	6564	+ .ddrc_cfg = ddr_ddrc_cfg,
	6565	+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
	6566	+ .ddrphy_cfg = ddr_ddrphy_cfg,
	6567	+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
	6568	+ .fsp_msg = ddr_dram_fsp_msg,
	6569	+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
	6570	+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
	6571	+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
	6572	+ .ddrphy_pie = ddr_phy_pie,
	6573	+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
	6574	+ .fsp_table = { 3200, 400, 100, },
	6575	+};
	6576	diff --git a/board/freescale/gauguin-imx8mp/spl.c b/board/freescale/gauguin-imx8mp/spl.c
	6577	new file mode 100644
	6578	index 00000000..913e2868
	6579	--- /dev/null
	6580	+++ b/board/freescale/gauguin-imx8mp/spl.c
	6581	@@ -0,0 +1,188 @@
	6582	+// SPDX-License-Identifier: GPL-2.0-or-later
	6583	+/*
	6584	+ * Copyright 2018-2019, 2021 NXP
	6585	+ *
	6586	+ */
	6587	+
	6588	+#include <common.h>
	6589	+#include <hang.h>
	6590	+#include <init.h>
	6591	+#include <log.h>
	6592	+#include <spl.h>
	6593	+#include <asm/global_data.h>
	6594	+#include <asm/arch/imx8mp_pins.h>
	6595	+#include <asm/arch/sys_proto.h>
	6596	+#include <asm/mach-imx/boot_mode.h>
	6597	+#include <power/pmic.h>
	6598	+
	6599	+#include <power/pca9450.h>
	6600	+#include <asm/arch/clock.h>
	6601	+#include <dm/uclass.h>
	6602	+#include <dm/device.h>
	6603	+#include <dm/uclass-internal.h>
	6604	+#include <dm/device-internal.h>
	6605	+#include <asm/mach-imx/gpio.h>
	6606	+#include <asm/mach-imx/iomux-v3.h>
	6607	+#include <asm/mach-imx/mxc_i2c.h>
	6608	+#include <fsl_esdhc_imx.h>
	6609	+#include <mmc.h>
	6610	+#include <asm/arch/ddr.h>
	6611	+
	6612	+DECLARE_GLOBAL_DATA_PTR;
	6613	+
	6614	+int spl_board_boot_device(enum boot_device boot_dev_spl)
	6615	+{
	6616	+#ifdef CONFIG_SPL_BOOTROM_SUPPORT
	6617	+ return BOOT_DEVICE_BOOTROM;
	6618	+#else
	6619	+ switch (boot_dev_spl) {
	6620	+ case SD1_BOOT:
	6621	+ case MMC1_BOOT:
	6622	+ case SD2_BOOT:
	6623	+ case MMC2_BOOT:
	6624	+ return BOOT_DEVICE_MMC1;
	6625	+ case SD3_BOOT:
	6626	+ case MMC3_BOOT:
	6627	+ return BOOT_DEVICE_MMC2;
	6628	+ case QSPI_BOOT:
	6629	+ return BOOT_DEVICE_NOR;
	6630	+ case NAND_BOOT:
	6631	+ return BOOT_DEVICE_NAND;
	6632	+ case USB_BOOT:
	6633	+ return BOOT_DEVICE_BOARD;
	6634	+ default:
	6635	+ return BOOT_DEVICE_NONE;
	6636	+ }
	6637	+#endif
	6638	+}
	6639	+
	6640	+void spl_dram_init(void)
	6641	+{
	6642	+ ddr_init(&dram_timing);
	6643	+}
	6644	+
	6645	+void spl_board_init(void)
	6646	+{
	6647	+ if (IS_ENABLED(CONFIG_FSL_CAAM)) {
	6648	+ struct udevice *dev;
	6649	+ int ret;
	6650	+
	6651	+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
	6652	+ if (ret)
	6653	+ printf("Failed to initialize caam_jr: %d\n", ret);
	6654	+ }
	6655	+ /*
	6656	+ * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
	6657	+ * not allow to change it. Should set the clock after PMIC
	6658	+ * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
	6659	+ * set by ROM for ND VDD_SOC
	6660	+ */
	6661	+#if defined(CONFIG_IMX8M_LPDDR4) && !defined(CONFIG_IMX8M_VDD_SOC_850MV)
	6662	+ clock_enable(CCGR_GIC, 0);
	6663	+ clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON \| CLK_ROOT_SOURCE_SEL(5));
	6664	+ clock_enable(CCGR_GIC, 1);
	6665	+
	6666	+ puts("Normal Boot\n");
	6667	+#endif
	6668	+}
	6669	+
	6670	+#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
	6671	+int power_init_board(void)
	6672	+{
	6673	+ struct udevice *dev;
	6674	+ int ret;
	6675	+
	6676	+ ret = pmic_get("pca9450@25", &dev);
	6677	+ if (ret == -ENODEV) {
	6678	+ puts("No pca9450@25\n");
	6679	+ return 0;
	6680	+ }
	6681	+ if (ret != 0)
	6682	+ return ret;
	6683	+
	6684	+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
	6685	+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
	6686	+
	6687	+#ifdef CONFIG_IMX8M_LPDDR4
	6688	+ /*
	6689	+ * increase VDD_SOC to typical value 0.95V before first
	6690	+ * DRAM access, set DVS1 to 0.85v for suspend.
	6691	+ * Enable DVS control through PMIC_STBY_REQ and
	6692	+ * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
	6693	+ */
	6694	+#ifdef CONFIG_IMX8M_VDD_SOC_850MV
	6695	+ /* set DVS0 to 0.85v for special case*/
	6696	+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
	6697	+#else
	6698	+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
	6699	+#endif
	6700	+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
	6701	+ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
	6702	+
	6703	+ /* Kernel uses OD/OD freq for SOC */
	6704	+ /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
	6705	+ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
	6706	+#elif defined(CONFIG_IMX8M_DDR4)
	6707	+ /* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */
	6708	+ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
	6709	+
	6710	+ /* Set NVCC_DRAM to 1.2v for DDR4 */
	6711	+ pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x18);
	6712	+#endif
	6713	+
	6714	+ /* set WDOG_B_CFG to cold reset */
	6715	+ pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
	6716	+
	6717	+ return 0;
	6718	+}
	6719	+#endif
	6720	+
	6721	+#ifdef CONFIG_SPL_LOAD_FIT
	6722	+int board_fit_config_name_match(const char *name)
	6723	+{
	6724	+ /* Just empty function now - can't decide what to choose */
	6725	+ debug("%s: %s\n", __func__, name);
	6726	+
	6727	+ return 0;
	6728	+}
	6729	+#endif
	6730	+
	6731	+void board_init_f(ulong dummy)
	6732	+{
	6733	+ struct udevice *dev;
	6734	+ int ret;
	6735	+
	6736	+ /* Clear the BSS. */
	6737	+ memset(__bss_start, 0, __bss_end - __bss_start);
	6738	+
	6739	+ arch_cpu_init();
	6740	+
	6741	+ board_early_init_f();
	6742	+
	6743	+ timer_init();
	6744	+
	6745	+ preloader_console_init();
	6746	+
	6747	+ ret = spl_early_init();
	6748	+ if (ret) {
	6749	+ debug("spl_early_init() failed: %d\n", ret);
	6750	+ hang();
	6751	+ }
	6752	+
	6753	+ ret = uclass_get_device_by_name(UCLASS_CLK,
	6754	+ "clock-controller@30380000",
	6755	+ &dev);
	6756	+ if (ret < 0) {
	6757	+ printf("Failed to find clock node. Check device tree\n");
	6758	+ hang();
	6759	+ }
	6760	+
	6761	+ enable_tzc380();
	6762	+
	6763	+ power_init_board();
	6764	+
	6765	+ /* DDR initialization */
	6766	+ spl_dram_init();
	6767	+
	6768	+ board_init_r(NULL, 0);
	6769	+}
	6770	diff --git a/configs/gauguin-imx8mp_defconfig b/configs/gauguin-imx8mp_defconfig
	6771	new file mode 100644
	6772	index 00000000..2ffd5329
	6773	--- /dev/null
	6774	+++ b/configs/gauguin-imx8mp_defconfig
	6775	@@ -0,0 +1,178 @@
	6776	+CONFIG_ARM=y
	6777	+CONFIG_ARCH_IMX8M=y
	6778	+CONFIG_SYS_TEXT_BASE=0x40200000
	6779	+CONFIG_SYS_MALLOC_LEN=0x2000000
	6780	+CONFIG_SYS_MALLOC_F_LEN=0x10000
	6781	+CONFIG_SPL_GPIO=y
	6782	+CONFIG_SPL_LIBCOMMON_SUPPORT=y
	6783	+CONFIG_SPL_LIBGENERIC_SUPPORT=y
	6784	+CONFIG_NR_DRAM_BANKS=3
	6785	+CONFIG_SYS_MEMTEST_START=0x60000000
	6786	+CONFIG_SYS_MEMTEST_END=0xC0000000
	6787	+CONFIG_ENV_SIZE=0x4000
	6788	+CONFIG_ENV_OFFSET=0x400000
	6789	+CONFIG_ENV_SECT_SIZE=0x10000
	6790	+CONFIG_DM_GPIO=y
	6791	+CONFIG_DEFAULT_DEVICE_TREE="gauguin-imx8mp"
	6792	+CONFIG_SPL_TEXT_BASE=0x920000
	6793	+CONFIG_TARGET_GAUGUIN_IMX8MP=y
	6794	+CONFIG_SPL_SERIAL=y
	6795	+CONFIG_SPL_DRIVERS_MISC=y
	6796	+CONFIG_SPL=y
	6797	+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
	6798	+CONFIG_OF_BOARD_FIXUP=y
	6799	+CONFIG_DISTRO_DEFAULTS=y
	6800	+CONFIG_SYS_LOAD_ADDR=0x40400000
	6801	+CONFIG_FIT=y
	6802	+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
	6803	+CONFIG_FIT_SIGNATURE=y
	6804	+CONFIG_SPL_LOAD_FIT=y
	6805	+CONFIG_LEGACY_IMAGE_FORMAT=y
	6806	+CONFIG_OF_BOARD_SETUP=y
	6807	+CONFIG_OF_SYSTEM_SETUP=y
	6808	+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
	6809	+CONFIG_DEFAULT_FDT_FILE="gauguin-imx8mp.dtb"
	6810	+CONFIG_BOARD_EARLY_INIT_F=y
	6811	+CONFIG_BOARD_LATE_INIT=y
	6812	+CONFIG_SPL_BOARD_INIT=y
	6813	+CONFIG_SPL_BOOTROM_SUPPORT=y
	6814	+CONFIG_SPL_SEPARATE_BSS=y
	6815	+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
	6816	+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
	6817	+CONFIG_SPL_I2C=y
	6818	+CONFIG_SPL_POWER=y
	6819	+CONFIG_SPL_WATCHDOG=y
	6820	+CONFIG_SYS_PROMPT="[u-boot@IGKBoard]# "
	6821	+# CONFIG_BOOTM_NETBSD is not set
	6822	+# CONFIG_CMD_EXPORTENV is not set
	6823	+# CONFIG_CMD_IMPORTENV is not set
	6824	+CONFIG_CMD_ERASEENV=y
	6825	+CONFIG_CMD_NVEDIT_EFI=y
	6826	+CONFIG_CRC32_VERIFY=y
	6827	+CONFIG_CMD_MEMTEST=y
	6828	+CONFIG_CMD_CLK=y
	6829	+CONFIG_CMD_DFU=y
	6830	+CONFIG_CMD_FUSE=y
	6831	+CONFIG_CMD_GPIO=y
	6832	+CONFIG_CMD_I2C=y
	6833	+CONFIG_CMD_MMC=y
	6834	+CONFIG_CMD_OPTEE_RPMB=y
	6835	+CONFIG_CMD_POWEROFF=y
	6836	+CONFIG_CMD_USB=y
	6837	+CONFIG_CMD_USB_MASS_STORAGE=y
	6838	+CONFIG_CMD_SNTP=y
	6839	+CONFIG_CMD_BMP=y
	6840	+CONFIG_CMD_CACHE=y
	6841	+CONFIG_CMD_EFIDEBUG=y
	6842	+CONFIG_CMD_RTC=y
	6843	+CONFIG_CMD_TIME=y
	6844	+CONFIG_CMD_GETTIME=y
	6845	+CONFIG_CMD_TIMER=y
	6846	+CONFIG_CMD_REGULATOR=y
	6847	+CONFIG_CMD_EXT4_WRITE=y
	6848	+CONFIG_OF_CONTROL=y
	6849	+CONFIG_SPL_OF_CONTROL=y
	6850	+CONFIG_ENV_OVERWRITE=y
	6851	+CONFIG_ENV_IS_NOWHERE=y
	6852	+CONFIG_ENV_IS_IN_MMC=y
	6853	+CONFIG_ENV_IS_IN_SPI_FLASH=y
	6854	+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
	6855	+CONFIG_SYS_MMC_ENV_DEV=1
	6856	+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
	6857	+CONFIG_NET_RANDOM_ETHADDR=y
	6858	+CONFIG_SPL_DM=y
	6859	+CONFIG_REGMAP=y
	6860	+CONFIG_SYSCON=y
	6861	+CONFIG_SPL_CLK_COMPOSITE_CCF=y
	6862	+CONFIG_CLK_COMPOSITE_CCF=y
	6863	+CONFIG_SPL_CLK_IMX8MP=y
	6864	+CONFIG_CLK_IMX8MP=y
	6865	+CONFIG_DFU_TFTP=y
	6866	+CONFIG_DFU_MMC=y
	6867	+CONFIG_DFU_RAM=y
	6868	+CONFIG_USB_FUNCTION_FASTBOOT=y
	6869	+CONFIG_UDP_FUNCTION_FASTBOOT=y
	6870	+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
	6871	+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
	6872	+CONFIG_FASTBOOT_FLASH=y
	6873	+CONFIG_MXC_GPIO=y
	6874	+CONFIG_DM_PCA953X=y
	6875	+CONFIG_DM_I2C=y
	6876	+CONFIG_LED=y
	6877	+CONFIG_LED_GPIO=y
	6878	+CONFIG_SUPPORT_EMMC_RPMB=y
	6879	+CONFIG_SUPPORT_EMMC_BOOT=y
	6880	+CONFIG_MMC_IO_VOLTAGE=y
	6881	+CONFIG_MMC_UHS_SUPPORT=y
	6882	+CONFIG_MMC_HS400_ES_SUPPORT=y
	6883	+CONFIG_MMC_HS400_SUPPORT=y
	6884	+CONFIG_FSL_USDHC=y
	6885	+CONFIG_DM_SPI_FLASH=y
	6886	+CONFIG_SF_DEFAULT_MODE=0
	6887	+CONFIG_SF_DEFAULT_SPEED=40000000
	6888	+CONFIG_SPI_FLASH_BAR=y
	6889	+CONFIG_SPI_FLASH_STMICRO=y
	6890	+CONFIG_PHY_REALTEK=y
	6891	+CONFIG_DM_ETH=y
	6892	+CONFIG_DM_ETH_PHY=y
	6893	+CONFIG_PHY_GIGE=y
	6894	+CONFIG_DWC_ETH_QOS=y
	6895	+CONFIG_DWC_ETH_QOS_IMX=y
	6896	+CONFIG_FEC_MXC=y
	6897	+CONFIG_MII=y
	6898	+CONFIG_PHY=y
	6899	+CONFIG_PHY_IMX8MQ_USB=y
	6900	+CONFIG_PINCTRL=y
	6901	+CONFIG_SPL_PINCTRL=y
	6902	+CONFIG_PINCTRL_IMX8M=y
	6903	+CONFIG_DM_PMIC=y
	6904	+CONFIG_SPL_DM_PMIC_PCA9450=y
	6905	+CONFIG_DM_REGULATOR=y
	6906	+CONFIG_DM_REGULATOR_FIXED=y
	6907	+CONFIG_DM_REGULATOR_GPIO=y
	6908	+CONFIG_DM_RTC=y
	6909	+CONFIG_RTC_EMULATION=y
	6910	+CONFIG_MXC_UART=y
	6911	+CONFIG_SPI=y
	6912	+CONFIG_DM_SPI=y
	6913	+CONFIG_NXP_FSPI=y
	6914	+CONFIG_SYSRESET=y
	6915	+CONFIG_SYSRESET_PSCI=y
	6916	+CONFIG_TEE=y
	6917	+CONFIG_OPTEE=y
	6918	+CONFIG_DM_THERMAL=y
	6919	+CONFIG_IMX_TMU=y
	6920	+CONFIG_USB=y
	6921	+CONFIG_USB_XHCI_HCD=y
	6922	+CONFIG_USB_XHCI_DWC3=y
	6923	+CONFIG_USB_DWC3=y
	6924	+CONFIG_USB_GADGET=y
	6925	+CONFIG_USB_GADGET_MANUFACTURER="FSL"
	6926	+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
	6927	+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
	6928	+CONFIG_DM_VIDEO=y
	6929	+CONFIG_VIDEO_LOGO=y
	6930	+CONFIG_SYS_WHITE_ON_BLACK=y
	6931	+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
	6932	+CONFIG_VIDEO_IMX_SEC_DSI=y
	6933	+CONFIG_VIDEO_IMX_LCDIFV3=y
	6934	+CONFIG_SPLASH_SCREEN=y
	6935	+CONFIG_SPLASH_SCREEN_ALIGN=y
	6936	+CONFIG_BMP_16BPP=y
	6937	+CONFIG_BMP_24BPP=y
	6938	+CONFIG_BMP_32BPP=y
	6939	+CONFIG_VIDEO_ADV7535=y
	6940	+CONFIG_SPL_RSA=y
	6941	+CONFIG_SHA384=y
	6942	+CONFIG_LZO=y
	6943	+CONFIG_BZIP2=y
	6944	+CONFIG_OF_LIBFDT_OVERLAY=y
	6945	+CONFIG_EFI_MM_COMM_TEE=y
	6946	+CONFIG_EFI_VAR_BUF_SIZE=139264
	6947	+CONFIG_EFI_SET_TIME=y
	6948	+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
	6949	+CONFIG_EFI_CAPSULE_ON_DISK=y
	6950	+CONFIG_EFI_IGNORE_OSINDICATIONS=y
	6951	+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
	6952	+CONFIG_EFI_CAPSULE_AUTHENTICATE=y
	6953	+CONFIG_EFI_SECURE_BOOT=y
	6954	diff --git a/drivers/video/u_boot_logo.S b/drivers/video/u_boot_logo.S
	6955	new file mode 100644
	6956	index 00000000..80551a33
	6957	--- /dev/null
	6958	+++ b/drivers/video/u_boot_logo.S
	6959	@@ -0,0 +1,8 @@
	6960	+.section .rodata.splash.init,"a"
	6961	+.balign 16
	6962	+.global __splash_u_boot_logo_begin
	6963	+__splash_u_boot_logo_begin:
	6964	+.incbin "drivers/video/u_boot_logo.bmp"
	6965	+__splash_u_boot_logo_end:
	6966	+.global __splash_u_boot_logo_end
	6967	+.balign 16
	6968	diff --git a/include/configs/gauguin-imx8mp.h b/include/configs/gauguin-imx8mp.h
	6969	new file mode 100644
	6970	index 00000000..0f5f3368
	6971	--- /dev/null
	6972	+++ b/include/configs/gauguin-imx8mp.h
	6973	@@ -0,0 +1,246 @@
	6974	+/* SPDX-License-Identifier: GPL-2.0+ */
	6975	+/*
	6976	+ * Copyright 2019 NXP
	6977	+ */
	6978	+
	6979	+#ifndef __GAUGUIN_IMX8MP_H
	6980	+#define __GAUGUIN_IMX8MP_H
	6981	+
	6982	+#include <linux/sizes.h>
	6983	+#include <linux/stringify.h>
	6984	+#include <asm/arch/imx-regs.h>
	6985	+#include "imx_env.h"
	6986	+
	6987	+#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
	6988	+
	6989	+#define CONFIG_SPL_MAX_SIZE (176 * 1024)
	6990	+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	6991	+#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
	6992	+
	6993	+#ifdef CONFIG_SPL_BUILD
	6994	+#define CONFIG_SPL_STACK 0x96dff0
	6995	+#define CONFIG_SPL_BSS_START_ADDR 0x96e000
	6996	+#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
	6997	+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
	6998	+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
	6999	+
	7000	+/* For RAW image gives a error info not panic */
	7001	+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
	7002	+
	7003	+#if defined(CONFIG_NAND_BOOT)
	7004	+#define CONFIG_SPL_NAND_BASE
	7005	+#define CONFIG_SPL_NAND_IDENT
	7006	+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */
	7007	+
	7008	+/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */
	7009	+#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \
	7010	+ (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400)
	7011	+#endif
	7012	+
	7013	+#endif
	7014	+
	7015	+#define CONFIG_CMD_READ
	7016	+#define CONFIG_SERIAL_TAG
	7017	+#define CONFIG_FASTBOOT_USB_DEV 0
	7018	+
	7019	+#define CONFIG_REMAKE_ELF
	7020	+/* ENET Config */
	7021	+/* ENET1 */
	7022	+
	7023	+#if defined(CONFIG_CMD_NET)
	7024	+#define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */
	7025	+
	7026	+#define CONFIG_FEC_XCV_TYPE RGMII
	7027	+#define CONFIG_FEC_MXC_PHYADDR 1
	7028	+
	7029	+#define DWC_NET_PHYADDR 1
	7030	+
	7031	+#define PHY_ANEG_TIMEOUT 20000
	7032	+
	7033	+#endif
	7034	+
	7035	+#ifdef CONFIG_DISTRO_DEFAULTS
	7036	+#define BOOT_TARGET_DEVICES(func) \
	7037	+ func(USB, usb, 0) \
	7038	+ func(MMC, mmc, 1) \
	7039	+ func(MMC, mmc, 2)
	7040	+
	7041	+#include <config_distro_bootcmd.h>
	7042	+#else
	7043	+#define BOOTENV
	7044	+#endif
	7045	+
	7046	+#define JH_ROOT_DTB "gauguin-imx8mp-root.dtb"
	7047	+
	7048	+#define JAILHOUSE_ENV \
	7049	+ "jh_clk= \0 " \
	7050	+ "jh_root_dtb=" JH_ROOT_DTB "\0" \
	7051	+ "jh_mmcboot=setenv fdtfile ${jh_root_dtb};" \
	7052	+ "setenv jh_clk clk_ignore_unused mem=1920MB; " \
	7053	+ "if run loadimage; then " \
	7054	+ "run mmcboot; " \
	7055	+ "else run jh_netboot; fi; \0" \
	7056	+ "jh_netboot=setenv fdtfile ${jh_root_dtb}; setenv jh_clk clk_ignore_unused mem=1920MB; run netboot; \0 "
	7057	+
	7058	+#define CONFIG_MFG_ENV_SETTINGS \
	7059	+ CONFIG_MFG_ENV_SETTINGS_DEFAULT \
	7060	+ "initrd_addr=0x43800000\0" \
	7061	+ "initrd_high=0xffffffffffffffff\0" \
	7062	+ "emmc_dev=2\0"\
	7063	+ "sd_dev=1\0"
	7064	+
	7065	+
	7066	+#ifdef CONFIG_NAND_BOOT
	7067	+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)"
	7068	+#endif
	7069	+
	7070	+/* Initial environment variables */
	7071	+#if defined(CONFIG_NAND_BOOT)
	7072	+#define CONFIG_EXTRA_ENV_SETTINGS \
	7073	+ CONFIG_MFG_ENV_SETTINGS \
	7074	+ "splashimage=0x50000000\0" \
	7075	+ "fdt_addr_r=0x43000000\0" \
	7076	+ "fdt_addr=0x43000000\0" \
	7077	+ "fdt_high=0xffffffffffffffff\0" \
	7078	+ "mtdparts=" MFG_NAND_PARTITION "\0" \
	7079	+ "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
	7080	+ "bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=nandrootfs " \
	7081	+ "root=ubi0:nandrootfs rootfstype=ubifs " \
	7082	+ MFG_NAND_PARTITION \
	7083	+ "\0" \
	7084	+ "bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\
	7085	+ "nand read ${fdt_addr_r} 0x7000000 0x100000;"\
	7086	+ "booti ${loadaddr} - ${fdt_addr_r}"
	7087	+
	7088	+#else
	7089	+#define CONFIG_EXTRA_ENV_SETTINGS \
	7090	+ CONFIG_MFG_ENV_SETTINGS \
	7091	+ JAILHOUSE_ENV \
	7092	+ BOOTENV \
	7093	+ "scriptaddr=0x43500000\0" \
	7094	+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
	7095	+ "bsp_script=boot.scr\0" \
	7096	+ "image=Image\0" \
	7097	+ "splashimage=0x50000000\0" \
	7098	+ "console=ttymxc1,115200\0" \
	7099	+ "fdt_addr_r=0x43000000\0" \
	7100	+ "fdt_addr=0x43000000\0" \
	7101	+ "boot_fdt=try\0" \
	7102	+ "fdt_high=0xffffffffffffffff\0" \
	7103	+ "boot_fit=no\0" \
	7104	+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
	7105	+ "bootm_size=0x10000000\0" \
	7106	+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
	7107	+ "mmcpart=1\0" \
	7108	+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
	7109	+ "mmcautodetect=yes\0" \
	7110	+ "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
	7111	+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \
	7112	+ "bootscript=echo Running bootscript from mmc ...; " \
	7113	+ "source\0" \
	7114	+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
	7115	+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
	7116	+ "ipaddr=192.168.3.10\0" \
	7117	+ "serverip=192.168.3.239\0" \
	7118	+ "nfspath=/srv/nfs/rootfs\0" \
	7119	+ "mmcboot=echo Booting from mmc ...; " \
	7120	+ "run mmcargs; " \
	7121	+ "if test ${boot_fit} = yes \|\| test ${boot_fit} = try; then " \
	7122	+ "bootm ${loadaddr}; " \
	7123	+ "else " \
	7124	+ "if run loadfdt; then " \
	7125	+ "booti ${loadaddr} - ${fdt_addr_r}; " \
	7126	+ "else " \
	7127	+ "echo WARN: Cannot load the DT; " \
	7128	+ "fi; " \
	7129	+ "fi;\0" \
	7130	+ "netargs=setenv bootargs ${jh_clk} console=${console} " \
	7131	+ "root=/dev/nfs " \
	7132	+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
	7133	+ "netargs_nfs=setenv bootargs console=${console} " \
	7134	+ "root=/dev/nfs " \
	7135	+ "nfsroot=${serverip}:${nfspath},proto=tcp rw ip=${ipaddr}:${serverip}:255.255.255.0::eth1:off\0" \
	7136	+ "netboot=echo Booting from net ...; " \
	7137	+ "tftp $loadaddr $image; tftp $fdt_addr ${fdtfile}; " \
	7138	+ "run mmcargs; " \
	7139	+ "booti ${loadaddr} - ${fdt_addr_r}\0" \
	7140	+ "netboot_nfs=echo Booting from net ... rootfs from nfs; " \
	7141	+ "tftp $loadaddr $image; tftp $fdt_addr ${fdtfile}; " \
	7142	+ "run netargs_nfs; " \
	7143	+ "booti ${loadaddr} - ${fdt_addr_r}\0" \
	7144	+ "bsp_bootcmd=echo Running BSP bootcmd ...; " \
	7145	+ "mmc dev ${mmcdev}; if mmc rescan; then " \
	7146	+ "if run loadbootscript; then " \
	7147	+ "run bootscript; " \
	7148	+ "else " \
	7149	+ "if run loadimage; then " \
	7150	+ "run mmcboot; " \
	7151	+ "else run netboot; " \
	7152	+ "fi; " \
	7153	+ "fi; " \
	7154	+ "fi;\0" \
	7155	+ ""
	7156	+#endif
	7157	+
	7158	+/* Link Definitions */
	7159	+
	7160	+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
	7161	+#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
	7162	+#define CONFIG_SYS_INIT_SP_OFFSET \
	7163	+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	7164	+#define CONFIG_SYS_INIT_SP_ADDR \
	7165	+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	7166	+
	7167	+#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
	7168	+
	7169	+/* Totally 6GB DDR */
	7170	+#define CONFIG_SYS_SDRAM_BASE 0x40000000
	7171	+#define PHYS_SDRAM 0x40000000
	7172	+#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
	7173	+#define PHYS_SDRAM_2 0x100000000
	7174	+#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK
	7175	+#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */
	7176	+#else
	7177	+#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
	7178	+#endif
	7179	+
	7180	+#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
	7181	+
	7182	+/* Monitor Command Prompt */
	7183	+#define CONFIG_SYS_CBSIZE 2048
	7184	+#define CONFIG_SYS_MAXARGS 64
	7185	+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	7186	+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	7187	+ sizeof(CONFIG_SYS_PROMPT) + 16)
	7188	+
	7189	+#define CONFIG_IMX_BOOTAUX
	7190	+
	7191	+#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK
	7192	+#define CONFIG_SYS_FSL_USDHC_NUM 1
	7193	+#else
	7194	+#define CONFIG_SYS_FSL_USDHC_NUM 2
	7195	+#endif
	7196	+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
	7197	+
	7198	+#ifdef CONFIG_NAND_MXS
	7199	+#define CONFIG_CMD_NAND_TRIMFFS
	7200	+
	7201	+/* NAND stuff */
	7202	+#define CONFIG_SYS_MAX_NAND_DEVICE 1
	7203	+#define CONFIG_SYS_NAND_BASE 0x20000000
	7204	+#define CONFIG_SYS_NAND_USE_FLASH_BBT
	7205	+#endif /* CONFIG_NAND_MXS */
	7206	+
	7207	+#define CONFIG_SYS_I2C_SPEED 100000
	7208	+
	7209	+/* USB configs */
	7210	+
	7211	+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
	7212	+#define CONFIG_USBD_HS
	7213	+#define CONFIG_USB_GADGET_VBUS_DRAW 2
	7214	+
	7215	+#ifdef CONFIG_ANDROID_SUPPORT
	7216	+#include "imx8mp_evk_android.h"
	7217	+#endif
	7218	+
	7219	+#endif
	7220	diff --git a/include/configs/gauguin-imx8mp_android.h b/include/configs/gauguin-imx8mp_android.h
	7221	new file mode 100644
	7222	index 00000000..4896ce11
	7223	--- /dev/null
	7224	+++ b/include/configs/gauguin-imx8mp_android.h
	7225	@@ -0,0 +1,46 @@
	7226	+/*
	7227	+ * Copyright 2021 NXP
	7228	+ *
	7229	+ * SPDX-License-Identifier: GPL-2.0+
	7230	+ */
	7231	+
	7232	+#ifndef GAUGUIN_IMX8MP_ANDROID_H
	7233	+#define GAUGUIN_IMX8MP_ANDROID_H
	7234	+
	7235	+#define FSL_FASTBOOT_FB_DEV "mmc"
	7236	+
	7237	+#undef CONFIG_EXTRA_ENV_SETTINGS
	7238	+#undef CONFIG_BOOTCOMMAND
	7239	+
	7240	+#define CONFIG_EXTRA_ENV_SETTINGS \
	7241	+ "splashpos=m,m\0" \
	7242	+ "splashimage=0x50000000\0" \
	7243	+ "fdt_high=0xffffffffffffffff\0" \
	7244	+ "initrd_high=0xffffffffffffffff\0" \
	7245	+
	7246	+/* Enable mcu firmware flash */
	7247	+#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT
	7248	+#define ANDROID_MCU_FRIMWARE_DEV_TYPE DEV_MMC
	7249	+#define ANDROID_MCU_FIRMWARE_START 0x500000
	7250	+#define ANDROID_MCU_OS_PARTITION_SIZE 0x40000
	7251	+#define ANDROID_MCU_FIRMWARE_SIZE 0x20000
	7252	+#define ANDROID_MCU_FIRMWARE_HEADER_STACK 0x20020000
	7253	+#endif
	7254	+
	7255	+#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
	7256	+
	7257	+#ifdef CONFIG_IMX_TRUSTY_OS
	7258	+#define BOOTLOADER_RBIDX_OFFSET 0x3FE000
	7259	+#define BOOTLOADER_RBIDX_START 0x3FF000
	7260	+#define BOOTLOADER_RBIDX_LEN 0x08
	7261	+#define BOOTLOADER_RBIDX_INITVAL 0
	7262	+#endif
	7263	+
	7264	+#ifdef CONFIG_IMX_TRUSTY_OS
	7265	+#define AVB_RPMB
	7266	+#define KEYSLOT_HWPARTITION_ID 2
	7267	+#define KEYSLOT_BLKS 0x1FFF
	7268	+#define NS_ARCH_ARM64 1
	7269	+#endif
	7270	+
	7271	+#endif /* GAUGUIN_IMX8MP_ANDROID_H */
	7272	diff --git a/tools/boot/bootm.c b/tools/boot/bootm.c
	7273	new file mode 100644
	7274	index 00000000..31ddd95f
	7275	--- /dev/null
	7276	+++ b/tools/boot/bootm.c
	7277	@@ -0,0 +1 @@
	7278	+#include <../boot/bootm.c>
	7279	diff --git a/tools/boot/fdt_region.c b/tools/boot/fdt_region.c
	7280	new file mode 100644
	7281	index 00000000..1bb9c886
	7282	--- /dev/null
	7283	+++ b/tools/boot/fdt_region.c
	7284	@@ -0,0 +1 @@
	7285	+#include <../boot/fdt_region.c>
	7286	diff --git a/tools/boot/image-cipher.c b/tools/boot/image-cipher.c
	7287	new file mode 100644
	7288	index 00000000..5013afee
	7289	--- /dev/null
	7290	+++ b/tools/boot/image-cipher.c
	7291	@@ -0,0 +1 @@
	7292	+#include <../boot/image-cipher.c>
	7293	diff --git a/tools/boot/image-fit-sig.c b/tools/boot/image-fit-sig.c
	7294	new file mode 100644
	7295	index 00000000..9da06c71
	7296	--- /dev/null
	7297	+++ b/tools/boot/image-fit-sig.c
	7298	@@ -0,0 +1 @@
	7299	+#include <../boot/image-fit-sig.c>
	7300	diff --git a/tools/boot/image-fit.c b/tools/boot/image-fit.c
	7301	new file mode 100644
	7302	index 00000000..9168e119
	7303	--- /dev/null
	7304	+++ b/tools/boot/image-fit.c
	7305	@@ -0,0 +1 @@
	7306	+#include <../boot/image-fit.c>
	7307	diff --git a/tools/boot/image-host.c b/tools/boot/image-host.c
	7308	new file mode 100644
	7309	index 00000000..fb0ad568
	7310	--- /dev/null
	7311	+++ b/tools/boot/image-host.c
	7312	@@ -0,0 +1 @@
	7313	+#include <../boot/image-host.c>
	7314	diff --git a/tools/boot/image.c b/tools/boot/image.c
	7315	new file mode 100644
	7316	index 00000000..48a2e765
	7317	--- /dev/null
	7318	+++ b/tools/boot/image.c
	7319	@@ -0,0 +1 @@
	7320	+#include <../boot/image.c>