| commit | author | age | ||
| be049f | 1 | diff --git a/.gitignore b/.gitignore |
| W | 2 | index 3a4d056e..1893a337 100644 |
| 3 | --- a/.gitignore | |
| 4 | +++ b/.gitignore | |
| 5 | @@ -30,6 +30,7 @@ | |
| 6 | *.order | |
| 7 | *.patch | |
| 8 | *.s | |
| 9 | +*.S | |
| 10 | *.su | |
| 11 | *.swp | |
| 12 | *.tab.[ch] | |
| 13 | diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile | |
| 14 | index 8b65ac0b..eb0435fa 100644 | |
| 15 | --- a/arch/arm/dts/Makefile | |
| 16 | +++ b/arch/arm/dts/Makefile | |
| 17 | @@ -1030,6 +1030,7 @@ dtb-$(CONFIG_ARCH_IMX8ULP) += \ | |
| 18 | imx8ulp-watch.dtb | |
| 19 | ||
| 20 | dtb-$(CONFIG_ARCH_IMX8M) += \ | |
| 21 | + igkboard-imx8mp.dtb \ | |
| 22 | imx8mm-data-modul-edm-sbc.dtb \ | |
| 23 | imx8mm-ddr4-evk.dtb \ | |
| 24 | imx8mm-ddr4-ab2.dtb \ | |
| 25 | diff --git a/arch/arm/dts/igkboard-imx8mp-u-boot.dtsi b/arch/arm/dts/igkboard-imx8mp-u-boot.dtsi | |
| 26 | new file mode 100644 | |
| 7640c6 | 27 | index 00000000..b69049bb |
| be049f | 28 | --- /dev/null |
| W | 29 | +++ b/arch/arm/dts/igkboard-imx8mp-u-boot.dtsi |
| 7640c6 | 30 | @@ -0,0 +1,86 @@ |
| be049f | 31 | +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| W | 32 | +/* |
| 33 | + * Copy from imx8mp-venice-u-boot.dtsi | |
| 34 | + */ | |
| 35 | + | |
| 36 | +#include "imx8mp-u-boot.dtsi" | |
| 37 | + | |
| 38 | +/ { | |
| 39 | + wdt-reboot { | |
| 40 | + compatible = "wdt-reboot"; | |
| 41 | + wdt = <&wdog1>; | |
| 42 | + u-boot,dm-spl; | |
| 43 | + }; | |
| 44 | +}; | |
| 45 | + | |
| 46 | +&gpio1 { | |
| 47 | + u-boot,dm-spl; | |
| 48 | +}; | |
| 49 | + | |
| 50 | +&gpio2 { | |
| 51 | + u-boot,dm-spl; | |
| 52 | +}; | |
| 53 | + | |
| 54 | +&gpio3 { | |
| 55 | + u-boot,dm-spl; | |
| 56 | +}; | |
| 57 | + | |
| 58 | +&gpio4 { | |
| 59 | + u-boot,dm-spl; | |
| 60 | +}; | |
| 61 | + | |
| 62 | +&gpio5 { | |
| 63 | + u-boot,dm-spl; | |
| 64 | +}; | |
| 65 | + | |
| 66 | +&uart2 { | |
| 67 | + u-boot,dm-spl; | |
| 68 | +}; | |
| 69 | + | |
| 70 | +&pinctrl_uart2 { | |
| 71 | + u-boot,dm-spl; | |
| 72 | +}; | |
| 73 | + | |
| 74 | +&usdhc3 { | |
| 75 | + u-boot,dm-spl; | |
| 76 | +}; | |
| 77 | + | |
| 78 | +&pinctrl_usdhc3 { | |
| 79 | + u-boot,dm-spl; | |
| 80 | +}; | |
| 81 | + | |
| 82 | +&i2c1 { | |
| 83 | + u-boot,dm-spl; | |
| 84 | +}; | |
| 85 | + | |
| 86 | +&pinctrl_i2c1 { | |
| 87 | + u-boot,dm-spl; | |
| 88 | +}; | |
| 89 | + | |
| 84751c | 90 | +&pinctrl_i2c1_gpio { |
| G | 91 | + u-boot,dm-spl; |
| 92 | +}; | |
| 93 | + | |
| be049f | 94 | +&i2c2 { |
| W | 95 | + u-boot,dm-spl; |
| 96 | +}; | |
| 97 | + | |
| 98 | +&wdog1 { | |
| 99 | + u-boot,dm-spl; | |
| 100 | +}; | |
| 101 | + | |
| 102 | +&pinctrl_wdog { | |
| 103 | + u-boot,dm-spl; | |
| 104 | +}; | |
| 7640c6 | 105 | + |
| G | 106 | +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} { |
| 107 | + u-boot,dm-spl; | |
| 108 | +}; | |
| 109 | + | |
| 110 | +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { | |
| 111 | + u-boot,dm-spl; | |
| 112 | +}; | |
| 113 | + | |
| 114 | +&pinctrl_pmic { | |
| 115 | + u-boot,dm-spl; | |
| 116 | +}; | |
| be049f | 117 | diff --git a/arch/arm/dts/igkboard-imx8mp.dts b/arch/arm/dts/igkboard-imx8mp.dts |
| W | 118 | new file mode 100644 |
| 335041 | 119 | index 00000000..2cad034a |
| be049f | 120 | --- /dev/null |
| W | 121 | +++ b/arch/arm/dts/igkboard-imx8mp.dts |
| d3809d | 122 | @@ -0,0 +1,469 @@ |
| be049f | 123 | +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| W | 124 | +/* |
| 125 | + * Copyright 2023 LingYun IoT System Studio. | |
| 126 | + */ | |
| 127 | + | |
| 128 | +/dts-v1/; | |
| 129 | + | |
| 130 | +#include <dt-bindings/usb/pd.h> | |
| 131 | +#include "imx8mp.dtsi" | |
| 132 | + | |
| 133 | +/*+------------------------+ | |
| 134 | + | root node | | |
| 135 | + +------------------------+*/ | |
| 136 | +/ { | |
| 137 | + model = "LingYun IoT Gateway Kits Board based on i.MX8MP"; | |
| 138 | + compatible = "lingyun,igkboard-imx8mp", "fsl,imx8mp"; | |
| 139 | + | |
| 2c3d96 | 140 | + /* console and bootargs */ |
| G | 141 | + chosen { |
| 142 | + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; | |
| 143 | + stdout-path = &uart2; | |
| 144 | + }; | |
| be049f | 145 | + |
| 2c3d96 | 146 | + /* MT53D512M32D2DS-053 WT:D, 2GB LPDDR4 */ |
| be049f | 147 | + memory@80000000 { |
| W | 148 | + device_type = "memory"; |
| 335041 | 149 | + reg = <0x0 0x80000000 0 0x40000000>; |
| 2c3d96 | 150 | + }; |
| be049f | 151 | + |
| W | 152 | + leds { |
| 153 | + compatible = "gpio-leds"; | |
| 154 | + pinctrl-names = "default"; | |
| 2c3d96 | 155 | + pinctrl-0 = <&pinctrl_leds>; |
| G | 156 | + status = "okay"; |
| be049f | 157 | + |
| W | 158 | + sysled { |
| 159 | + label = "sysled"; | |
| 160 | + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; | |
| 161 | + default-state = "on"; | |
| 2c3d96 | 162 | + }; |
| G | 163 | + }; |
| be049f | 164 | +}; |
| W | 165 | + |
| 166 | +/*+------------------------+ | |
| 167 | + | power key & reset | | |
| 168 | + +------------------------+*/ | |
| 169 | + | |
| 170 | +&snvs_pwrkey { | |
| 171 | + status = "okay"; | |
| 172 | +}; | |
| 173 | + | |
| 174 | +&wdog1 { | |
| 175 | + pinctrl-names = "default"; | |
| 176 | + pinctrl-0 = <&pinctrl_wdog>; | |
| 177 | + fsl,ext-reset-output; | |
| 178 | + status = "okay"; | |
| 179 | +}; | |
| 180 | + | |
| 181 | +/*+------------------------+ | |
| 182 | + | console usart2 | | |
| 183 | + +------------------------+*/ | |
| 184 | +&uart2 { | |
| 185 | + pinctrl-names = "default"; | |
| 186 | + pinctrl-0 = <&pinctrl_uart2>; | |
| 187 | + status = "okay"; | |
| 188 | +}; | |
| 189 | + | |
| 190 | +/*+------------------------+ | |
| 191 | + | 8GB eMMC on SD3 | | |
| 192 | + +------------------------+*/ | |
| 193 | + | |
| 194 | +/* KLM8G1GETF-B041 8GB eMMC */ | |
| 195 | +&usdhc3 { | |
| 196 | + pinctrl-names = "default", "state_100mhz", "state_200mhz"; | |
| 197 | + pinctrl-0 = <&pinctrl_usdhc3>; | |
| 198 | + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; | |
| 199 | + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; | |
| 200 | + bus-width = <8>; | |
| 201 | + non-removable; | |
| 202 | + status = "okay"; | |
| 203 | +}; | |
| 204 | + | |
| 205 | +/*+------------------------+ | |
| 206 | + | TF Card on SD2 | | |
| 207 | + +------------------------+*/ | |
| 208 | + | |
| 209 | +&usdhc2 { | |
| 2c3d96 | 210 | + pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| G | 211 | + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| 212 | + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; | |
| 213 | + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; | |
| 214 | + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; | |
| 215 | + bus-width = <4>; | |
| 216 | + no-1-8-v; | |
| 217 | + status = "okay"; | |
| be049f | 218 | +}; |
| W | 219 | + |
| 220 | +/*+------------------------+ | |
| 221 | + | Typec USB for download | | |
| 222 | + +------------------------+*/ | |
| 223 | + | |
| 224 | +&usb3_phy0 { | |
| 2c3d96 | 225 | + fsl,phy-tx-vref-tune = <6>; |
| G | 226 | + fsl,phy-tx-rise-tune = <0>; |
| 227 | + fsl,phy-tx-preemp-amp-tune = <3>; | |
| 228 | + fsl,phy-comp-dis-tune = <7>; | |
| 229 | + fsl,pcs-tx-deemph-3p5db = <0x21>; | |
| 230 | + fsl,phy-pcs-tx-swing-full = <0x7f>; | |
| 231 | + status = "okay"; | |
| be049f | 232 | +}; |
| W | 233 | + |
| 234 | +&usb3_0 { | |
| 2c3d96 | 235 | + status = "okay"; |
| be049f | 236 | +}; |
| W | 237 | + |
| 238 | +&usb_dwc3_0 { | |
| 2c3d96 | 239 | + dr_mode = "peripheral"; |
| G | 240 | + hnp-disable; |
| 241 | + srp-disable; | |
| 242 | + adp-disable; | |
| 243 | + status = "okay"; | |
| be049f | 244 | +}; |
| W | 245 | + |
| 246 | +/*+------------------------+ | |
| 247 | + | 2xUSB Host on USB Hub | | |
| 248 | + +------------------------+*/ | |
| 249 | + | |
| 250 | +/* Renesas USB 3.0 Hub uPD720210 */ | |
| 251 | +&usb3_phy1 { | |
| 2c3d96 | 252 | + fsl,phy-tx-preemp-amp-tune = <2>; |
| G | 253 | + status = "okay"; |
| be049f | 254 | +}; |
| W | 255 | + |
| 256 | +&usb3_1 { | |
| 2c3d96 | 257 | + status = "okay"; |
| be049f | 258 | +}; |
| W | 259 | + |
| 260 | +&usb_dwc3_1 { | |
| 2c3d96 | 261 | + dr_mode = "host"; |
| G | 262 | + status = "okay"; |
| be049f | 263 | +}; |
| W | 264 | + |
| 265 | +/*+------------------------+ | |
| 266 | + | Ethernet | | |
| 267 | + +------------------------+*/ | |
| 268 | + | |
| 2c3d96 | 269 | +/* First 1000Mbps Ethernet For TSN on ENET */ |
| be049f | 270 | +&eqos { |
| W | 271 | + pinctrl-names = "default"; |
| 272 | + pinctrl-0 = <&pinctrl_eqos>; | |
| 273 | + phy-mode = "rgmii-id"; | |
| 274 | + phy-handle = <ðphy0>; | |
| 275 | + status = "okay"; | |
| 276 | + | |
| 277 | + mdio { | |
| 278 | + compatible = "snps,dwmac-mdio"; | |
| 2c3d96 | 279 | + #address-cells = <1>; |
| G | 280 | + #size-cells = <0>; |
| d3809d | 281 | + clock-frequency = <5000000>; |
| be049f | 282 | + |
| 2c3d96 | 283 | + ethphy0: ethernet-phy@0 { /* YT8521SH-CA */ |
| be049f | 284 | + compatible = "ethernet-phy-ieee802.3-c22"; |
| 2c3d96 | 285 | + reg = <0>; |
| be049f | 286 | + eee-broken-1000t; |
| 2c3d96 | 287 | + }; |
| G | 288 | + }; |
| be049f | 289 | +}; |
| W | 290 | + |
| e14437 | 291 | +/* Second 1000Mbps Ethernet on ENET1, test okay */ |
| be049f | 292 | +&fec { |
| W | 293 | + pinctrl-names = "default"; |
| 294 | + pinctrl-0 = <&pinctrl_fec>; | |
| 295 | + phy-mode = "rgmii-id"; | |
| 296 | + phy-handle = <ðphy1>; | |
| 297 | + fsl,magic-packet; | |
| 298 | + status = "okay"; | |
| 299 | + | |
| 300 | + mdio { | |
| 2c3d96 | 301 | + #address-cells = <1>; |
| G | 302 | + #size-cells = <0>; |
| d3809d | 303 | + clock-frequency = <5000000>; |
| be049f | 304 | + |
| 2c3d96 | 305 | + ethphy1: ethernet-phy@0 { /* YT8521SH-CA */ |
| be049f | 306 | + compatible = "ethernet-phy-ieee802.3-c22"; |
| 2c3d96 | 307 | + reg = <0>; |
| be049f | 308 | + eee-broken-1000t; |
| 2c3d96 | 309 | + }; |
| G | 310 | + }; |
| be049f | 311 | +}; |
| W | 312 | + |
| 313 | +/*+------------------------+ | |
| 314 | + | PCA9450CHN PMIC | | |
| 315 | + +------------------------+*/ | |
| 316 | + | |
| 317 | +&i2c1 { | |
| 2c3d96 | 318 | + clock-frequency = <400000>; |
| G | 319 | + pinctrl-names = "default", "gpio"; |
| 320 | + pinctrl-0 = <&pinctrl_i2c1>; | |
| 321 | + pinctrl-1 = <&pinctrl_i2c1_gpio>; | |
| 322 | + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; | |
| 323 | + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; | |
| 324 | + status = "okay"; | |
| be049f | 325 | + |
| 2c3d96 | 326 | + pmic@25 { |
| G | 327 | + compatible = "nxp,pca9450c"; |
| 328 | + reg = <0x25>; | |
| 329 | + pinctrl-names = "default"; | |
| 330 | + pinctrl-0 = <&pinctrl_pmic>; | |
| 331 | + interrupt-parent = <&gpio1>; | |
| 332 | + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; | |
| be049f | 333 | + |
| 2c3d96 | 334 | + regulators { |
| G | 335 | + buck1: BUCK1 { |
| 336 | + regulator-name = "BUCK1"; | |
| 337 | + regulator-min-microvolt = <600000>; | |
| 338 | + regulator-max-microvolt = <2187500>; | |
| 339 | + regulator-boot-on; | |
| 340 | + regulator-always-on; | |
| 341 | + regulator-ramp-delay = <3125>; | |
| 342 | + }; | |
| be049f | 343 | + |
| 2c3d96 | 344 | + buck2: BUCK2 { |
| G | 345 | + regulator-name = "BUCK2"; |
| 346 | + regulator-min-microvolt = <600000>; | |
| 347 | + regulator-max-microvolt = <2187500>; | |
| 348 | + regulator-boot-on; | |
| 349 | + regulator-always-on; | |
| 350 | + regulator-ramp-delay = <3125>; | |
| 351 | + nxp,dvs-run-voltage = <950000>; | |
| 352 | + nxp,dvs-standby-voltage = <850000>; | |
| 353 | + }; | |
| be049f | 354 | + |
| 2c3d96 | 355 | + buck4: BUCK4{ |
| G | 356 | + regulator-name = "BUCK4"; |
| 357 | + regulator-min-microvolt = <600000>; | |
| 358 | + regulator-max-microvolt = <3400000>; | |
| 359 | + regulator-boot-on; | |
| 360 | + regulator-always-on; | |
| 361 | + }; | |
| be049f | 362 | + |
| 2c3d96 | 363 | + buck5: BUCK5{ |
| G | 364 | + regulator-name = "BUCK5"; |
| 365 | + regulator-min-microvolt = <600000>; | |
| 366 | + regulator-max-microvolt = <3400000>; | |
| 367 | + regulator-boot-on; | |
| 368 | + regulator-always-on; | |
| 369 | + }; | |
| be049f | 370 | + |
| 2c3d96 | 371 | + buck6: BUCK6 { |
| G | 372 | + regulator-name = "BUCK6"; |
| 373 | + regulator-min-microvolt = <600000>; | |
| 374 | + regulator-max-microvolt = <3400000>; | |
| 375 | + regulator-boot-on; | |
| 376 | + regulator-always-on; | |
| 377 | + }; | |
| be049f | 378 | + |
| 2c3d96 | 379 | + ldo1: LDO1 { |
| G | 380 | + regulator-name = "LDO1"; |
| 381 | + regulator-min-microvolt = <1600000>; | |
| 382 | + regulator-max-microvolt = <3300000>; | |
| 383 | + regulator-boot-on; | |
| 384 | + regulator-always-on; | |
| 385 | + }; | |
| be049f | 386 | + |
| 2c3d96 | 387 | + ldo2: LDO2 { |
| G | 388 | + regulator-name = "LDO2"; |
| 389 | + regulator-min-microvolt = <800000>; | |
| 390 | + regulator-max-microvolt = <1150000>; | |
| 391 | + regulator-boot-on; | |
| 392 | + regulator-always-on; | |
| 393 | + }; | |
| be049f | 394 | + |
| 2c3d96 | 395 | + ldo3: LDO3 { |
| G | 396 | + regulator-name = "LDO3"; |
| 397 | + regulator-min-microvolt = <800000>; | |
| 398 | + regulator-max-microvolt = <3300000>; | |
| 399 | + regulator-boot-on; | |
| 400 | + regulator-always-on; | |
| 401 | + }; | |
| be049f | 402 | + |
| 2c3d96 | 403 | + ldo4: LDO4 { |
| G | 404 | + regulator-name = "LDO4"; |
| 405 | + regulator-min-microvolt = <800000>; | |
| 406 | + regulator-max-microvolt = <3300000>; | |
| 407 | + regulator-boot-on; | |
| 408 | + regulator-always-on; | |
| 409 | + }; | |
| be049f | 410 | + |
| 2c3d96 | 411 | + ldo5: LDO5 { |
| G | 412 | + regulator-name = "LDO5"; |
| 413 | + regulator-min-microvolt = <1800000>; | |
| 414 | + regulator-max-microvolt = <3300000>; | |
| 415 | + regulator-boot-on; | |
| 416 | + regulator-always-on; | |
| 417 | + }; | |
| 418 | + }; | |
| 419 | + }; | |
| be049f | 420 | +}; |
| W | 421 | + |
| 422 | +&iomuxc { | |
| 2c3d96 | 423 | + pinctrl-names = "default"; |
| be049f | 424 | + |
| 2c3d96 | 425 | + pinctrl_leds: ledsgrp { |
| G | 426 | + fsl,pins = < |
| 427 | + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 | |
| 428 | + >; | |
| 429 | + }; | |
| be049f | 430 | + |
| 2c3d96 | 431 | + pinctrl_wdog: wdoggrp { |
| G | 432 | + fsl,pins = < |
| 433 | + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 | |
| 434 | + >; | |
| 435 | + }; | |
| be049f | 436 | + |
| 2c3d96 | 437 | + pinctrl_uart2: uart2grp { |
| G | 438 | + fsl,pins = < |
| 439 | + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 | |
| 440 | + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 | |
| 441 | + >; | |
| 442 | + }; | |
| 84751c | 443 | + |
| 2c3d96 | 444 | + pinctrl_i2c1: i2c1grp { |
| G | 445 | + fsl,pins = < |
| 446 | + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 | |
| 447 | + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 | |
| 448 | + >; | |
| 449 | + }; | |
| be049f | 450 | + |
| 2c3d96 | 451 | + pinctrl_i2c1_gpio: i2c1grp-gpio { |
| G | 452 | + fsl,pins = < |
| 453 | + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3 | |
| 454 | + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3 | |
| 455 | + >; | |
| 456 | + }; | |
| be049f | 457 | + |
| 2c3d96 | 458 | + pinctrl_pmic: pmicirq { |
| G | 459 | + fsl,pins = < |
| 460 | + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 | |
| 461 | + >; | |
| 462 | + }; | |
| be049f | 463 | + |
| 2c3d96 | 464 | + pinctrl_usdhc2_gpio: usdhc2grp-gpio { |
| G | 465 | + fsl,pins = < |
| 466 | + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 | |
| 467 | + >; | |
| 468 | + }; | |
| be049f | 469 | + |
| 2c3d96 | 470 | + pinctrl_usdhc2: usdhc2grp { |
| G | 471 | + fsl,pins = < |
| 472 | + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 | |
| 473 | + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 | |
| 474 | + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 | |
| 475 | + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 | |
| 476 | + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 | |
| 477 | + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 | |
| 478 | + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 | |
| 479 | + >; | |
| 480 | + }; | |
| be049f | 481 | + |
| 2c3d96 | 482 | + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { |
| G | 483 | + fsl,pins = < |
| 484 | + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 | |
| 485 | + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 | |
| 486 | + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 | |
| 487 | + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 | |
| 488 | + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 | |
| 489 | + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 | |
| 490 | + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 | |
| 491 | + >; | |
| 492 | + }; | |
| be049f | 493 | + |
| 2c3d96 | 494 | + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { |
| G | 495 | + fsl,pins = < |
| 496 | + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 | |
| 497 | + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 | |
| 498 | + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 | |
| 499 | + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 | |
| 500 | + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 | |
| 501 | + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 | |
| 502 | + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 | |
| 503 | + >; | |
| 504 | + }; | |
| be049f | 505 | + |
| 2c3d96 | 506 | + pinctrl_usdhc3: usdhc3grp { |
| G | 507 | + fsl,pins = < |
| 508 | + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 | |
| 509 | + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 | |
| 510 | + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 | |
| 511 | + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 | |
| 512 | + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 | |
| 513 | + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 | |
| 514 | + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 | |
| 515 | + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 | |
| 516 | + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 | |
| 517 | + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 | |
| 518 | + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 | |
| 519 | + >; | |
| 520 | + }; | |
| be049f | 521 | + |
| 2c3d96 | 522 | + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { |
| G | 523 | + fsl,pins = < |
| 524 | + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 | |
| 525 | + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 | |
| 526 | + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 | |
| 527 | + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 | |
| 528 | + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 | |
| 529 | + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 | |
| 530 | + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 | |
| 531 | + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 | |
| 532 | + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 | |
| 533 | + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 | |
| 534 | + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 | |
| 535 | + >; | |
| 536 | + }; | |
| be049f | 537 | + |
| 2c3d96 | 538 | + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { |
| G | 539 | + fsl,pins = < |
| 540 | + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 | |
| 541 | + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 | |
| 542 | + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 | |
| 543 | + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 | |
| 544 | + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 | |
| 545 | + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 | |
| 546 | + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 | |
| 547 | + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 | |
| 548 | + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 | |
| 549 | + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 | |
| 550 | + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 | |
| 551 | + >; | |
| 552 | + }; | |
| be049f | 553 | + |
| 2c3d96 | 554 | + pinctrl_eqos: eqosgrp { |
| G | 555 | + fsl,pins = < |
| 556 | + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 | |
| 557 | + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 | |
| 558 | + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 | |
| 559 | + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 | |
| 560 | + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 | |
| 561 | + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 | |
| 562 | + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 | |
| 563 | + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 | |
| 564 | + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 | |
| 565 | + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 | |
| 566 | + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 | |
| 567 | + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 | |
| 568 | + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 | |
| 569 | + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 | |
| 570 | + >; | |
| 571 | + }; | |
| be049f | 572 | + |
| 2c3d96 | 573 | + pinctrl_fec: fecgrp { |
| G | 574 | + fsl,pins = < |
| 575 | + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 | |
| 576 | + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 | |
| 577 | + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 | |
| 578 | + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 | |
| 579 | + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 | |
| 580 | + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 | |
| 581 | + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 | |
| 582 | + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 | |
| 583 | + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 | |
| 584 | + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 | |
| 585 | + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 | |
| 586 | + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 | |
| 587 | + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 | |
| 588 | + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 | |
| 589 | + >; | |
| 590 | + }; | |
| be049f | 591 | +}; |
| W | 592 | diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig |
| 84751c | 593 | index b1240279..e9bcd610 100644 |
| be049f | 594 | --- a/arch/arm/mach-imx/imx8m/Kconfig |
| W | 595 | +++ b/arch/arm/mach-imx/imx8m/Kconfig |
| 84751c | 596 | @@ -318,6 +318,12 @@ config TARGET_IMX8MP_EVK |
| be049f | 597 | select ARCH_MISC_INIT |
| W | 598 | select SPL_CRYPTO if SPL |
| 599 | ||
| 600 | +config TARGET_IGKBOARD_IMX8MP | |
| 601 | + bool "LingYun IoT Gateway Kits Board based on i.MX8M Plus" | |
| 602 | + select IMX8MP | |
| 603 | + select SUPPORT_SPL | |
| 604 | + select IMX8M_LPDDR4 | |
| 605 | + | |
| 606 | config TARGET_IMX8MP_VENICE | |
| 607 | bool "Support Gateworks Venice iMX8M Plus module" | |
| 608 | select BINMAN | |
| 84751c | 609 | @@ -481,5 +487,6 @@ source "board/technexion/pico-imx8mq/Kconfig" |
| be049f | 610 | source "board/variscite/imx8mn_var_som/Kconfig" |
| W | 611 | source "board/toradex/verdin-imx8mm/Kconfig" |
| 612 | source "board/toradex/verdin-imx8mp/Kconfig" | |
| 613 | +source "board/lingyun/igkboard-imx8mp/Kconfig" | |
| 614 | ||
| 615 | endif | |
| 616 | diff --git a/board/lingyun/igkboard-imx8mp/Kconfig b/board/lingyun/igkboard-imx8mp/Kconfig | |
| 617 | new file mode 100644 | |
| 618 | index 00000000..50ec59bc | |
| 619 | --- /dev/null | |
| 620 | +++ b/board/lingyun/igkboard-imx8mp/Kconfig | |
| 621 | @@ -0,0 +1,15 @@ | |
| 622 | +if TARGET_IGKBOARD_IMX8MP | |
| 623 | + | |
| 624 | +config SYS_BOARD | |
| 625 | + default "igkboard-imx8mp" | |
| 626 | + | |
| 627 | +config SYS_VENDOR | |
| 628 | + default "lingyun" | |
| 629 | + | |
| 630 | +config SYS_CONFIG_NAME | |
| 631 | + default "igkboard-imx8mp" | |
| 632 | + | |
| 633 | +config IMX_CONFIG | |
| 634 | + default "board/lingyun/igkboard-imx8mp/imximage-8mp-lpddr4.cfg" | |
| 635 | + | |
| 636 | +endif | |
| 637 | diff --git a/board/lingyun/igkboard-imx8mp/MAINTAINERS b/board/lingyun/igkboard-imx8mp/MAINTAINERS | |
| 638 | new file mode 100644 | |
| 639 | index 00000000..76066977 | |
| 640 | --- /dev/null | |
| 641 | +++ b/board/lingyun/igkboard-imx8mp/MAINTAINERS | |
| 642 | @@ -0,0 +1,7 @@ | |
| 643 | +IGKBoard i.MX8MP | |
| 644 | +M: Wenxue Guo <guowenxue@gmail.com> | |
| 645 | +S: Maintained | |
| 646 | +B: board/freescale/imx8mp_evk/ | |
| 647 | +F: board/lingyun/igkboard-imx8mp/ | |
| 648 | +F: include/configs/igkboard-imx8mp.h | |
| 649 | +F: configs/igkboard-imx8mp_defconfig | |
| 650 | diff --git a/board/lingyun/igkboard-imx8mp/Makefile b/board/lingyun/igkboard-imx8mp/Makefile | |
| 651 | new file mode 100644 | |
| 652 | index 00000000..05c561ed | |
| 653 | --- /dev/null | |
| 654 | +++ b/board/lingyun/igkboard-imx8mp/Makefile | |
| 655 | @@ -0,0 +1,13 @@ | |
| 656 | +# | |
| 657 | +# Copyright 2019 NXP | |
| 658 | +# | |
| 659 | +# SPDX-License-Identifier: GPL-2.0+ | |
| 660 | +# | |
| 661 | + | |
| 662 | +obj-y += igkboard-imx8mp.o | |
| 663 | +obj-y += ../../freescale/common/mmc.o | |
| 664 | + | |
| 665 | +ifdef CONFIG_SPL_BUILD | |
| 666 | +obj-y += spl.o | |
| 667 | +obj-y += lpddr4_timing.o | |
| 668 | +endif | |
| 669 | diff --git a/board/lingyun/igkboard-imx8mp/igkboard-imx8mp.c b/board/lingyun/igkboard-imx8mp/igkboard-imx8mp.c | |
| 670 | new file mode 100644 | |
| 671 | index 00000000..189ab3b1 | |
| 672 | --- /dev/null | |
| 673 | +++ b/board/lingyun/igkboard-imx8mp/igkboard-imx8mp.c | |
| 674 | @@ -0,0 +1,513 @@ | |
| 675 | +// SPDX-License-Identifier: GPL-2.0+ | |
| 676 | +/* | |
| 677 | + * Copyright 2019 NXP | |
| 678 | + */ | |
| 679 | + | |
| 680 | +#include <common.h> | |
| 681 | +#include <efi_loader.h> | |
| 682 | +#include <env.h> | |
| 683 | +#include <errno.h> | |
| 684 | +#include <init.h> | |
| 685 | +#include <miiphy.h> | |
| 686 | +#include <netdev.h> | |
| 687 | +#include <linux/delay.h> | |
| 688 | +#include <asm/global_data.h> | |
| 689 | +#include <asm/io.h> | |
| 690 | +#include <asm/mach-imx/iomux-v3.h> | |
| 691 | +#include <asm-generic/gpio.h> | |
| 692 | +#include <asm/arch/imx8mp_pins.h> | |
| 693 | +#include <asm/arch/clock.h> | |
| 694 | +#include <asm/arch/sys_proto.h> | |
| 695 | +#include <asm/mach-imx/gpio.h> | |
| 696 | +#include <asm/mach-imx/mxc_i2c.h> | |
| 697 | +#include <spl.h> | |
| 698 | +#include <asm/mach-imx/dma.h> | |
| 699 | +#include <power/pmic.h> | |
| 700 | +#include "../../freescale/common/tcpc.h" | |
| 701 | +#include <usb.h> | |
| 702 | +#include <dwc3-uboot.h> | |
| 703 | +#include <mmc.h> | |
| 704 | + | |
| 705 | +DECLARE_GLOBAL_DATA_PTR; | |
| 706 | + | |
| 707 | +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) | |
| 708 | +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) | |
| 709 | + | |
| 710 | +static iomux_v3_cfg_t const uart_pads[] = { | |
| 711 | + MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | |
| 712 | + MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | |
| 713 | +}; | |
| 714 | + | |
| 715 | +static iomux_v3_cfg_t const wdog_pads[] = { | |
| 716 | + MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), | |
| 717 | +}; | |
| 718 | + | |
| 719 | +#ifdef CONFIG_NAND_MXS | |
| 720 | + | |
| 721 | +static void setup_gpmi_nand(void) | |
| 722 | +{ | |
| 723 | + init_nand_clk(); | |
| 724 | +} | |
| 725 | +#endif | |
| 726 | + | |
| 727 | +#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT) | |
| 728 | +struct efi_fw_image fw_images[] = { | |
| 729 | + { | |
| 730 | + .image_type_id = IMX_BOOT_IMAGE_GUID, | |
| 731 | + .fw_name = u"IMX8MP-EVK-RAW", | |
| 732 | + .image_index = 1, | |
| 733 | + }, | |
| 734 | +}; | |
| 735 | + | |
| 736 | +struct efi_capsule_update_info update_info = { | |
| 737 | + .dfu_string = "mmc 2=flash-bin raw 0 0x2000 mmcpart 1", | |
| 738 | + .images = fw_images, | |
| 739 | +}; | |
| 740 | + | |
| 741 | +u8 num_image_type_guids = ARRAY_SIZE(fw_images); | |
| 742 | +#endif /* EFI_HAVE_CAPSULE_SUPPORT */ | |
| 743 | + | |
| 744 | +int board_early_init_f(void) | |
| 745 | +{ | |
| 746 | + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; | |
| 747 | + | |
| 748 | + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); | |
| 749 | + | |
| 750 | + set_wdog_reset(wdog); | |
| 751 | + | |
| 752 | + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); | |
| 753 | + | |
| 754 | + init_uart_clk(1); | |
| 755 | + | |
| 756 | + return 0; | |
| 757 | +} | |
| 758 | + | |
| 759 | +#ifdef CONFIG_OF_BOARD_SETUP | |
| 760 | +int ft_board_setup(void *blob, struct bd_info *bd) | |
| 761 | +{ | |
| 762 | +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC | |
| 763 | +#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK | |
| 764 | + int rc; | |
| 765 | + phys_addr_t ecc_start = 0x120000000; | |
| 766 | + size_t ecc_size = 0x20000000; | |
| 767 | + | |
| 768 | + rc = add_res_mem_dt_node(blob, "ecc", ecc_start, ecc_size); | |
| 769 | + if (rc < 0) { | |
| 770 | + printf("Could not create ecc reserved-memory node.\n"); | |
| 771 | + return rc; | |
| 772 | + } | |
| 773 | +#else | |
| 774 | + int rc; | |
| 775 | + phys_addr_t ecc0_start = 0xb0000000; | |
| 776 | + phys_addr_t ecc1_start = 0x130000000; | |
| 777 | + phys_addr_t ecc2_start = 0x1b0000000; | |
| 778 | + size_t ecc_size = 0x10000000; | |
| 779 | + | |
| 780 | + rc = add_res_mem_dt_node(blob, "ecc", ecc0_start, ecc_size); | |
| 781 | + if (rc < 0) { | |
| 782 | + printf("Could not create ecc0 reserved-memory node.\n"); | |
| 783 | + return rc; | |
| 784 | + } | |
| 785 | + | |
| 786 | + rc = add_res_mem_dt_node(blob, "ecc", ecc1_start, ecc_size); | |
| 787 | + if (rc < 0) { | |
| 788 | + printf("Could not create ecc1 reserved-memory node.\n"); | |
| 789 | + return rc; | |
| 790 | + } | |
| 791 | + | |
| 792 | + rc = add_res_mem_dt_node(blob, "ecc", ecc2_start, ecc_size); | |
| 793 | + if (rc < 0) { | |
| 794 | + printf("Could not create ecc2 reserved-memory node.\n"); | |
| 795 | + return rc; | |
| 796 | + } | |
| 797 | +#endif | |
| 798 | +#endif | |
| 799 | + | |
| 800 | + return 0; | |
| 801 | +} | |
| 802 | +#endif | |
| 803 | + | |
| 804 | +#ifdef CONFIG_USB_TCPC | |
| 805 | +struct tcpc_port port1; | |
| 806 | +struct tcpc_port port2; | |
| 807 | + | |
| 808 | +static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr) | |
| 809 | +{ | |
| 810 | + struct udevice *bus; | |
| 811 | + struct udevice *i2c_dev = NULL; | |
| 812 | + int ret; | |
| 813 | + uint8_t valb; | |
| 814 | + | |
| 815 | + ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus); | |
| 816 | + if (ret) { | |
| 817 | + printf("%s: Can't find bus\n", __func__); | |
| 818 | + return -EINVAL; | |
| 819 | + } | |
| 820 | + | |
| 821 | + ret = dm_i2c_probe(bus, addr, 0, &i2c_dev); | |
| 822 | + if (ret) { | |
| 823 | + printf("%s: Can't find device id=0x%x\n", | |
| 824 | + __func__, addr); | |
| 825 | + return -ENODEV; | |
| 826 | + } | |
| 827 | + | |
| 828 | + ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1); | |
| 829 | + if (ret) { | |
| 830 | + printf("%s dm_i2c_read failed, err %d\n", __func__, ret); | |
| 831 | + return -EIO; | |
| 832 | + } | |
| 833 | + valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */ | |
| 834 | + ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1); | |
| 835 | + if (ret) { | |
| 836 | + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); | |
| 837 | + return -EIO; | |
| 838 | + } | |
| 839 | + | |
| 840 | + /* Set OVP threshold to 23V */ | |
| 841 | + valb = 0x6; | |
| 842 | + ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1); | |
| 843 | + if (ret) { | |
| 844 | + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); | |
| 845 | + return -EIO; | |
| 846 | + } | |
| 847 | + | |
| 848 | + return 0; | |
| 849 | +} | |
| 850 | + | |
| 851 | +int pd_switch_snk_enable(struct tcpc_port *port) | |
| 852 | +{ | |
| 853 | + if (port == &port1) { | |
| 854 | + debug("Setup pd switch on port 1\n"); | |
| 855 | + return setup_pd_switch(1, 0x72); | |
| 856 | + } else | |
| 857 | + return -EINVAL; | |
| 858 | +} | |
| 859 | + | |
| 860 | +/* Port2 is the power supply, port 1 does not support power */ | |
| 861 | +struct tcpc_port_config port1_config = { | |
| 862 | + .i2c_bus = 1, /*i2c2*/ | |
| 863 | + .addr = 0x50, | |
| 864 | + .port_type = TYPEC_PORT_UFP, | |
| 865 | + .max_snk_mv = 20000, | |
| 866 | + .max_snk_ma = 3000, | |
| 867 | + .max_snk_mw = 45000, | |
| 868 | + .op_snk_mv = 15000, | |
| 869 | + .switch_setup_func = &pd_switch_snk_enable, | |
| 870 | + .disable_pd = true, | |
| 871 | +}; | |
| 872 | + | |
| 873 | +struct tcpc_port_config port2_config = { | |
| 874 | + .i2c_bus = 2, /*i2c3*/ | |
| 875 | + .addr = 0x50, | |
| 876 | + .port_type = TYPEC_PORT_UFP, | |
| 877 | + .max_snk_mv = 20000, | |
| 878 | + .max_snk_ma = 3000, | |
| 879 | + .max_snk_mw = 45000, | |
| 880 | + .op_snk_mv = 15000, | |
| 881 | +}; | |
| 882 | + | |
| 883 | +#define USB_TYPEC_SEL IMX_GPIO_NR(4, 20) | |
| 884 | +#define USB_TYPEC_EN IMX_GPIO_NR(2, 20) | |
| 885 | + | |
| 886 | +static iomux_v3_cfg_t ss_mux_gpio[] = { | |
| 887 | + MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
| 888 | + MX8MP_PAD_SD2_WP__GPIO2_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
| 889 | +}; | |
| 890 | + | |
| 891 | +void ss_mux_select(enum typec_cc_polarity pol) | |
| 892 | +{ | |
| 893 | + if (pol == TYPEC_POLARITY_CC1) | |
| 894 | + gpio_direction_output(USB_TYPEC_SEL, 0); | |
| 895 | + else | |
| 896 | + gpio_direction_output(USB_TYPEC_SEL, 1); | |
| 897 | +} | |
| 898 | + | |
| 899 | +static int setup_typec(void) | |
| 900 | +{ | |
| 901 | + int ret; | |
| 902 | + struct gpio_desc per_12v_desc; | |
| 903 | + | |
| 904 | + debug("tcpc_init port 2\n"); | |
| 905 | + ret = tcpc_init(&port2, port2_config, NULL); | |
| 906 | + if (ret) { | |
| 907 | + printf("%s: tcpc port2 init failed, err=%d\n", | |
| 908 | + __func__, ret); | |
| 909 | + } else if (tcpc_pd_sink_check_charging(&port2)) { | |
| 910 | + printf("Power supply on USB2\n"); | |
| 911 | + | |
| 912 | + /* Enable PER 12V, any check before it? */ | |
| 913 | + ret = dm_gpio_lookup_name("gpio@20_1", &per_12v_desc); | |
| 914 | + if (ret) { | |
| 915 | + printf("%s lookup gpio@20_1 failed ret = %d\n", __func__, ret); | |
| 916 | + return -ENODEV; | |
| 917 | + } | |
| 918 | + | |
| 919 | + ret = dm_gpio_request(&per_12v_desc, "per_12v_en"); | |
| 920 | + if (ret) { | |
| 921 | + printf("%s request per_12v failed ret = %d\n", __func__, ret); | |
| 922 | + return -EIO; | |
| 923 | + } | |
| 924 | + | |
| 925 | + /* Enable PER 12V regulator */ | |
| 926 | + dm_gpio_set_dir_flags(&per_12v_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); | |
| 927 | + } | |
| 928 | + | |
| 929 | + debug("tcpc_init port 1\n"); | |
| 930 | + imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio)); | |
| 931 | + gpio_request(USB_TYPEC_SEL, "typec_sel"); | |
| 932 | + gpio_request(USB_TYPEC_EN, "typec_en"); | |
| 933 | + gpio_direction_output(USB_TYPEC_EN, 0); | |
| 934 | + | |
| 935 | + ret = tcpc_init(&port1, port1_config, &ss_mux_select); | |
| 936 | + if (ret) { | |
| 937 | + printf("%s: tcpc port1 init failed, err=%d\n", | |
| 938 | + __func__, ret); | |
| 939 | + } else { | |
| 940 | + return ret; | |
| 941 | + } | |
| 942 | + | |
| 943 | + return ret; | |
| 944 | +} | |
| 945 | +#endif | |
| 946 | + | |
| 947 | +#ifdef CONFIG_USB_DWC3 | |
| 948 | + | |
| 949 | +#define USB_PHY_CTRL0 0xF0040 | |
| 950 | +#define USB_PHY_CTRL0_REF_SSP_EN BIT(2) | |
| 951 | + | |
| 952 | +#define USB_PHY_CTRL1 0xF0044 | |
| 953 | +#define USB_PHY_CTRL1_RESET BIT(0) | |
| 954 | +#define USB_PHY_CTRL1_COMMONONN BIT(1) | |
| 955 | +#define USB_PHY_CTRL1_ATERESET BIT(3) | |
| 956 | +#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) | |
| 957 | +#define USB_PHY_CTRL1_VDATDETENB0 BIT(20) | |
| 958 | + | |
| 959 | +#define USB_PHY_CTRL2 0xF0048 | |
| 960 | +#define USB_PHY_CTRL2_TXENABLEN0 BIT(8) | |
| 961 | + | |
| 962 | +#define USB_PHY_CTRL6 0xF0058 | |
| 963 | + | |
| 964 | +#define HSIO_GPR_BASE (0x32F10000U) | |
| 965 | +#define HSIO_GPR_REG_0 (HSIO_GPR_BASE) | |
| 966 | +#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT (1) | |
| 967 | +#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN (0x1U << HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT) | |
| 968 | + | |
| 969 | + | |
| 970 | +static struct dwc3_device dwc3_device_data = { | |
| 971 | +#ifdef CONFIG_SPL_BUILD | |
| 972 | + .maximum_speed = USB_SPEED_HIGH, | |
| 973 | +#else | |
| 974 | + .maximum_speed = USB_SPEED_SUPER, | |
| 975 | +#endif | |
| 976 | + .base = USB1_BASE_ADDR, | |
| 977 | + .dr_mode = USB_DR_MODE_PERIPHERAL, | |
| 978 | + .index = 0, | |
| 979 | + .power_down_scale = 2, | |
| 980 | +}; | |
| 981 | + | |
| 982 | +int usb_gadget_handle_interrupts(int index) | |
| 983 | +{ | |
| 984 | + dwc3_uboot_handle_interrupt(index); | |
| 985 | + return 0; | |
| 986 | +} | |
| 987 | + | |
| 988 | +static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) | |
| 989 | +{ | |
| 990 | + u32 RegData; | |
| 991 | + | |
| 992 | + /* enable usb clock via hsio gpr */ | |
| 993 | + RegData = readl(HSIO_GPR_REG_0); | |
| 994 | + RegData |= HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN; | |
| 995 | + writel(RegData, HSIO_GPR_REG_0); | |
| 996 | + | |
| 997 | + /* USB3.0 PHY signal fsel for 100M ref */ | |
| 998 | + RegData = readl(dwc3->base + USB_PHY_CTRL0); | |
| 999 | + RegData = (RegData & 0xfffff81f) | (0x2a<<5); | |
| 1000 | + writel(RegData, dwc3->base + USB_PHY_CTRL0); | |
| 1001 | + | |
| 1002 | + RegData = readl(dwc3->base + USB_PHY_CTRL6); | |
| 1003 | + RegData &=~0x1; | |
| 1004 | + writel(RegData, dwc3->base + USB_PHY_CTRL6); | |
| 1005 | + | |
| 1006 | + RegData = readl(dwc3->base + USB_PHY_CTRL1); | |
| 1007 | + RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | | |
| 1008 | + USB_PHY_CTRL1_COMMONONN); | |
| 1009 | + RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; | |
| 1010 | + writel(RegData, dwc3->base + USB_PHY_CTRL1); | |
| 1011 | + | |
| 1012 | + RegData = readl(dwc3->base + USB_PHY_CTRL0); | |
| 1013 | + RegData |= USB_PHY_CTRL0_REF_SSP_EN; | |
| 1014 | + writel(RegData, dwc3->base + USB_PHY_CTRL0); | |
| 1015 | + | |
| 1016 | + RegData = readl(dwc3->base + USB_PHY_CTRL2); | |
| 1017 | + RegData |= USB_PHY_CTRL2_TXENABLEN0; | |
| 1018 | + writel(RegData, dwc3->base + USB_PHY_CTRL2); | |
| 1019 | + | |
| 1020 | + RegData = readl(dwc3->base + USB_PHY_CTRL1); | |
| 1021 | + RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); | |
| 1022 | + writel(RegData, dwc3->base + USB_PHY_CTRL1); | |
| 1023 | +} | |
| 1024 | +#endif | |
| 1025 | + | |
| 1026 | +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) | |
| 1027 | +#define USB2_PWR_EN IMX_GPIO_NR(1, 14) | |
| 1028 | +int board_usb_init(int index, enum usb_init_type init) | |
| 1029 | +{ | |
| 1030 | + int ret = 0; | |
| 1031 | + | |
| 1032 | + if (index == 0 && init == USB_INIT_DEVICE) { | |
| 1033 | + imx8m_usb_power(index, true); | |
| 1034 | +#ifdef CONFIG_USB_TCPC | |
| 1035 | + ret = tcpc_setup_ufp_mode(&port1); | |
| 1036 | + if (ret) | |
| 1037 | + return ret; | |
| 1038 | +#endif | |
| 1039 | + dwc3_nxp_usb_phy_init(&dwc3_device_data); | |
| 1040 | + return dwc3_uboot_init(&dwc3_device_data); | |
| 1041 | + } else if (index == 0 && init == USB_INIT_HOST) { | |
| 1042 | +#ifdef CONFIG_USB_TCPC | |
| 1043 | + ret = tcpc_setup_dfp_mode(&port1); | |
| 1044 | +#endif | |
| 1045 | + return ret; | |
| 1046 | + } | |
| 1047 | + | |
| 1048 | + return 0; | |
| 1049 | +} | |
| 1050 | + | |
| 1051 | +int board_usb_cleanup(int index, enum usb_init_type init) | |
| 1052 | +{ | |
| 1053 | + int ret = 0; | |
| 1054 | + if (index == 0 && init == USB_INIT_DEVICE) { | |
| 1055 | + dwc3_uboot_exit(index); | |
| 1056 | + imx8m_usb_power(index, false); | |
| 1057 | + } else if (index == 0 && init == USB_INIT_HOST) { | |
| 1058 | +#ifdef CONFIG_USB_TCPC | |
| 1059 | + ret = tcpc_disable_src_vbus(&port1); | |
| 1060 | +#endif | |
| 1061 | + } | |
| 1062 | + | |
| 1063 | + return ret; | |
| 1064 | +} | |
| 1065 | + | |
| 1066 | +#ifdef CONFIG_USB_TCPC | |
| 1067 | +/* Not used so far */ | |
| 1068 | +int board_typec_get_mode(int index) | |
| 1069 | +{ | |
| 1070 | + int ret = 0; | |
| 1071 | + enum typec_cc_polarity pol; | |
| 1072 | + enum typec_cc_state state; | |
| 1073 | + | |
| 1074 | + if (index == 0) { | |
| 1075 | + tcpc_setup_ufp_mode(&port1); | |
| 1076 | + | |
| 1077 | + ret = tcpc_get_cc_status(&port1, &pol, &state); | |
| 1078 | + if (!ret) { | |
| 1079 | + if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD) | |
| 1080 | + return USB_INIT_HOST; | |
| 1081 | + } | |
| 1082 | + | |
| 1083 | + return USB_INIT_DEVICE; | |
| 1084 | + } else { | |
| 1085 | + return USB_INIT_HOST; | |
| 1086 | + } | |
| 1087 | +} | |
| 1088 | +#endif | |
| 1089 | +#endif | |
| 1090 | + | |
| 1091 | +static void setup_fec(void) | |
| 1092 | +{ | |
| 1093 | + struct iomuxc_gpr_base_regs *gpr = | |
| 1094 | + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; | |
| 1095 | + | |
| 1096 | + /* Enable RGMII TX clk output */ | |
| 1097 | + setbits_le32(&gpr->gpr[1], BIT(22)); | |
| 1098 | +} | |
| 1099 | + | |
| 1100 | +static int setup_eqos(void) | |
| 1101 | +{ | |
| 1102 | + struct iomuxc_gpr_base_regs *gpr = | |
| 1103 | + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; | |
| 1104 | + | |
| 1105 | + /* set INTF as RGMII, enable RGMII TXC clock */ | |
| 1106 | + clrsetbits_le32(&gpr->gpr[1], | |
| 1107 | + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); | |
| 1108 | + setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); | |
| 1109 | + | |
| 1110 | + return set_clk_eqos(ENET_125MHZ); | |
| 1111 | +} | |
| 1112 | + | |
| 1113 | +#if CONFIG_IS_ENABLED(NET) | |
| 1114 | +int board_phy_config(struct phy_device *phydev) | |
| 1115 | +{ | |
| 1116 | + if (phydev->drv->config) | |
| 1117 | + phydev->drv->config(phydev); | |
| 1118 | + return 0; | |
| 1119 | +} | |
| 1120 | +#endif | |
| 1121 | + | |
| 1122 | +int board_init(void) | |
| 1123 | +{ | |
| 1124 | +#ifdef CONFIG_USB_TCPC | |
| 1125 | + setup_typec(); | |
| 1126 | +#endif | |
| 1127 | + | |
| 1128 | + if (IS_ENABLED(CONFIG_FEC_MXC)) { | |
| 1129 | + setup_fec(); | |
| 1130 | + } | |
| 1131 | + | |
| 1132 | + if (IS_ENABLED(CONFIG_DWC_ETH_QOS)) { | |
| 1133 | + setup_eqos(); | |
| 1134 | + } | |
| 1135 | + | |
| 1136 | +#ifdef CONFIG_NAND_MXS | |
| 1137 | + setup_gpmi_nand(); | |
| 1138 | +#endif | |
| 1139 | + | |
| 1140 | +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) | |
| 1141 | + init_usb_clk(); | |
| 1142 | +#endif | |
| 1143 | + | |
| 1144 | + return 0; | |
| 1145 | +} | |
| 1146 | + | |
| 1147 | +int board_late_init(void) | |
| 1148 | +{ | |
| 1149 | +#ifdef CONFIG_ENV_IS_IN_MMC | |
| 1150 | + board_late_mmc_env_init(); | |
| 1151 | +#endif | |
| 1152 | +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG | |
| 1153 | + env_set("board_name", "EVK"); | |
| 1154 | + env_set("board_rev", "iMX8MP"); | |
| 1155 | +#endif | |
| 1156 | + | |
| 1157 | + return 0; | |
| 1158 | +} | |
| 1159 | + | |
| 1160 | +#ifdef CONFIG_ANDROID_SUPPORT | |
| 1161 | +bool is_power_key_pressed(void) { | |
| 1162 | + return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6))); | |
| 1163 | +} | |
| 1164 | +#endif | |
| 1165 | + | |
| 1166 | +#ifdef CONFIG_SPL_MMC | |
| 1167 | +#define UBOOT_RAW_SECTOR_OFFSET 0x40 | |
| 1168 | +unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc) | |
| 1169 | +{ | |
| 1170 | + u32 boot_dev = spl_boot_device(); | |
| 1171 | + switch (boot_dev) { | |
| 1172 | + case BOOT_DEVICE_MMC2: | |
| 1173 | + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET; | |
| 1174 | + default: | |
| 1175 | + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; | |
| 1176 | + } | |
| 1177 | +} | |
| 1178 | +#endif | |
| 1179 | + | |
| 1180 | +#ifdef CONFIG_FSL_FASTBOOT | |
| 1181 | +#ifdef CONFIG_ANDROID_RECOVERY | |
| 1182 | +int is_recovery_key_pressing(void) | |
| 1183 | +{ | |
| 1184 | + return 0; /* TODO */ | |
| 1185 | +} | |
| 1186 | +#endif /* CONFIG_ANDROID_RECOVERY */ | |
| 1187 | +#endif /* CONFIG_FSL_FASTBOOT */ | |
| 1188 | diff --git a/board/lingyun/igkboard-imx8mp/imximage-8mp-lpddr4.cfg b/board/lingyun/igkboard-imx8mp/imximage-8mp-lpddr4.cfg | |
| 1189 | new file mode 100644 | |
| 1190 | index 00000000..6dedf172 | |
| 1191 | --- /dev/null | |
| 1192 | +++ b/board/lingyun/igkboard-imx8mp/imximage-8mp-lpddr4.cfg | |
| 1193 | @@ -0,0 +1,9 @@ | |
| 1194 | +/* SPDX-License-Identifier: GPL-2.0+ */ | |
| 1195 | +/* | |
| 1196 | + * Copyright 2021 NXP | |
| 1197 | + */ | |
| 1198 | + | |
| 1199 | + | |
| 1200 | +ROM_VERSION v2 | |
| 1201 | +BOOT_FROM sd | |
| 1202 | +LOADER u-boot-spl-ddr.bin 0x920000 | |
| 1203 | diff --git a/board/lingyun/igkboard-imx8mp/lpddr4_timing.c b/board/lingyun/igkboard-imx8mp/lpddr4_timing.c | |
| 1204 | new file mode 100644 | |
| 84751c | 1205 | index 00000000..29d2d1fb |
| be049f | 1206 | --- /dev/null |
| W | 1207 | +++ b/board/lingyun/igkboard-imx8mp/lpddr4_timing.c |
| 84751c | 1208 | @@ -0,0 +1,1854 @@ |
| be049f | 1209 | +/* |
| W | 1210 | + * Copyright 2019 NXP |
| 1211 | + * | |
| 1212 | + * SPDX-License-Identifier: GPL-2.0+ | |
| 1213 | + * | |
| 1214 | + * Generated code from MX8M_DDR_tool | |
| 1215 | + * | |
| 1216 | + * Align with uboot version: | |
| 1217 | + * imx_v2019.04_5.4.x and above version | |
| 1218 | + * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: | |
| 1219 | + * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h> | |
| 1220 | + */ | |
| 1221 | + | |
| 1222 | +#include <linux/kernel.h> | |
| 1223 | +#include <asm/arch/ddr.h> | |
| 1224 | + | |
| 1225 | +struct dram_cfg_param ddr_ddrc_cfg[] = { | |
| 1226 | + /** Initialize DDRC registers **/ | |
| 1227 | + { 0x3d400304, 0x1 }, | |
| 1228 | + { 0x3d400030, 0x1 }, | |
| 84751c | 1229 | + { 0x3d400000, 0xa1080020 }, |
| be049f | 1230 | + { 0x3d400020, 0x1223 }, |
| 84751c | 1231 | + { 0x3d400024, 0x16e3600 }, |
| G | 1232 | + { 0x3d400064, 0x5b00d2 }, |
| 1233 | + { 0x3d400070, 0x7027f90 }, | |
| 1234 | + { 0x3d400074, 0x790 }, | |
| 1235 | + { 0x3d4000d0, 0xc00305ba }, | |
| 1236 | + { 0x3d4000d4, 0x940000 }, | |
| be049f | 1237 | + { 0x3d4000dc, 0xd4002d }, |
| 84751c | 1238 | + { 0x3d4000e0, 0x310000 }, |
| be049f | 1239 | + { 0x3d4000e8, 0x660048 }, |
| W | 1240 | + { 0x3d4000ec, 0x160048 }, |
| 84751c | 1241 | + { 0x3d400100, 0x191e1920 }, |
| G | 1242 | + { 0x3d400104, 0x60630 }, |
| 1243 | + { 0x3d40010c, 0xb0b000 }, | |
| 1244 | + { 0x3d400110, 0xe04080e }, | |
| be049f | 1245 | + { 0x3d400114, 0x2040c0c }, |
| W | 1246 | + { 0x3d400118, 0x1010007 }, |
| 84751c | 1247 | + { 0x3d40011c, 0x402 }, |
| be049f | 1248 | + { 0x3d400130, 0x20600 }, |
| 84751c | 1249 | + { 0x3d400134, 0xc100002 }, |
| G | 1250 | + { 0x3d400138, 0xd8 }, |
| 1251 | + { 0x3d400144, 0x96004b }, | |
| 1252 | + { 0x3d400180, 0x2ee0017 }, | |
| 1253 | + { 0x3d400184, 0x2605b8e }, | |
| be049f | 1254 | + { 0x3d400188, 0x0 }, |
| W | 1255 | + { 0x3d400190, 0x497820a }, |
| 1256 | + { 0x3d400194, 0x80303 }, | |
| 1257 | + { 0x3d4001b4, 0x170a }, | |
| 1258 | + { 0x3d4001a0, 0xe0400018 }, | |
| 1259 | + { 0x3d4001a4, 0xdf00e4 }, | |
| 1260 | + { 0x3d4001a8, 0x80000000 }, | |
| 1261 | + { 0x3d4001b0, 0x11 }, | |
| 1262 | + { 0x3d4001c0, 0x1 }, | |
| 1263 | + { 0x3d4001c4, 0x1 }, | |
| 84751c | 1264 | + { 0x3d4000f4, 0x699 }, |
| be049f | 1265 | + { 0x3d400108, 0x70e1617 }, |
| 84751c | 1266 | + { 0x3d400200, 0x1f }, |
| G | 1267 | + { 0x3d400208, 0x0 }, |
| be049f | 1268 | + { 0x3d40020c, 0x0 }, |
| W | 1269 | + { 0x3d400210, 0x1f1f }, |
| 1270 | + { 0x3d400204, 0x80808 }, | |
| 1271 | + { 0x3d400214, 0x7070707 }, | |
| 84751c | 1272 | + { 0x3d400218, 0x7070707 }, |
| G | 1273 | + { 0x3d40021c, 0xf0f }, |
| be049f | 1274 | + { 0x3d400250, 0x1705 }, |
| W | 1275 | + { 0x3d400254, 0x2c }, |
| 1276 | + { 0x3d40025c, 0x4000030 }, | |
| 1277 | + { 0x3d400264, 0x900093e7 }, | |
| 1278 | + { 0x3d40026c, 0x2005574 }, | |
| 1279 | + { 0x3d400400, 0x111 }, | |
| 1280 | + { 0x3d400404, 0x72ff }, | |
| 1281 | + { 0x3d400408, 0x72ff }, | |
| 1282 | + { 0x3d400494, 0x2100e07 }, | |
| 1283 | + { 0x3d400498, 0x620096 }, | |
| 1284 | + { 0x3d40049c, 0x1100e07 }, | |
| 1285 | + { 0x3d4004a0, 0xc8012c }, | |
| 1286 | + { 0x3d402020, 0x1021 }, | |
| 1287 | + { 0x3d402024, 0x30d400 }, | |
| 1288 | + { 0x3d402050, 0x20d000 }, | |
| 84751c | 1289 | + { 0x3d402064, 0xc001c }, |
| be049f | 1290 | + { 0x3d4020dc, 0x840000 }, |
| W | 1291 | + { 0x3d4020e0, 0x330000 }, |
| 1292 | + { 0x3d4020e8, 0x660048 }, | |
| 1293 | + { 0x3d4020ec, 0x160048 }, | |
| 1294 | + { 0x3d402100, 0xa040305 }, | |
| 1295 | + { 0x3d402104, 0x30407 }, | |
| 1296 | + { 0x3d402108, 0x203060b }, | |
| 1297 | + { 0x3d40210c, 0x505000 }, | |
| 1298 | + { 0x3d402110, 0x2040202 }, | |
| 1299 | + { 0x3d402114, 0x2030202 }, | |
| 1300 | + { 0x3d402118, 0x1010004 }, | |
| 84751c | 1301 | + { 0x3d40211c, 0x302 }, |
| be049f | 1302 | + { 0x3d402130, 0x20300 }, |
| W | 1303 | + { 0x3d402134, 0xa100002 }, |
| 84751c | 1304 | + { 0x3d402138, 0x1d }, |
| be049f | 1305 | + { 0x3d402144, 0x14000a }, |
| W | 1306 | + { 0x3d402180, 0x640004 }, |
| 1307 | + { 0x3d402190, 0x3818200 }, | |
| 1308 | + { 0x3d402194, 0x80303 }, | |
| 1309 | + { 0x3d4021b4, 0x100 }, | |
| 84751c | 1310 | + { 0x3d4020f4, 0x599 }, |
| be049f | 1311 | + { 0x3d403020, 0x1021 }, |
| W | 1312 | + { 0x3d403024, 0xc3500 }, |
| 1313 | + { 0x3d403050, 0x20d000 }, | |
| 84751c | 1314 | + { 0x3d403064, 0x30007 }, |
| be049f | 1315 | + { 0x3d4030dc, 0x840000 }, |
| W | 1316 | + { 0x3d4030e0, 0x330000 }, |
| 1317 | + { 0x3d4030e8, 0x660048 }, | |
| 1318 | + { 0x3d4030ec, 0x160048 }, | |
| 1319 | + { 0x3d403100, 0xa010102 }, | |
| 1320 | + { 0x3d403104, 0x30404 }, | |
| 1321 | + { 0x3d403108, 0x203060b }, | |
| 1322 | + { 0x3d40310c, 0x505000 }, | |
| 1323 | + { 0x3d403110, 0x2040202 }, | |
| 1324 | + { 0x3d403114, 0x2030202 }, | |
| 1325 | + { 0x3d403118, 0x1010004 }, | |
| 84751c | 1326 | + { 0x3d40311c, 0x302 }, |
| be049f | 1327 | + { 0x3d403130, 0x20300 }, |
| W | 1328 | + { 0x3d403134, 0xa100002 }, |
| 84751c | 1329 | + { 0x3d403138, 0x8 }, |
| be049f | 1330 | + { 0x3d403144, 0x50003 }, |
| W | 1331 | + { 0x3d403180, 0x190004 }, |
| 1332 | + { 0x3d403190, 0x3818200 }, | |
| 1333 | + { 0x3d403194, 0x80303 }, | |
| 1334 | + { 0x3d4031b4, 0x100 }, | |
| 84751c | 1335 | + { 0x3d4030f4, 0x599 }, |
| be049f | 1336 | + { 0x3d400028, 0x0 }, |
| W | 1337 | +}; |
| 1338 | + | |
| 1339 | +/* PHY Initialize Configuration */ | |
| 1340 | +struct dram_cfg_param ddr_ddrphy_cfg[] = { | |
| 1341 | + { 0x100a0, 0x0 }, | |
| 1342 | + { 0x100a1, 0x1 }, | |
| 1343 | + { 0x100a2, 0x2 }, | |
| 1344 | + { 0x100a3, 0x3 }, | |
| 1345 | + { 0x100a4, 0x4 }, | |
| 1346 | + { 0x100a5, 0x5 }, | |
| 1347 | + { 0x100a6, 0x6 }, | |
| 1348 | + { 0x100a7, 0x7 }, | |
| 1349 | + { 0x110a0, 0x0 }, | |
| 1350 | + { 0x110a1, 0x1 }, | |
| 1351 | + { 0x110a2, 0x3 }, | |
| 1352 | + { 0x110a3, 0x4 }, | |
| 1353 | + { 0x110a4, 0x5 }, | |
| 1354 | + { 0x110a5, 0x2 }, | |
| 1355 | + { 0x110a6, 0x7 }, | |
| 1356 | + { 0x110a7, 0x6 }, | |
| 1357 | + { 0x120a0, 0x0 }, | |
| 1358 | + { 0x120a1, 0x1 }, | |
| 1359 | + { 0x120a2, 0x3 }, | |
| 1360 | + { 0x120a3, 0x2 }, | |
| 1361 | + { 0x120a4, 0x5 }, | |
| 1362 | + { 0x120a5, 0x4 }, | |
| 1363 | + { 0x120a6, 0x7 }, | |
| 1364 | + { 0x120a7, 0x6 }, | |
| 1365 | + { 0x130a0, 0x0 }, | |
| 1366 | + { 0x130a1, 0x1 }, | |
| 1367 | + { 0x130a2, 0x2 }, | |
| 1368 | + { 0x130a3, 0x3 }, | |
| 1369 | + { 0x130a4, 0x4 }, | |
| 1370 | + { 0x130a5, 0x5 }, | |
| 1371 | + { 0x130a6, 0x6 }, | |
| 1372 | + { 0x130a7, 0x7 }, | |
| 1373 | + { 0x1005f, 0x1ff }, | |
| 1374 | + { 0x1015f, 0x1ff }, | |
| 1375 | + { 0x1105f, 0x1ff }, | |
| 1376 | + { 0x1115f, 0x1ff }, | |
| 1377 | + { 0x1205f, 0x1ff }, | |
| 1378 | + { 0x1215f, 0x1ff }, | |
| 1379 | + { 0x1305f, 0x1ff }, | |
| 1380 | + { 0x1315f, 0x1ff }, | |
| 1381 | + { 0x11005f, 0x1ff }, | |
| 1382 | + { 0x11015f, 0x1ff }, | |
| 1383 | + { 0x11105f, 0x1ff }, | |
| 1384 | + { 0x11115f, 0x1ff }, | |
| 1385 | + { 0x11205f, 0x1ff }, | |
| 1386 | + { 0x11215f, 0x1ff }, | |
| 1387 | + { 0x11305f, 0x1ff }, | |
| 1388 | + { 0x11315f, 0x1ff }, | |
| 1389 | + { 0x21005f, 0x1ff }, | |
| 1390 | + { 0x21015f, 0x1ff }, | |
| 1391 | + { 0x21105f, 0x1ff }, | |
| 1392 | + { 0x21115f, 0x1ff }, | |
| 1393 | + { 0x21205f, 0x1ff }, | |
| 1394 | + { 0x21215f, 0x1ff }, | |
| 1395 | + { 0x21305f, 0x1ff }, | |
| 1396 | + { 0x21315f, 0x1ff }, | |
| 1397 | + { 0x55, 0x1ff }, | |
| 1398 | + { 0x1055, 0x1ff }, | |
| 1399 | + { 0x2055, 0x1ff }, | |
| 1400 | + { 0x3055, 0x1ff }, | |
| 1401 | + { 0x4055, 0x1ff }, | |
| 1402 | + { 0x5055, 0x1ff }, | |
| 1403 | + { 0x6055, 0x1ff }, | |
| 1404 | + { 0x7055, 0x1ff }, | |
| 1405 | + { 0x8055, 0x1ff }, | |
| 1406 | + { 0x9055, 0x1ff }, | |
| 1407 | + { 0x200c5, 0x19 }, | |
| 1408 | + { 0x1200c5, 0x7 }, | |
| 1409 | + { 0x2200c5, 0x7 }, | |
| 1410 | + { 0x2002e, 0x2 }, | |
| 1411 | + { 0x12002e, 0x2 }, | |
| 1412 | + { 0x22002e, 0x2 }, | |
| 1413 | + { 0x90204, 0x0 }, | |
| 1414 | + { 0x190204, 0x0 }, | |
| 1415 | + { 0x290204, 0x0 }, | |
| 84751c | 1416 | + { 0x20024, 0x1a3 }, |
| be049f | 1417 | + { 0x2003a, 0x2 }, |
| 84751c | 1418 | + { 0x120024, 0x1a3 }, |
| be049f | 1419 | + { 0x2003a, 0x2 }, |
| 84751c | 1420 | + { 0x220024, 0x1a3 }, |
| be049f | 1421 | + { 0x2003a, 0x2 }, |
| W | 1422 | + { 0x20056, 0x3 }, |
| 1423 | + { 0x120056, 0x3 }, | |
| 1424 | + { 0x220056, 0x3 }, | |
| 1425 | + { 0x1004d, 0xe00 }, | |
| 1426 | + { 0x1014d, 0xe00 }, | |
| 1427 | + { 0x1104d, 0xe00 }, | |
| 1428 | + { 0x1114d, 0xe00 }, | |
| 1429 | + { 0x1204d, 0xe00 }, | |
| 1430 | + { 0x1214d, 0xe00 }, | |
| 1431 | + { 0x1304d, 0xe00 }, | |
| 1432 | + { 0x1314d, 0xe00 }, | |
| 1433 | + { 0x11004d, 0xe00 }, | |
| 1434 | + { 0x11014d, 0xe00 }, | |
| 1435 | + { 0x11104d, 0xe00 }, | |
| 1436 | + { 0x11114d, 0xe00 }, | |
| 1437 | + { 0x11204d, 0xe00 }, | |
| 1438 | + { 0x11214d, 0xe00 }, | |
| 1439 | + { 0x11304d, 0xe00 }, | |
| 1440 | + { 0x11314d, 0xe00 }, | |
| 1441 | + { 0x21004d, 0xe00 }, | |
| 1442 | + { 0x21014d, 0xe00 }, | |
| 1443 | + { 0x21104d, 0xe00 }, | |
| 1444 | + { 0x21114d, 0xe00 }, | |
| 1445 | + { 0x21204d, 0xe00 }, | |
| 1446 | + { 0x21214d, 0xe00 }, | |
| 1447 | + { 0x21304d, 0xe00 }, | |
| 1448 | + { 0x21314d, 0xe00 }, | |
| 1449 | + { 0x10049, 0xeba }, | |
| 1450 | + { 0x10149, 0xeba }, | |
| 1451 | + { 0x11049, 0xeba }, | |
| 1452 | + { 0x11149, 0xeba }, | |
| 1453 | + { 0x12049, 0xeba }, | |
| 1454 | + { 0x12149, 0xeba }, | |
| 1455 | + { 0x13049, 0xeba }, | |
| 1456 | + { 0x13149, 0xeba }, | |
| 1457 | + { 0x110049, 0xeba }, | |
| 1458 | + { 0x110149, 0xeba }, | |
| 1459 | + { 0x111049, 0xeba }, | |
| 1460 | + { 0x111149, 0xeba }, | |
| 1461 | + { 0x112049, 0xeba }, | |
| 1462 | + { 0x112149, 0xeba }, | |
| 1463 | + { 0x113049, 0xeba }, | |
| 1464 | + { 0x113149, 0xeba }, | |
| 1465 | + { 0x210049, 0xeba }, | |
| 1466 | + { 0x210149, 0xeba }, | |
| 1467 | + { 0x211049, 0xeba }, | |
| 1468 | + { 0x211149, 0xeba }, | |
| 1469 | + { 0x212049, 0xeba }, | |
| 1470 | + { 0x212149, 0xeba }, | |
| 1471 | + { 0x213049, 0xeba }, | |
| 1472 | + { 0x213149, 0xeba }, | |
| 1473 | + { 0x43, 0x63 }, | |
| 1474 | + { 0x1043, 0x63 }, | |
| 1475 | + { 0x2043, 0x63 }, | |
| 1476 | + { 0x3043, 0x63 }, | |
| 1477 | + { 0x4043, 0x63 }, | |
| 1478 | + { 0x5043, 0x63 }, | |
| 1479 | + { 0x6043, 0x63 }, | |
| 1480 | + { 0x7043, 0x63 }, | |
| 1481 | + { 0x8043, 0x63 }, | |
| 1482 | + { 0x9043, 0x63 }, | |
| 1483 | + { 0x20018, 0x3 }, | |
| 1484 | + { 0x20075, 0x4 }, | |
| 1485 | + { 0x20050, 0x0 }, | |
| 84751c | 1486 | + { 0x20008, 0x2ee }, |
| be049f | 1487 | + { 0x120008, 0x64 }, |
| W | 1488 | + { 0x220008, 0x19 }, |
| 1489 | + { 0x20088, 0x9 }, | |
| 1490 | + { 0x200b2, 0x104 }, | |
| 1491 | + { 0x10043, 0x5a1 }, | |
| 1492 | + { 0x10143, 0x5a1 }, | |
| 1493 | + { 0x11043, 0x5a1 }, | |
| 1494 | + { 0x11143, 0x5a1 }, | |
| 1495 | + { 0x12043, 0x5a1 }, | |
| 1496 | + { 0x12143, 0x5a1 }, | |
| 1497 | + { 0x13043, 0x5a1 }, | |
| 1498 | + { 0x13143, 0x5a1 }, | |
| 1499 | + { 0x1200b2, 0x104 }, | |
| 1500 | + { 0x110043, 0x5a1 }, | |
| 1501 | + { 0x110143, 0x5a1 }, | |
| 1502 | + { 0x111043, 0x5a1 }, | |
| 1503 | + { 0x111143, 0x5a1 }, | |
| 1504 | + { 0x112043, 0x5a1 }, | |
| 1505 | + { 0x112143, 0x5a1 }, | |
| 1506 | + { 0x113043, 0x5a1 }, | |
| 1507 | + { 0x113143, 0x5a1 }, | |
| 1508 | + { 0x2200b2, 0x104 }, | |
| 1509 | + { 0x210043, 0x5a1 }, | |
| 1510 | + { 0x210143, 0x5a1 }, | |
| 1511 | + { 0x211043, 0x5a1 }, | |
| 1512 | + { 0x211143, 0x5a1 }, | |
| 1513 | + { 0x212043, 0x5a1 }, | |
| 1514 | + { 0x212143, 0x5a1 }, | |
| 1515 | + { 0x213043, 0x5a1 }, | |
| 1516 | + { 0x213143, 0x5a1 }, | |
| 1517 | + { 0x200fa, 0x1 }, | |
| 1518 | + { 0x1200fa, 0x1 }, | |
| 1519 | + { 0x2200fa, 0x1 }, | |
| 1520 | + { 0x20019, 0x1 }, | |
| 1521 | + { 0x120019, 0x1 }, | |
| 1522 | + { 0x220019, 0x1 }, | |
| 1523 | + { 0x200f0, 0x660 }, | |
| 1524 | + { 0x200f1, 0x0 }, | |
| 1525 | + { 0x200f2, 0x4444 }, | |
| 1526 | + { 0x200f3, 0x8888 }, | |
| 1527 | + { 0x200f4, 0x5665 }, | |
| 1528 | + { 0x200f5, 0x0 }, | |
| 1529 | + { 0x200f6, 0x0 }, | |
| 1530 | + { 0x200f7, 0xf000 }, | |
| 1531 | + { 0x20025, 0x0 }, | |
| 1532 | + { 0x2002d, 0x0 }, | |
| 1533 | + { 0x12002d, 0x0 }, | |
| 1534 | + { 0x22002d, 0x0 }, | |
| 1535 | + { 0x2007d, 0x212 }, | |
| 1536 | + { 0x12007d, 0x212 }, | |
| 1537 | + { 0x22007d, 0x212 }, | |
| 1538 | + { 0x2007c, 0x61 }, | |
| 1539 | + { 0x12007c, 0x61 }, | |
| 1540 | + { 0x22007c, 0x61 }, | |
| 1541 | + { 0x1004a, 0x500 }, | |
| 1542 | + { 0x1104a, 0x500 }, | |
| 1543 | + { 0x1204a, 0x500 }, | |
| 1544 | + { 0x1304a, 0x500 }, | |
| 1545 | + { 0x2002c, 0x0 }, | |
| 1546 | +}; | |
| 1547 | + | |
| 1548 | +/* ddr phy trained csr */ | |
| 1549 | +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { | |
| 1550 | + { 0x200b2, 0x0 }, | |
| 1551 | + { 0x1200b2, 0x0 }, | |
| 1552 | + { 0x2200b2, 0x0 }, | |
| 1553 | + { 0x200cb, 0x0 }, | |
| 1554 | + { 0x10043, 0x0 }, | |
| 1555 | + { 0x110043, 0x0 }, | |
| 1556 | + { 0x210043, 0x0 }, | |
| 1557 | + { 0x10143, 0x0 }, | |
| 1558 | + { 0x110143, 0x0 }, | |
| 1559 | + { 0x210143, 0x0 }, | |
| 1560 | + { 0x11043, 0x0 }, | |
| 1561 | + { 0x111043, 0x0 }, | |
| 1562 | + { 0x211043, 0x0 }, | |
| 1563 | + { 0x11143, 0x0 }, | |
| 1564 | + { 0x111143, 0x0 }, | |
| 1565 | + { 0x211143, 0x0 }, | |
| 1566 | + { 0x12043, 0x0 }, | |
| 1567 | + { 0x112043, 0x0 }, | |
| 1568 | + { 0x212043, 0x0 }, | |
| 1569 | + { 0x12143, 0x0 }, | |
| 1570 | + { 0x112143, 0x0 }, | |
| 1571 | + { 0x212143, 0x0 }, | |
| 1572 | + { 0x13043, 0x0 }, | |
| 1573 | + { 0x113043, 0x0 }, | |
| 1574 | + { 0x213043, 0x0 }, | |
| 1575 | + { 0x13143, 0x0 }, | |
| 1576 | + { 0x113143, 0x0 }, | |
| 1577 | + { 0x213143, 0x0 }, | |
| 1578 | + { 0x80, 0x0 }, | |
| 1579 | + { 0x100080, 0x0 }, | |
| 1580 | + { 0x200080, 0x0 }, | |
| 1581 | + { 0x1080, 0x0 }, | |
| 1582 | + { 0x101080, 0x0 }, | |
| 1583 | + { 0x201080, 0x0 }, | |
| 1584 | + { 0x2080, 0x0 }, | |
| 1585 | + { 0x102080, 0x0 }, | |
| 1586 | + { 0x202080, 0x0 }, | |
| 1587 | + { 0x3080, 0x0 }, | |
| 1588 | + { 0x103080, 0x0 }, | |
| 1589 | + { 0x203080, 0x0 }, | |
| 1590 | + { 0x4080, 0x0 }, | |
| 1591 | + { 0x104080, 0x0 }, | |
| 1592 | + { 0x204080, 0x0 }, | |
| 1593 | + { 0x5080, 0x0 }, | |
| 1594 | + { 0x105080, 0x0 }, | |
| 1595 | + { 0x205080, 0x0 }, | |
| 1596 | + { 0x6080, 0x0 }, | |
| 1597 | + { 0x106080, 0x0 }, | |
| 1598 | + { 0x206080, 0x0 }, | |
| 1599 | + { 0x7080, 0x0 }, | |
| 1600 | + { 0x107080, 0x0 }, | |
| 1601 | + { 0x207080, 0x0 }, | |
| 1602 | + { 0x8080, 0x0 }, | |
| 1603 | + { 0x108080, 0x0 }, | |
| 1604 | + { 0x208080, 0x0 }, | |
| 1605 | + { 0x9080, 0x0 }, | |
| 1606 | + { 0x109080, 0x0 }, | |
| 1607 | + { 0x209080, 0x0 }, | |
| 1608 | + { 0x10080, 0x0 }, | |
| 1609 | + { 0x110080, 0x0 }, | |
| 1610 | + { 0x210080, 0x0 }, | |
| 1611 | + { 0x10180, 0x0 }, | |
| 1612 | + { 0x110180, 0x0 }, | |
| 1613 | + { 0x210180, 0x0 }, | |
| 1614 | + { 0x11080, 0x0 }, | |
| 1615 | + { 0x111080, 0x0 }, | |
| 1616 | + { 0x211080, 0x0 }, | |
| 1617 | + { 0x11180, 0x0 }, | |
| 1618 | + { 0x111180, 0x0 }, | |
| 1619 | + { 0x211180, 0x0 }, | |
| 1620 | + { 0x12080, 0x0 }, | |
| 1621 | + { 0x112080, 0x0 }, | |
| 1622 | + { 0x212080, 0x0 }, | |
| 1623 | + { 0x12180, 0x0 }, | |
| 1624 | + { 0x112180, 0x0 }, | |
| 1625 | + { 0x212180, 0x0 }, | |
| 1626 | + { 0x13080, 0x0 }, | |
| 1627 | + { 0x113080, 0x0 }, | |
| 1628 | + { 0x213080, 0x0 }, | |
| 1629 | + { 0x13180, 0x0 }, | |
| 1630 | + { 0x113180, 0x0 }, | |
| 1631 | + { 0x213180, 0x0 }, | |
| 1632 | + { 0x10081, 0x0 }, | |
| 1633 | + { 0x110081, 0x0 }, | |
| 1634 | + { 0x210081, 0x0 }, | |
| 1635 | + { 0x10181, 0x0 }, | |
| 1636 | + { 0x110181, 0x0 }, | |
| 1637 | + { 0x210181, 0x0 }, | |
| 1638 | + { 0x11081, 0x0 }, | |
| 1639 | + { 0x111081, 0x0 }, | |
| 1640 | + { 0x211081, 0x0 }, | |
| 1641 | + { 0x11181, 0x0 }, | |
| 1642 | + { 0x111181, 0x0 }, | |
| 1643 | + { 0x211181, 0x0 }, | |
| 1644 | + { 0x12081, 0x0 }, | |
| 1645 | + { 0x112081, 0x0 }, | |
| 1646 | + { 0x212081, 0x0 }, | |
| 1647 | + { 0x12181, 0x0 }, | |
| 1648 | + { 0x112181, 0x0 }, | |
| 1649 | + { 0x212181, 0x0 }, | |
| 1650 | + { 0x13081, 0x0 }, | |
| 1651 | + { 0x113081, 0x0 }, | |
| 1652 | + { 0x213081, 0x0 }, | |
| 1653 | + { 0x13181, 0x0 }, | |
| 1654 | + { 0x113181, 0x0 }, | |
| 1655 | + { 0x213181, 0x0 }, | |
| 1656 | + { 0x100d0, 0x0 }, | |
| 1657 | + { 0x1100d0, 0x0 }, | |
| 1658 | + { 0x2100d0, 0x0 }, | |
| 1659 | + { 0x101d0, 0x0 }, | |
| 1660 | + { 0x1101d0, 0x0 }, | |
| 1661 | + { 0x2101d0, 0x0 }, | |
| 1662 | + { 0x110d0, 0x0 }, | |
| 1663 | + { 0x1110d0, 0x0 }, | |
| 1664 | + { 0x2110d0, 0x0 }, | |
| 1665 | + { 0x111d0, 0x0 }, | |
| 1666 | + { 0x1111d0, 0x0 }, | |
| 1667 | + { 0x2111d0, 0x0 }, | |
| 1668 | + { 0x120d0, 0x0 }, | |
| 1669 | + { 0x1120d0, 0x0 }, | |
| 1670 | + { 0x2120d0, 0x0 }, | |
| 1671 | + { 0x121d0, 0x0 }, | |
| 1672 | + { 0x1121d0, 0x0 }, | |
| 1673 | + { 0x2121d0, 0x0 }, | |
| 1674 | + { 0x130d0, 0x0 }, | |
| 1675 | + { 0x1130d0, 0x0 }, | |
| 1676 | + { 0x2130d0, 0x0 }, | |
| 1677 | + { 0x131d0, 0x0 }, | |
| 1678 | + { 0x1131d0, 0x0 }, | |
| 1679 | + { 0x2131d0, 0x0 }, | |
| 1680 | + { 0x100d1, 0x0 }, | |
| 1681 | + { 0x1100d1, 0x0 }, | |
| 1682 | + { 0x2100d1, 0x0 }, | |
| 1683 | + { 0x101d1, 0x0 }, | |
| 1684 | + { 0x1101d1, 0x0 }, | |
| 1685 | + { 0x2101d1, 0x0 }, | |
| 1686 | + { 0x110d1, 0x0 }, | |
| 1687 | + { 0x1110d1, 0x0 }, | |
| 1688 | + { 0x2110d1, 0x0 }, | |
| 1689 | + { 0x111d1, 0x0 }, | |
| 1690 | + { 0x1111d1, 0x0 }, | |
| 1691 | + { 0x2111d1, 0x0 }, | |
| 1692 | + { 0x120d1, 0x0 }, | |
| 1693 | + { 0x1120d1, 0x0 }, | |
| 1694 | + { 0x2120d1, 0x0 }, | |
| 1695 | + { 0x121d1, 0x0 }, | |
| 1696 | + { 0x1121d1, 0x0 }, | |
| 1697 | + { 0x2121d1, 0x0 }, | |
| 1698 | + { 0x130d1, 0x0 }, | |
| 1699 | + { 0x1130d1, 0x0 }, | |
| 1700 | + { 0x2130d1, 0x0 }, | |
| 1701 | + { 0x131d1, 0x0 }, | |
| 1702 | + { 0x1131d1, 0x0 }, | |
| 1703 | + { 0x2131d1, 0x0 }, | |
| 1704 | + { 0x10068, 0x0 }, | |
| 1705 | + { 0x10168, 0x0 }, | |
| 1706 | + { 0x10268, 0x0 }, | |
| 1707 | + { 0x10368, 0x0 }, | |
| 1708 | + { 0x10468, 0x0 }, | |
| 1709 | + { 0x10568, 0x0 }, | |
| 1710 | + { 0x10668, 0x0 }, | |
| 1711 | + { 0x10768, 0x0 }, | |
| 1712 | + { 0x10868, 0x0 }, | |
| 1713 | + { 0x11068, 0x0 }, | |
| 1714 | + { 0x11168, 0x0 }, | |
| 1715 | + { 0x11268, 0x0 }, | |
| 1716 | + { 0x11368, 0x0 }, | |
| 1717 | + { 0x11468, 0x0 }, | |
| 1718 | + { 0x11568, 0x0 }, | |
| 1719 | + { 0x11668, 0x0 }, | |
| 1720 | + { 0x11768, 0x0 }, | |
| 1721 | + { 0x11868, 0x0 }, | |
| 1722 | + { 0x12068, 0x0 }, | |
| 1723 | + { 0x12168, 0x0 }, | |
| 1724 | + { 0x12268, 0x0 }, | |
| 1725 | + { 0x12368, 0x0 }, | |
| 1726 | + { 0x12468, 0x0 }, | |
| 1727 | + { 0x12568, 0x0 }, | |
| 1728 | + { 0x12668, 0x0 }, | |
| 1729 | + { 0x12768, 0x0 }, | |
| 1730 | + { 0x12868, 0x0 }, | |
| 1731 | + { 0x13068, 0x0 }, | |
| 1732 | + { 0x13168, 0x0 }, | |
| 1733 | + { 0x13268, 0x0 }, | |
| 1734 | + { 0x13368, 0x0 }, | |
| 1735 | + { 0x13468, 0x0 }, | |
| 1736 | + { 0x13568, 0x0 }, | |
| 1737 | + { 0x13668, 0x0 }, | |
| 1738 | + { 0x13768, 0x0 }, | |
| 1739 | + { 0x13868, 0x0 }, | |
| 1740 | + { 0x10069, 0x0 }, | |
| 1741 | + { 0x10169, 0x0 }, | |
| 1742 | + { 0x10269, 0x0 }, | |
| 1743 | + { 0x10369, 0x0 }, | |
| 1744 | + { 0x10469, 0x0 }, | |
| 1745 | + { 0x10569, 0x0 }, | |
| 1746 | + { 0x10669, 0x0 }, | |
| 1747 | + { 0x10769, 0x0 }, | |
| 1748 | + { 0x10869, 0x0 }, | |
| 1749 | + { 0x11069, 0x0 }, | |
| 1750 | + { 0x11169, 0x0 }, | |
| 1751 | + { 0x11269, 0x0 }, | |
| 1752 | + { 0x11369, 0x0 }, | |
| 1753 | + { 0x11469, 0x0 }, | |
| 1754 | + { 0x11569, 0x0 }, | |
| 1755 | + { 0x11669, 0x0 }, | |
| 1756 | + { 0x11769, 0x0 }, | |
| 1757 | + { 0x11869, 0x0 }, | |
| 1758 | + { 0x12069, 0x0 }, | |
| 1759 | + { 0x12169, 0x0 }, | |
| 1760 | + { 0x12269, 0x0 }, | |
| 1761 | + { 0x12369, 0x0 }, | |
| 1762 | + { 0x12469, 0x0 }, | |
| 1763 | + { 0x12569, 0x0 }, | |
| 1764 | + { 0x12669, 0x0 }, | |
| 1765 | + { 0x12769, 0x0 }, | |
| 1766 | + { 0x12869, 0x0 }, | |
| 1767 | + { 0x13069, 0x0 }, | |
| 1768 | + { 0x13169, 0x0 }, | |
| 1769 | + { 0x13269, 0x0 }, | |
| 1770 | + { 0x13369, 0x0 }, | |
| 1771 | + { 0x13469, 0x0 }, | |
| 1772 | + { 0x13569, 0x0 }, | |
| 1773 | + { 0x13669, 0x0 }, | |
| 1774 | + { 0x13769, 0x0 }, | |
| 1775 | + { 0x13869, 0x0 }, | |
| 1776 | + { 0x1008c, 0x0 }, | |
| 1777 | + { 0x11008c, 0x0 }, | |
| 1778 | + { 0x21008c, 0x0 }, | |
| 1779 | + { 0x1018c, 0x0 }, | |
| 1780 | + { 0x11018c, 0x0 }, | |
| 1781 | + { 0x21018c, 0x0 }, | |
| 1782 | + { 0x1108c, 0x0 }, | |
| 1783 | + { 0x11108c, 0x0 }, | |
| 1784 | + { 0x21108c, 0x0 }, | |
| 1785 | + { 0x1118c, 0x0 }, | |
| 1786 | + { 0x11118c, 0x0 }, | |
| 1787 | + { 0x21118c, 0x0 }, | |
| 1788 | + { 0x1208c, 0x0 }, | |
| 1789 | + { 0x11208c, 0x0 }, | |
| 1790 | + { 0x21208c, 0x0 }, | |
| 1791 | + { 0x1218c, 0x0 }, | |
| 1792 | + { 0x11218c, 0x0 }, | |
| 1793 | + { 0x21218c, 0x0 }, | |
| 1794 | + { 0x1308c, 0x0 }, | |
| 1795 | + { 0x11308c, 0x0 }, | |
| 1796 | + { 0x21308c, 0x0 }, | |
| 1797 | + { 0x1318c, 0x0 }, | |
| 1798 | + { 0x11318c, 0x0 }, | |
| 1799 | + { 0x21318c, 0x0 }, | |
| 1800 | + { 0x1008d, 0x0 }, | |
| 1801 | + { 0x11008d, 0x0 }, | |
| 1802 | + { 0x21008d, 0x0 }, | |
| 1803 | + { 0x1018d, 0x0 }, | |
| 1804 | + { 0x11018d, 0x0 }, | |
| 1805 | + { 0x21018d, 0x0 }, | |
| 1806 | + { 0x1108d, 0x0 }, | |
| 1807 | + { 0x11108d, 0x0 }, | |
| 1808 | + { 0x21108d, 0x0 }, | |
| 1809 | + { 0x1118d, 0x0 }, | |
| 1810 | + { 0x11118d, 0x0 }, | |
| 1811 | + { 0x21118d, 0x0 }, | |
| 1812 | + { 0x1208d, 0x0 }, | |
| 1813 | + { 0x11208d, 0x0 }, | |
| 1814 | + { 0x21208d, 0x0 }, | |
| 1815 | + { 0x1218d, 0x0 }, | |
| 1816 | + { 0x11218d, 0x0 }, | |
| 1817 | + { 0x21218d, 0x0 }, | |
| 1818 | + { 0x1308d, 0x0 }, | |
| 1819 | + { 0x11308d, 0x0 }, | |
| 1820 | + { 0x21308d, 0x0 }, | |
| 1821 | + { 0x1318d, 0x0 }, | |
| 1822 | + { 0x11318d, 0x0 }, | |
| 1823 | + { 0x21318d, 0x0 }, | |
| 1824 | + { 0x100c0, 0x0 }, | |
| 1825 | + { 0x1100c0, 0x0 }, | |
| 1826 | + { 0x2100c0, 0x0 }, | |
| 1827 | + { 0x101c0, 0x0 }, | |
| 1828 | + { 0x1101c0, 0x0 }, | |
| 1829 | + { 0x2101c0, 0x0 }, | |
| 1830 | + { 0x102c0, 0x0 }, | |
| 1831 | + { 0x1102c0, 0x0 }, | |
| 1832 | + { 0x2102c0, 0x0 }, | |
| 1833 | + { 0x103c0, 0x0 }, | |
| 1834 | + { 0x1103c0, 0x0 }, | |
| 1835 | + { 0x2103c0, 0x0 }, | |
| 1836 | + { 0x104c0, 0x0 }, | |
| 1837 | + { 0x1104c0, 0x0 }, | |
| 1838 | + { 0x2104c0, 0x0 }, | |
| 1839 | + { 0x105c0, 0x0 }, | |
| 1840 | + { 0x1105c0, 0x0 }, | |
| 1841 | + { 0x2105c0, 0x0 }, | |
| 1842 | + { 0x106c0, 0x0 }, | |
| 1843 | + { 0x1106c0, 0x0 }, | |
| 1844 | + { 0x2106c0, 0x0 }, | |
| 1845 | + { 0x107c0, 0x0 }, | |
| 1846 | + { 0x1107c0, 0x0 }, | |
| 1847 | + { 0x2107c0, 0x0 }, | |
| 1848 | + { 0x108c0, 0x0 }, | |
| 1849 | + { 0x1108c0, 0x0 }, | |
| 1850 | + { 0x2108c0, 0x0 }, | |
| 1851 | + { 0x110c0, 0x0 }, | |
| 1852 | + { 0x1110c0, 0x0 }, | |
| 1853 | + { 0x2110c0, 0x0 }, | |
| 1854 | + { 0x111c0, 0x0 }, | |
| 1855 | + { 0x1111c0, 0x0 }, | |
| 1856 | + { 0x2111c0, 0x0 }, | |
| 1857 | + { 0x112c0, 0x0 }, | |
| 1858 | + { 0x1112c0, 0x0 }, | |
| 1859 | + { 0x2112c0, 0x0 }, | |
| 1860 | + { 0x113c0, 0x0 }, | |
| 1861 | + { 0x1113c0, 0x0 }, | |
| 1862 | + { 0x2113c0, 0x0 }, | |
| 1863 | + { 0x114c0, 0x0 }, | |
| 1864 | + { 0x1114c0, 0x0 }, | |
| 1865 | + { 0x2114c0, 0x0 }, | |
| 1866 | + { 0x115c0, 0x0 }, | |
| 1867 | + { 0x1115c0, 0x0 }, | |
| 1868 | + { 0x2115c0, 0x0 }, | |
| 1869 | + { 0x116c0, 0x0 }, | |
| 1870 | + { 0x1116c0, 0x0 }, | |
| 1871 | + { 0x2116c0, 0x0 }, | |
| 1872 | + { 0x117c0, 0x0 }, | |
| 1873 | + { 0x1117c0, 0x0 }, | |
| 1874 | + { 0x2117c0, 0x0 }, | |
| 1875 | + { 0x118c0, 0x0 }, | |
| 1876 | + { 0x1118c0, 0x0 }, | |
| 1877 | + { 0x2118c0, 0x0 }, | |
| 1878 | + { 0x120c0, 0x0 }, | |
| 1879 | + { 0x1120c0, 0x0 }, | |
| 1880 | + { 0x2120c0, 0x0 }, | |
| 1881 | + { 0x121c0, 0x0 }, | |
| 1882 | + { 0x1121c0, 0x0 }, | |
| 1883 | + { 0x2121c0, 0x0 }, | |
| 1884 | + { 0x122c0, 0x0 }, | |
| 1885 | + { 0x1122c0, 0x0 }, | |
| 1886 | + { 0x2122c0, 0x0 }, | |
| 1887 | + { 0x123c0, 0x0 }, | |
| 1888 | + { 0x1123c0, 0x0 }, | |
| 1889 | + { 0x2123c0, 0x0 }, | |
| 1890 | + { 0x124c0, 0x0 }, | |
| 1891 | + { 0x1124c0, 0x0 }, | |
| 1892 | + { 0x2124c0, 0x0 }, | |
| 1893 | + { 0x125c0, 0x0 }, | |
| 1894 | + { 0x1125c0, 0x0 }, | |
| 1895 | + { 0x2125c0, 0x0 }, | |
| 1896 | + { 0x126c0, 0x0 }, | |
| 1897 | + { 0x1126c0, 0x0 }, | |
| 1898 | + { 0x2126c0, 0x0 }, | |
| 1899 | + { 0x127c0, 0x0 }, | |
| 1900 | + { 0x1127c0, 0x0 }, | |
| 1901 | + { 0x2127c0, 0x0 }, | |
| 1902 | + { 0x128c0, 0x0 }, | |
| 1903 | + { 0x1128c0, 0x0 }, | |
| 1904 | + { 0x2128c0, 0x0 }, | |
| 1905 | + { 0x130c0, 0x0 }, | |
| 1906 | + { 0x1130c0, 0x0 }, | |
| 1907 | + { 0x2130c0, 0x0 }, | |
| 1908 | + { 0x131c0, 0x0 }, | |
| 1909 | + { 0x1131c0, 0x0 }, | |
| 1910 | + { 0x2131c0, 0x0 }, | |
| 1911 | + { 0x132c0, 0x0 }, | |
| 1912 | + { 0x1132c0, 0x0 }, | |
| 1913 | + { 0x2132c0, 0x0 }, | |
| 1914 | + { 0x133c0, 0x0 }, | |
| 1915 | + { 0x1133c0, 0x0 }, | |
| 1916 | + { 0x2133c0, 0x0 }, | |
| 1917 | + { 0x134c0, 0x0 }, | |
| 1918 | + { 0x1134c0, 0x0 }, | |
| 1919 | + { 0x2134c0, 0x0 }, | |
| 1920 | + { 0x135c0, 0x0 }, | |
| 1921 | + { 0x1135c0, 0x0 }, | |
| 1922 | + { 0x2135c0, 0x0 }, | |
| 1923 | + { 0x136c0, 0x0 }, | |
| 1924 | + { 0x1136c0, 0x0 }, | |
| 1925 | + { 0x2136c0, 0x0 }, | |
| 1926 | + { 0x137c0, 0x0 }, | |
| 1927 | + { 0x1137c0, 0x0 }, | |
| 1928 | + { 0x2137c0, 0x0 }, | |
| 1929 | + { 0x138c0, 0x0 }, | |
| 1930 | + { 0x1138c0, 0x0 }, | |
| 1931 | + { 0x2138c0, 0x0 }, | |
| 1932 | + { 0x100c1, 0x0 }, | |
| 1933 | + { 0x1100c1, 0x0 }, | |
| 1934 | + { 0x2100c1, 0x0 }, | |
| 1935 | + { 0x101c1, 0x0 }, | |
| 1936 | + { 0x1101c1, 0x0 }, | |
| 1937 | + { 0x2101c1, 0x0 }, | |
| 1938 | + { 0x102c1, 0x0 }, | |
| 1939 | + { 0x1102c1, 0x0 }, | |
| 1940 | + { 0x2102c1, 0x0 }, | |
| 1941 | + { 0x103c1, 0x0 }, | |
| 1942 | + { 0x1103c1, 0x0 }, | |
| 1943 | + { 0x2103c1, 0x0 }, | |
| 1944 | + { 0x104c1, 0x0 }, | |
| 1945 | + { 0x1104c1, 0x0 }, | |
| 1946 | + { 0x2104c1, 0x0 }, | |
| 1947 | + { 0x105c1, 0x0 }, | |
| 1948 | + { 0x1105c1, 0x0 }, | |
| 1949 | + { 0x2105c1, 0x0 }, | |
| 1950 | + { 0x106c1, 0x0 }, | |
| 1951 | + { 0x1106c1, 0x0 }, | |
| 1952 | + { 0x2106c1, 0x0 }, | |
| 1953 | + { 0x107c1, 0x0 }, | |
| 1954 | + { 0x1107c1, 0x0 }, | |
| 1955 | + { 0x2107c1, 0x0 }, | |
| 1956 | + { 0x108c1, 0x0 }, | |
| 1957 | + { 0x1108c1, 0x0 }, | |
| 1958 | + { 0x2108c1, 0x0 }, | |
| 1959 | + { 0x110c1, 0x0 }, | |
| 1960 | + { 0x1110c1, 0x0 }, | |
| 1961 | + { 0x2110c1, 0x0 }, | |
| 1962 | + { 0x111c1, 0x0 }, | |
| 1963 | + { 0x1111c1, 0x0 }, | |
| 1964 | + { 0x2111c1, 0x0 }, | |
| 1965 | + { 0x112c1, 0x0 }, | |
| 1966 | + { 0x1112c1, 0x0 }, | |
| 1967 | + { 0x2112c1, 0x0 }, | |
| 1968 | + { 0x113c1, 0x0 }, | |
| 1969 | + { 0x1113c1, 0x0 }, | |
| 1970 | + { 0x2113c1, 0x0 }, | |
| 1971 | + { 0x114c1, 0x0 }, | |
| 1972 | + { 0x1114c1, 0x0 }, | |
| 1973 | + { 0x2114c1, 0x0 }, | |
| 1974 | + { 0x115c1, 0x0 }, | |
| 1975 | + { 0x1115c1, 0x0 }, | |
| 1976 | + { 0x2115c1, 0x0 }, | |
| 1977 | + { 0x116c1, 0x0 }, | |
| 1978 | + { 0x1116c1, 0x0 }, | |
| 1979 | + { 0x2116c1, 0x0 }, | |
| 1980 | + { 0x117c1, 0x0 }, | |
| 1981 | + { 0x1117c1, 0x0 }, | |
| 1982 | + { 0x2117c1, 0x0 }, | |
| 1983 | + { 0x118c1, 0x0 }, | |
| 1984 | + { 0x1118c1, 0x0 }, | |
| 1985 | + { 0x2118c1, 0x0 }, | |
| 1986 | + { 0x120c1, 0x0 }, | |
| 1987 | + { 0x1120c1, 0x0 }, | |
| 1988 | + { 0x2120c1, 0x0 }, | |
| 1989 | + { 0x121c1, 0x0 }, | |
| 1990 | + { 0x1121c1, 0x0 }, | |
| 1991 | + { 0x2121c1, 0x0 }, | |
| 1992 | + { 0x122c1, 0x0 }, | |
| 1993 | + { 0x1122c1, 0x0 }, | |
| 1994 | + { 0x2122c1, 0x0 }, | |
| 1995 | + { 0x123c1, 0x0 }, | |
| 1996 | + { 0x1123c1, 0x0 }, | |
| 1997 | + { 0x2123c1, 0x0 }, | |
| 1998 | + { 0x124c1, 0x0 }, | |
| 1999 | + { 0x1124c1, 0x0 }, | |
| 2000 | + { 0x2124c1, 0x0 }, | |
| 2001 | + { 0x125c1, 0x0 }, | |
| 2002 | + { 0x1125c1, 0x0 }, | |
| 2003 | + { 0x2125c1, 0x0 }, | |
| 2004 | + { 0x126c1, 0x0 }, | |
| 2005 | + { 0x1126c1, 0x0 }, | |
| 2006 | + { 0x2126c1, 0x0 }, | |
| 2007 | + { 0x127c1, 0x0 }, | |
| 2008 | + { 0x1127c1, 0x0 }, | |
| 2009 | + { 0x2127c1, 0x0 }, | |
| 2010 | + { 0x128c1, 0x0 }, | |
| 2011 | + { 0x1128c1, 0x0 }, | |
| 2012 | + { 0x2128c1, 0x0 }, | |
| 2013 | + { 0x130c1, 0x0 }, | |
| 2014 | + { 0x1130c1, 0x0 }, | |
| 2015 | + { 0x2130c1, 0x0 }, | |
| 2016 | + { 0x131c1, 0x0 }, | |
| 2017 | + { 0x1131c1, 0x0 }, | |
| 2018 | + { 0x2131c1, 0x0 }, | |
| 2019 | + { 0x132c1, 0x0 }, | |
| 2020 | + { 0x1132c1, 0x0 }, | |
| 2021 | + { 0x2132c1, 0x0 }, | |
| 2022 | + { 0x133c1, 0x0 }, | |
| 2023 | + { 0x1133c1, 0x0 }, | |
| 2024 | + { 0x2133c1, 0x0 }, | |
| 2025 | + { 0x134c1, 0x0 }, | |
| 2026 | + { 0x1134c1, 0x0 }, | |
| 2027 | + { 0x2134c1, 0x0 }, | |
| 2028 | + { 0x135c1, 0x0 }, | |
| 2029 | + { 0x1135c1, 0x0 }, | |
| 2030 | + { 0x2135c1, 0x0 }, | |
| 2031 | + { 0x136c1, 0x0 }, | |
| 2032 | + { 0x1136c1, 0x0 }, | |
| 2033 | + { 0x2136c1, 0x0 }, | |
| 2034 | + { 0x137c1, 0x0 }, | |
| 2035 | + { 0x1137c1, 0x0 }, | |
| 2036 | + { 0x2137c1, 0x0 }, | |
| 2037 | + { 0x138c1, 0x0 }, | |
| 2038 | + { 0x1138c1, 0x0 }, | |
| 2039 | + { 0x2138c1, 0x0 }, | |
| 2040 | + { 0x10020, 0x0 }, | |
| 2041 | + { 0x110020, 0x0 }, | |
| 2042 | + { 0x210020, 0x0 }, | |
| 2043 | + { 0x11020, 0x0 }, | |
| 2044 | + { 0x111020, 0x0 }, | |
| 2045 | + { 0x211020, 0x0 }, | |
| 2046 | + { 0x12020, 0x0 }, | |
| 2047 | + { 0x112020, 0x0 }, | |
| 2048 | + { 0x212020, 0x0 }, | |
| 2049 | + { 0x13020, 0x0 }, | |
| 2050 | + { 0x113020, 0x0 }, | |
| 2051 | + { 0x213020, 0x0 }, | |
| 2052 | + { 0x20072, 0x0 }, | |
| 2053 | + { 0x20073, 0x0 }, | |
| 2054 | + { 0x20074, 0x0 }, | |
| 2055 | + { 0x100aa, 0x0 }, | |
| 2056 | + { 0x110aa, 0x0 }, | |
| 2057 | + { 0x120aa, 0x0 }, | |
| 2058 | + { 0x130aa, 0x0 }, | |
| 2059 | + { 0x20010, 0x0 }, | |
| 2060 | + { 0x120010, 0x0 }, | |
| 2061 | + { 0x220010, 0x0 }, | |
| 2062 | + { 0x20011, 0x0 }, | |
| 2063 | + { 0x120011, 0x0 }, | |
| 2064 | + { 0x220011, 0x0 }, | |
| 2065 | + { 0x100ae, 0x0 }, | |
| 2066 | + { 0x1100ae, 0x0 }, | |
| 2067 | + { 0x2100ae, 0x0 }, | |
| 2068 | + { 0x100af, 0x0 }, | |
| 2069 | + { 0x1100af, 0x0 }, | |
| 2070 | + { 0x2100af, 0x0 }, | |
| 2071 | + { 0x110ae, 0x0 }, | |
| 2072 | + { 0x1110ae, 0x0 }, | |
| 2073 | + { 0x2110ae, 0x0 }, | |
| 2074 | + { 0x110af, 0x0 }, | |
| 2075 | + { 0x1110af, 0x0 }, | |
| 2076 | + { 0x2110af, 0x0 }, | |
| 2077 | + { 0x120ae, 0x0 }, | |
| 2078 | + { 0x1120ae, 0x0 }, | |
| 2079 | + { 0x2120ae, 0x0 }, | |
| 2080 | + { 0x120af, 0x0 }, | |
| 2081 | + { 0x1120af, 0x0 }, | |
| 2082 | + { 0x2120af, 0x0 }, | |
| 2083 | + { 0x130ae, 0x0 }, | |
| 2084 | + { 0x1130ae, 0x0 }, | |
| 2085 | + { 0x2130ae, 0x0 }, | |
| 2086 | + { 0x130af, 0x0 }, | |
| 2087 | + { 0x1130af, 0x0 }, | |
| 2088 | + { 0x2130af, 0x0 }, | |
| 2089 | + { 0x20020, 0x0 }, | |
| 2090 | + { 0x120020, 0x0 }, | |
| 2091 | + { 0x220020, 0x0 }, | |
| 2092 | + { 0x100a0, 0x0 }, | |
| 2093 | + { 0x100a1, 0x0 }, | |
| 2094 | + { 0x100a2, 0x0 }, | |
| 2095 | + { 0x100a3, 0x0 }, | |
| 2096 | + { 0x100a4, 0x0 }, | |
| 2097 | + { 0x100a5, 0x0 }, | |
| 2098 | + { 0x100a6, 0x0 }, | |
| 2099 | + { 0x100a7, 0x0 }, | |
| 2100 | + { 0x110a0, 0x0 }, | |
| 2101 | + { 0x110a1, 0x0 }, | |
| 2102 | + { 0x110a2, 0x0 }, | |
| 2103 | + { 0x110a3, 0x0 }, | |
| 2104 | + { 0x110a4, 0x0 }, | |
| 2105 | + { 0x110a5, 0x0 }, | |
| 2106 | + { 0x110a6, 0x0 }, | |
| 2107 | + { 0x110a7, 0x0 }, | |
| 2108 | + { 0x120a0, 0x0 }, | |
| 2109 | + { 0x120a1, 0x0 }, | |
| 2110 | + { 0x120a2, 0x0 }, | |
| 2111 | + { 0x120a3, 0x0 }, | |
| 2112 | + { 0x120a4, 0x0 }, | |
| 2113 | + { 0x120a5, 0x0 }, | |
| 2114 | + { 0x120a6, 0x0 }, | |
| 2115 | + { 0x120a7, 0x0 }, | |
| 2116 | + { 0x130a0, 0x0 }, | |
| 2117 | + { 0x130a1, 0x0 }, | |
| 2118 | + { 0x130a2, 0x0 }, | |
| 2119 | + { 0x130a3, 0x0 }, | |
| 2120 | + { 0x130a4, 0x0 }, | |
| 2121 | + { 0x130a5, 0x0 }, | |
| 2122 | + { 0x130a6, 0x0 }, | |
| 2123 | + { 0x130a7, 0x0 }, | |
| 2124 | + { 0x2007c, 0x0 }, | |
| 2125 | + { 0x12007c, 0x0 }, | |
| 2126 | + { 0x22007c, 0x0 }, | |
| 2127 | + { 0x2007d, 0x0 }, | |
| 2128 | + { 0x12007d, 0x0 }, | |
| 2129 | + { 0x22007d, 0x0 }, | |
| 2130 | + { 0x400fd, 0x0 }, | |
| 2131 | + { 0x400c0, 0x0 }, | |
| 2132 | + { 0x90201, 0x0 }, | |
| 2133 | + { 0x190201, 0x0 }, | |
| 2134 | + { 0x290201, 0x0 }, | |
| 2135 | + { 0x90202, 0x0 }, | |
| 2136 | + { 0x190202, 0x0 }, | |
| 2137 | + { 0x290202, 0x0 }, | |
| 2138 | + { 0x90203, 0x0 }, | |
| 2139 | + { 0x190203, 0x0 }, | |
| 2140 | + { 0x290203, 0x0 }, | |
| 2141 | + { 0x90204, 0x0 }, | |
| 2142 | + { 0x190204, 0x0 }, | |
| 2143 | + { 0x290204, 0x0 }, | |
| 2144 | + { 0x90205, 0x0 }, | |
| 2145 | + { 0x190205, 0x0 }, | |
| 2146 | + { 0x290205, 0x0 }, | |
| 2147 | + { 0x90206, 0x0 }, | |
| 2148 | + { 0x190206, 0x0 }, | |
| 2149 | + { 0x290206, 0x0 }, | |
| 2150 | + { 0x90207, 0x0 }, | |
| 2151 | + { 0x190207, 0x0 }, | |
| 2152 | + { 0x290207, 0x0 }, | |
| 2153 | + { 0x90208, 0x0 }, | |
| 2154 | + { 0x190208, 0x0 }, | |
| 2155 | + { 0x290208, 0x0 }, | |
| 2156 | + { 0x10062, 0x0 }, | |
| 2157 | + { 0x10162, 0x0 }, | |
| 2158 | + { 0x10262, 0x0 }, | |
| 2159 | + { 0x10362, 0x0 }, | |
| 2160 | + { 0x10462, 0x0 }, | |
| 2161 | + { 0x10562, 0x0 }, | |
| 2162 | + { 0x10662, 0x0 }, | |
| 2163 | + { 0x10762, 0x0 }, | |
| 2164 | + { 0x10862, 0x0 }, | |
| 2165 | + { 0x11062, 0x0 }, | |
| 2166 | + { 0x11162, 0x0 }, | |
| 2167 | + { 0x11262, 0x0 }, | |
| 2168 | + { 0x11362, 0x0 }, | |
| 2169 | + { 0x11462, 0x0 }, | |
| 2170 | + { 0x11562, 0x0 }, | |
| 2171 | + { 0x11662, 0x0 }, | |
| 2172 | + { 0x11762, 0x0 }, | |
| 2173 | + { 0x11862, 0x0 }, | |
| 2174 | + { 0x12062, 0x0 }, | |
| 2175 | + { 0x12162, 0x0 }, | |
| 2176 | + { 0x12262, 0x0 }, | |
| 2177 | + { 0x12362, 0x0 }, | |
| 2178 | + { 0x12462, 0x0 }, | |
| 2179 | + { 0x12562, 0x0 }, | |
| 2180 | + { 0x12662, 0x0 }, | |
| 2181 | + { 0x12762, 0x0 }, | |
| 2182 | + { 0x12862, 0x0 }, | |
| 2183 | + { 0x13062, 0x0 }, | |
| 2184 | + { 0x13162, 0x0 }, | |
| 2185 | + { 0x13262, 0x0 }, | |
| 2186 | + { 0x13362, 0x0 }, | |
| 2187 | + { 0x13462, 0x0 }, | |
| 2188 | + { 0x13562, 0x0 }, | |
| 2189 | + { 0x13662, 0x0 }, | |
| 2190 | + { 0x13762, 0x0 }, | |
| 2191 | + { 0x13862, 0x0 }, | |
| 2192 | + { 0x20077, 0x0 }, | |
| 2193 | + { 0x10001, 0x0 }, | |
| 2194 | + { 0x11001, 0x0 }, | |
| 2195 | + { 0x12001, 0x0 }, | |
| 2196 | + { 0x13001, 0x0 }, | |
| 2197 | + { 0x10040, 0x0 }, | |
| 2198 | + { 0x10140, 0x0 }, | |
| 2199 | + { 0x10240, 0x0 }, | |
| 2200 | + { 0x10340, 0x0 }, | |
| 2201 | + { 0x10440, 0x0 }, | |
| 2202 | + { 0x10540, 0x0 }, | |
| 2203 | + { 0x10640, 0x0 }, | |
| 2204 | + { 0x10740, 0x0 }, | |
| 2205 | + { 0x10840, 0x0 }, | |
| 2206 | + { 0x10030, 0x0 }, | |
| 2207 | + { 0x10130, 0x0 }, | |
| 2208 | + { 0x10230, 0x0 }, | |
| 2209 | + { 0x10330, 0x0 }, | |
| 2210 | + { 0x10430, 0x0 }, | |
| 2211 | + { 0x10530, 0x0 }, | |
| 2212 | + { 0x10630, 0x0 }, | |
| 2213 | + { 0x10730, 0x0 }, | |
| 2214 | + { 0x10830, 0x0 }, | |
| 2215 | + { 0x11040, 0x0 }, | |
| 2216 | + { 0x11140, 0x0 }, | |
| 2217 | + { 0x11240, 0x0 }, | |
| 2218 | + { 0x11340, 0x0 }, | |
| 2219 | + { 0x11440, 0x0 }, | |
| 2220 | + { 0x11540, 0x0 }, | |
| 2221 | + { 0x11640, 0x0 }, | |
| 2222 | + { 0x11740, 0x0 }, | |
| 2223 | + { 0x11840, 0x0 }, | |
| 2224 | + { 0x11030, 0x0 }, | |
| 2225 | + { 0x11130, 0x0 }, | |
| 2226 | + { 0x11230, 0x0 }, | |
| 2227 | + { 0x11330, 0x0 }, | |
| 2228 | + { 0x11430, 0x0 }, | |
| 2229 | + { 0x11530, 0x0 }, | |
| 2230 | + { 0x11630, 0x0 }, | |
| 2231 | + { 0x11730, 0x0 }, | |
| 2232 | + { 0x11830, 0x0 }, | |
| 2233 | + { 0x12040, 0x0 }, | |
| 2234 | + { 0x12140, 0x0 }, | |
| 2235 | + { 0x12240, 0x0 }, | |
| 2236 | + { 0x12340, 0x0 }, | |
| 2237 | + { 0x12440, 0x0 }, | |
| 2238 | + { 0x12540, 0x0 }, | |
| 2239 | + { 0x12640, 0x0 }, | |
| 2240 | + { 0x12740, 0x0 }, | |
| 2241 | + { 0x12840, 0x0 }, | |
| 2242 | + { 0x12030, 0x0 }, | |
| 2243 | + { 0x12130, 0x0 }, | |
| 2244 | + { 0x12230, 0x0 }, | |
| 2245 | + { 0x12330, 0x0 }, | |
| 2246 | + { 0x12430, 0x0 }, | |
| 2247 | + { 0x12530, 0x0 }, | |
| 2248 | + { 0x12630, 0x0 }, | |
| 2249 | + { 0x12730, 0x0 }, | |
| 2250 | + { 0x12830, 0x0 }, | |
| 2251 | + { 0x13040, 0x0 }, | |
| 2252 | + { 0x13140, 0x0 }, | |
| 2253 | + { 0x13240, 0x0 }, | |
| 2254 | + { 0x13340, 0x0 }, | |
| 2255 | + { 0x13440, 0x0 }, | |
| 2256 | + { 0x13540, 0x0 }, | |
| 2257 | + { 0x13640, 0x0 }, | |
| 2258 | + { 0x13740, 0x0 }, | |
| 2259 | + { 0x13840, 0x0 }, | |
| 2260 | + { 0x13030, 0x0 }, | |
| 2261 | + { 0x13130, 0x0 }, | |
| 2262 | + { 0x13230, 0x0 }, | |
| 2263 | + { 0x13330, 0x0 }, | |
| 2264 | + { 0x13430, 0x0 }, | |
| 2265 | + { 0x13530, 0x0 }, | |
| 2266 | + { 0x13630, 0x0 }, | |
| 2267 | + { 0x13730, 0x0 }, | |
| 2268 | + { 0x13830, 0x0 }, | |
| 2269 | +}; | |
| 2270 | +/* P0 message block paremeter for training firmware */ | |
| 2271 | +struct dram_cfg_param ddr_fsp0_cfg[] = { | |
| 2272 | + { 0xd0000, 0x0 }, | |
| 84751c | 2273 | + { 0x54003, 0xbb8 }, |
| be049f | 2274 | + { 0x54004, 0x2 }, |
| W | 2275 | + { 0x54005, 0x2228 }, |
| 2276 | + { 0x54006, 0x14 }, | |
| 2277 | + { 0x54008, 0x131f }, | |
| 2278 | + { 0x54009, 0xc8 }, | |
| 2279 | + { 0x5400b, 0x2 }, | |
| 2280 | + { 0x5400f, 0x100 }, | |
| 84751c | 2281 | + { 0x54012, 0x110 }, |
| be049f | 2282 | + { 0x54019, 0x2dd4 }, |
| 84751c | 2283 | + { 0x5401a, 0x31 }, |
| be049f | 2284 | + { 0x5401b, 0x4866 }, |
| W | 2285 | + { 0x5401c, 0x4800 }, |
| 2286 | + { 0x5401e, 0x16 }, | |
| 2287 | + { 0x5401f, 0x2dd4 }, | |
| 84751c | 2288 | + { 0x54020, 0x31 }, |
| be049f | 2289 | + { 0x54021, 0x4866 }, |
| W | 2290 | + { 0x54022, 0x4800 }, |
| 2291 | + { 0x54024, 0x16 }, | |
| 2292 | + { 0x5402b, 0x1000 }, | |
| 84751c | 2293 | + { 0x5402c, 0x1 }, |
| be049f | 2294 | + { 0x54032, 0xd400 }, |
| 84751c | 2295 | + { 0x54033, 0x312d }, |
| be049f | 2296 | + { 0x54034, 0x6600 }, |
| W | 2297 | + { 0x54035, 0x48 }, |
| 2298 | + { 0x54036, 0x48 }, | |
| 2299 | + { 0x54037, 0x1600 }, | |
| 2300 | + { 0x54038, 0xd400 }, | |
| 84751c | 2301 | + { 0x54039, 0x312d }, |
| be049f | 2302 | + { 0x5403a, 0x6600 }, |
| W | 2303 | + { 0x5403b, 0x48 }, |
| 2304 | + { 0x5403c, 0x48 }, | |
| 2305 | + { 0x5403d, 0x1600 }, | |
| 2306 | + { 0xd0000, 0x1 }, | |
| 2307 | +}; | |
| 2308 | + | |
| 2309 | + | |
| 2310 | +/* P1 message block paremeter for training firmware */ | |
| 2311 | +struct dram_cfg_param ddr_fsp1_cfg[] = { | |
| 2312 | + { 0xd0000, 0x0 }, | |
| 2313 | + { 0x54002, 0x101 }, | |
| 2314 | + { 0x54003, 0x190 }, | |
| 2315 | + { 0x54004, 0x2 }, | |
| 2316 | + { 0x54005, 0x2228 }, | |
| 2317 | + { 0x54006, 0x14 }, | |
| 2318 | + { 0x54008, 0x121f }, | |
| 2319 | + { 0x54009, 0xc8 }, | |
| 2320 | + { 0x5400b, 0x2 }, | |
| 2321 | + { 0x5400f, 0x100 }, | |
| 84751c | 2322 | + { 0x54012, 0x110 }, |
| be049f | 2323 | + { 0x54019, 0x84 }, |
| W | 2324 | + { 0x5401a, 0x33 }, |
| 2325 | + { 0x5401b, 0x4866 }, | |
| 2326 | + { 0x5401c, 0x4800 }, | |
| 2327 | + { 0x5401e, 0x16 }, | |
| 2328 | + { 0x5401f, 0x84 }, | |
| 2329 | + { 0x54020, 0x33 }, | |
| 2330 | + { 0x54021, 0x4866 }, | |
| 2331 | + { 0x54022, 0x4800 }, | |
| 2332 | + { 0x54024, 0x16 }, | |
| 2333 | + { 0x5402b, 0x1000 }, | |
| 84751c | 2334 | + { 0x5402c, 0x1 }, |
| be049f | 2335 | + { 0x54032, 0x8400 }, |
| W | 2336 | + { 0x54033, 0x3300 }, |
| 2337 | + { 0x54034, 0x6600 }, | |
| 2338 | + { 0x54035, 0x48 }, | |
| 2339 | + { 0x54036, 0x48 }, | |
| 2340 | + { 0x54037, 0x1600 }, | |
| 2341 | + { 0x54038, 0x8400 }, | |
| 2342 | + { 0x54039, 0x3300 }, | |
| 2343 | + { 0x5403a, 0x6600 }, | |
| 2344 | + { 0x5403b, 0x48 }, | |
| 2345 | + { 0x5403c, 0x48 }, | |
| 2346 | + { 0x5403d, 0x1600 }, | |
| 2347 | + { 0xd0000, 0x1 }, | |
| 2348 | +}; | |
| 2349 | + | |
| 2350 | + | |
| 2351 | +/* P2 message block paremeter for training firmware */ | |
| 2352 | +struct dram_cfg_param ddr_fsp2_cfg[] = { | |
| 2353 | + { 0xd0000, 0x0 }, | |
| 2354 | + { 0x54002, 0x102 }, | |
| 2355 | + { 0x54003, 0x64 }, | |
| 2356 | + { 0x54004, 0x2 }, | |
| 2357 | + { 0x54005, 0x2228 }, | |
| 2358 | + { 0x54006, 0x14 }, | |
| 2359 | + { 0x54008, 0x121f }, | |
| 2360 | + { 0x54009, 0xc8 }, | |
| 2361 | + { 0x5400b, 0x2 }, | |
| 2362 | + { 0x5400f, 0x100 }, | |
| 84751c | 2363 | + { 0x54012, 0x110 }, |
| be049f | 2364 | + { 0x54019, 0x84 }, |
| W | 2365 | + { 0x5401a, 0x33 }, |
| 2366 | + { 0x5401b, 0x4866 }, | |
| 2367 | + { 0x5401c, 0x4800 }, | |
| 2368 | + { 0x5401e, 0x16 }, | |
| 2369 | + { 0x5401f, 0x84 }, | |
| 2370 | + { 0x54020, 0x33 }, | |
| 2371 | + { 0x54021, 0x4866 }, | |
| 2372 | + { 0x54022, 0x4800 }, | |
| 2373 | + { 0x54024, 0x16 }, | |
| 2374 | + { 0x5402b, 0x1000 }, | |
| 84751c | 2375 | + { 0x5402c, 0x1 }, |
| be049f | 2376 | + { 0x54032, 0x8400 }, |
| W | 2377 | + { 0x54033, 0x3300 }, |
| 2378 | + { 0x54034, 0x6600 }, | |
| 2379 | + { 0x54035, 0x48 }, | |
| 2380 | + { 0x54036, 0x48 }, | |
| 2381 | + { 0x54037, 0x1600 }, | |
| 2382 | + { 0x54038, 0x8400 }, | |
| 2383 | + { 0x54039, 0x3300 }, | |
| 2384 | + { 0x5403a, 0x6600 }, | |
| 2385 | + { 0x5403b, 0x48 }, | |
| 2386 | + { 0x5403c, 0x48 }, | |
| 2387 | + { 0x5403d, 0x1600 }, | |
| 2388 | + { 0xd0000, 0x1 }, | |
| 2389 | +}; | |
| 2390 | + | |
| 2391 | + | |
| 2392 | +/* P0 2D message block paremeter for training firmware */ | |
| 2393 | +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { | |
| 2394 | + { 0xd0000, 0x0 }, | |
| 84751c | 2395 | + { 0x54003, 0xbb8 }, |
| be049f | 2396 | + { 0x54004, 0x2 }, |
| W | 2397 | + { 0x54005, 0x2228 }, |
| 2398 | + { 0x54006, 0x14 }, | |
| 2399 | + { 0x54008, 0x61 }, | |
| 2400 | + { 0x54009, 0xc8 }, | |
| 2401 | + { 0x5400b, 0x2 }, | |
| 2402 | + { 0x5400f, 0x100 }, | |
| 2403 | + { 0x54010, 0x1f7f }, | |
| 84751c | 2404 | + { 0x54012, 0x110 }, |
| be049f | 2405 | + { 0x54019, 0x2dd4 }, |
| 84751c | 2406 | + { 0x5401a, 0x31 }, |
| be049f | 2407 | + { 0x5401b, 0x4866 }, |
| W | 2408 | + { 0x5401c, 0x4800 }, |
| 2409 | + { 0x5401e, 0x16 }, | |
| 2410 | + { 0x5401f, 0x2dd4 }, | |
| 84751c | 2411 | + { 0x54020, 0x31 }, |
| be049f | 2412 | + { 0x54021, 0x4866 }, |
| W | 2413 | + { 0x54022, 0x4800 }, |
| 2414 | + { 0x54024, 0x16 }, | |
| 2415 | + { 0x5402b, 0x1000 }, | |
| 84751c | 2416 | + { 0x5402c, 0x1 }, |
| be049f | 2417 | + { 0x54032, 0xd400 }, |
| 84751c | 2418 | + { 0x54033, 0x312d }, |
| be049f | 2419 | + { 0x54034, 0x6600 }, |
| W | 2420 | + { 0x54035, 0x48 }, |
| 2421 | + { 0x54036, 0x48 }, | |
| 2422 | + { 0x54037, 0x1600 }, | |
| 2423 | + { 0x54038, 0xd400 }, | |
| 84751c | 2424 | + { 0x54039, 0x312d }, |
| be049f | 2425 | + { 0x5403a, 0x6600 }, |
| W | 2426 | + { 0x5403b, 0x48 }, |
| 2427 | + { 0x5403c, 0x48 }, | |
| 2428 | + { 0x5403d, 0x1600 }, | |
| 2429 | + { 0xd0000, 0x1 }, | |
| 2430 | +}; | |
| 2431 | + | |
| 2432 | +/* DRAM PHY init engine image */ | |
| 2433 | +struct dram_cfg_param ddr_phy_pie[] = { | |
| 2434 | + { 0xd0000, 0x0 }, | |
| 2435 | + { 0x90000, 0x10 }, | |
| 2436 | + { 0x90001, 0x400 }, | |
| 2437 | + { 0x90002, 0x10e }, | |
| 2438 | + { 0x90003, 0x0 }, | |
| 2439 | + { 0x90004, 0x0 }, | |
| 2440 | + { 0x90005, 0x8 }, | |
| 2441 | + { 0x90029, 0xb }, | |
| 2442 | + { 0x9002a, 0x480 }, | |
| 2443 | + { 0x9002b, 0x109 }, | |
| 2444 | + { 0x9002c, 0x8 }, | |
| 2445 | + { 0x9002d, 0x448 }, | |
| 2446 | + { 0x9002e, 0x139 }, | |
| 2447 | + { 0x9002f, 0x8 }, | |
| 2448 | + { 0x90030, 0x478 }, | |
| 2449 | + { 0x90031, 0x109 }, | |
| 2450 | + { 0x90032, 0x0 }, | |
| 2451 | + { 0x90033, 0xe8 }, | |
| 2452 | + { 0x90034, 0x109 }, | |
| 2453 | + { 0x90035, 0x2 }, | |
| 2454 | + { 0x90036, 0x10 }, | |
| 2455 | + { 0x90037, 0x139 }, | |
| 2456 | + { 0x90038, 0xb }, | |
| 2457 | + { 0x90039, 0x7c0 }, | |
| 2458 | + { 0x9003a, 0x139 }, | |
| 2459 | + { 0x9003b, 0x44 }, | |
| 2460 | + { 0x9003c, 0x633 }, | |
| 2461 | + { 0x9003d, 0x159 }, | |
| 2462 | + { 0x9003e, 0x14f }, | |
| 2463 | + { 0x9003f, 0x630 }, | |
| 2464 | + { 0x90040, 0x159 }, | |
| 2465 | + { 0x90041, 0x47 }, | |
| 2466 | + { 0x90042, 0x633 }, | |
| 2467 | + { 0x90043, 0x149 }, | |
| 2468 | + { 0x90044, 0x4f }, | |
| 2469 | + { 0x90045, 0x633 }, | |
| 2470 | + { 0x90046, 0x179 }, | |
| 2471 | + { 0x90047, 0x8 }, | |
| 2472 | + { 0x90048, 0xe0 }, | |
| 2473 | + { 0x90049, 0x109 }, | |
| 2474 | + { 0x9004a, 0x0 }, | |
| 2475 | + { 0x9004b, 0x7c8 }, | |
| 2476 | + { 0x9004c, 0x109 }, | |
| 2477 | + { 0x9004d, 0x0 }, | |
| 2478 | + { 0x9004e, 0x1 }, | |
| 2479 | + { 0x9004f, 0x8 }, | |
| 2480 | + { 0x90050, 0x0 }, | |
| 2481 | + { 0x90051, 0x45a }, | |
| 2482 | + { 0x90052, 0x9 }, | |
| 2483 | + { 0x90053, 0x0 }, | |
| 2484 | + { 0x90054, 0x448 }, | |
| 2485 | + { 0x90055, 0x109 }, | |
| 2486 | + { 0x90056, 0x40 }, | |
| 2487 | + { 0x90057, 0x633 }, | |
| 2488 | + { 0x90058, 0x179 }, | |
| 2489 | + { 0x90059, 0x1 }, | |
| 2490 | + { 0x9005a, 0x618 }, | |
| 2491 | + { 0x9005b, 0x109 }, | |
| 2492 | + { 0x9005c, 0x40c0 }, | |
| 2493 | + { 0x9005d, 0x633 }, | |
| 2494 | + { 0x9005e, 0x149 }, | |
| 2495 | + { 0x9005f, 0x8 }, | |
| 2496 | + { 0x90060, 0x4 }, | |
| 2497 | + { 0x90061, 0x48 }, | |
| 2498 | + { 0x90062, 0x4040 }, | |
| 2499 | + { 0x90063, 0x633 }, | |
| 2500 | + { 0x90064, 0x149 }, | |
| 2501 | + { 0x90065, 0x0 }, | |
| 2502 | + { 0x90066, 0x4 }, | |
| 2503 | + { 0x90067, 0x48 }, | |
| 2504 | + { 0x90068, 0x40 }, | |
| 2505 | + { 0x90069, 0x633 }, | |
| 2506 | + { 0x9006a, 0x149 }, | |
| 2507 | + { 0x9006b, 0x10 }, | |
| 2508 | + { 0x9006c, 0x4 }, | |
| 2509 | + { 0x9006d, 0x18 }, | |
| 2510 | + { 0x9006e, 0x0 }, | |
| 2511 | + { 0x9006f, 0x4 }, | |
| 2512 | + { 0x90070, 0x78 }, | |
| 2513 | + { 0x90071, 0x549 }, | |
| 2514 | + { 0x90072, 0x633 }, | |
| 2515 | + { 0x90073, 0x159 }, | |
| 2516 | + { 0x90074, 0xd49 }, | |
| 2517 | + { 0x90075, 0x633 }, | |
| 2518 | + { 0x90076, 0x159 }, | |
| 2519 | + { 0x90077, 0x94a }, | |
| 2520 | + { 0x90078, 0x633 }, | |
| 2521 | + { 0x90079, 0x159 }, | |
| 2522 | + { 0x9007a, 0x441 }, | |
| 2523 | + { 0x9007b, 0x633 }, | |
| 2524 | + { 0x9007c, 0x149 }, | |
| 2525 | + { 0x9007d, 0x42 }, | |
| 2526 | + { 0x9007e, 0x633 }, | |
| 2527 | + { 0x9007f, 0x149 }, | |
| 2528 | + { 0x90080, 0x1 }, | |
| 2529 | + { 0x90081, 0x633 }, | |
| 2530 | + { 0x90082, 0x149 }, | |
| 2531 | + { 0x90083, 0x0 }, | |
| 2532 | + { 0x90084, 0xe0 }, | |
| 2533 | + { 0x90085, 0x109 }, | |
| 2534 | + { 0x90086, 0xa }, | |
| 2535 | + { 0x90087, 0x10 }, | |
| 2536 | + { 0x90088, 0x109 }, | |
| 2537 | + { 0x90089, 0x9 }, | |
| 2538 | + { 0x9008a, 0x3c0 }, | |
| 2539 | + { 0x9008b, 0x149 }, | |
| 2540 | + { 0x9008c, 0x9 }, | |
| 2541 | + { 0x9008d, 0x3c0 }, | |
| 2542 | + { 0x9008e, 0x159 }, | |
| 2543 | + { 0x9008f, 0x18 }, | |
| 2544 | + { 0x90090, 0x10 }, | |
| 2545 | + { 0x90091, 0x109 }, | |
| 2546 | + { 0x90092, 0x0 }, | |
| 2547 | + { 0x90093, 0x3c0 }, | |
| 2548 | + { 0x90094, 0x109 }, | |
| 2549 | + { 0x90095, 0x18 }, | |
| 2550 | + { 0x90096, 0x4 }, | |
| 2551 | + { 0x90097, 0x48 }, | |
| 2552 | + { 0x90098, 0x18 }, | |
| 2553 | + { 0x90099, 0x4 }, | |
| 2554 | + { 0x9009a, 0x58 }, | |
| 2555 | + { 0x9009b, 0xb }, | |
| 2556 | + { 0x9009c, 0x10 }, | |
| 2557 | + { 0x9009d, 0x109 }, | |
| 2558 | + { 0x9009e, 0x1 }, | |
| 2559 | + { 0x9009f, 0x10 }, | |
| 2560 | + { 0x900a0, 0x109 }, | |
| 2561 | + { 0x900a1, 0x5 }, | |
| 2562 | + { 0x900a2, 0x7c0 }, | |
| 2563 | + { 0x900a3, 0x109 }, | |
| 2564 | + { 0x40000, 0x811 }, | |
| 2565 | + { 0x40020, 0x880 }, | |
| 2566 | + { 0x40040, 0x0 }, | |
| 2567 | + { 0x40060, 0x0 }, | |
| 2568 | + { 0x40001, 0x4008 }, | |
| 2569 | + { 0x40021, 0x83 }, | |
| 2570 | + { 0x40041, 0x4f }, | |
| 2571 | + { 0x40061, 0x0 }, | |
| 2572 | + { 0x40002, 0x4040 }, | |
| 2573 | + { 0x40022, 0x83 }, | |
| 2574 | + { 0x40042, 0x51 }, | |
| 2575 | + { 0x40062, 0x0 }, | |
| 2576 | + { 0x40003, 0x811 }, | |
| 2577 | + { 0x40023, 0x880 }, | |
| 2578 | + { 0x40043, 0x0 }, | |
| 2579 | + { 0x40063, 0x0 }, | |
| 2580 | + { 0x40004, 0x720 }, | |
| 2581 | + { 0x40024, 0xf }, | |
| 2582 | + { 0x40044, 0x1740 }, | |
| 2583 | + { 0x40064, 0x0 }, | |
| 2584 | + { 0x40005, 0x16 }, | |
| 2585 | + { 0x40025, 0x83 }, | |
| 2586 | + { 0x40045, 0x4b }, | |
| 2587 | + { 0x40065, 0x0 }, | |
| 2588 | + { 0x40006, 0x716 }, | |
| 2589 | + { 0x40026, 0xf }, | |
| 2590 | + { 0x40046, 0x2001 }, | |
| 2591 | + { 0x40066, 0x0 }, | |
| 2592 | + { 0x40007, 0x716 }, | |
| 2593 | + { 0x40027, 0xf }, | |
| 2594 | + { 0x40047, 0x2800 }, | |
| 2595 | + { 0x40067, 0x0 }, | |
| 2596 | + { 0x40008, 0x716 }, | |
| 2597 | + { 0x40028, 0xf }, | |
| 2598 | + { 0x40048, 0xf00 }, | |
| 2599 | + { 0x40068, 0x0 }, | |
| 2600 | + { 0x40009, 0x720 }, | |
| 2601 | + { 0x40029, 0xf }, | |
| 2602 | + { 0x40049, 0x1400 }, | |
| 2603 | + { 0x40069, 0x0 }, | |
| 2604 | + { 0x4000a, 0xe08 }, | |
| 2605 | + { 0x4002a, 0xc15 }, | |
| 2606 | + { 0x4004a, 0x0 }, | |
| 2607 | + { 0x4006a, 0x0 }, | |
| 2608 | + { 0x4000b, 0x625 }, | |
| 2609 | + { 0x4002b, 0x15 }, | |
| 2610 | + { 0x4004b, 0x0 }, | |
| 2611 | + { 0x4006b, 0x0 }, | |
| 2612 | + { 0x4000c, 0x4028 }, | |
| 2613 | + { 0x4002c, 0x80 }, | |
| 2614 | + { 0x4004c, 0x0 }, | |
| 2615 | + { 0x4006c, 0x0 }, | |
| 2616 | + { 0x4000d, 0xe08 }, | |
| 2617 | + { 0x4002d, 0xc1a }, | |
| 2618 | + { 0x4004d, 0x0 }, | |
| 2619 | + { 0x4006d, 0x0 }, | |
| 2620 | + { 0x4000e, 0x625 }, | |
| 2621 | + { 0x4002e, 0x1a }, | |
| 2622 | + { 0x4004e, 0x0 }, | |
| 2623 | + { 0x4006e, 0x0 }, | |
| 2624 | + { 0x4000f, 0x4040 }, | |
| 2625 | + { 0x4002f, 0x80 }, | |
| 2626 | + { 0x4004f, 0x0 }, | |
| 2627 | + { 0x4006f, 0x0 }, | |
| 2628 | + { 0x40010, 0x2604 }, | |
| 2629 | + { 0x40030, 0x15 }, | |
| 2630 | + { 0x40050, 0x0 }, | |
| 2631 | + { 0x40070, 0x0 }, | |
| 2632 | + { 0x40011, 0x708 }, | |
| 2633 | + { 0x40031, 0x5 }, | |
| 2634 | + { 0x40051, 0x0 }, | |
| 2635 | + { 0x40071, 0x2002 }, | |
| 2636 | + { 0x40012, 0x8 }, | |
| 2637 | + { 0x40032, 0x80 }, | |
| 2638 | + { 0x40052, 0x0 }, | |
| 2639 | + { 0x40072, 0x0 }, | |
| 2640 | + { 0x40013, 0x2604 }, | |
| 2641 | + { 0x40033, 0x1a }, | |
| 2642 | + { 0x40053, 0x0 }, | |
| 2643 | + { 0x40073, 0x0 }, | |
| 2644 | + { 0x40014, 0x708 }, | |
| 2645 | + { 0x40034, 0xa }, | |
| 2646 | + { 0x40054, 0x0 }, | |
| 2647 | + { 0x40074, 0x2002 }, | |
| 2648 | + { 0x40015, 0x4040 }, | |
| 2649 | + { 0x40035, 0x80 }, | |
| 2650 | + { 0x40055, 0x0 }, | |
| 2651 | + { 0x40075, 0x0 }, | |
| 2652 | + { 0x40016, 0x60a }, | |
| 2653 | + { 0x40036, 0x15 }, | |
| 2654 | + { 0x40056, 0x1200 }, | |
| 2655 | + { 0x40076, 0x0 }, | |
| 2656 | + { 0x40017, 0x61a }, | |
| 2657 | + { 0x40037, 0x15 }, | |
| 2658 | + { 0x40057, 0x1300 }, | |
| 2659 | + { 0x40077, 0x0 }, | |
| 2660 | + { 0x40018, 0x60a }, | |
| 2661 | + { 0x40038, 0x1a }, | |
| 2662 | + { 0x40058, 0x1200 }, | |
| 2663 | + { 0x40078, 0x0 }, | |
| 2664 | + { 0x40019, 0x642 }, | |
| 2665 | + { 0x40039, 0x1a }, | |
| 2666 | + { 0x40059, 0x1300 }, | |
| 2667 | + { 0x40079, 0x0 }, | |
| 2668 | + { 0x4001a, 0x4808 }, | |
| 2669 | + { 0x4003a, 0x880 }, | |
| 2670 | + { 0x4005a, 0x0 }, | |
| 2671 | + { 0x4007a, 0x0 }, | |
| 2672 | + { 0x900a4, 0x0 }, | |
| 2673 | + { 0x900a5, 0x790 }, | |
| 2674 | + { 0x900a6, 0x11a }, | |
| 2675 | + { 0x900a7, 0x8 }, | |
| 2676 | + { 0x900a8, 0x7aa }, | |
| 2677 | + { 0x900a9, 0x2a }, | |
| 2678 | + { 0x900aa, 0x10 }, | |
| 2679 | + { 0x900ab, 0x7b2 }, | |
| 2680 | + { 0x900ac, 0x2a }, | |
| 2681 | + { 0x900ad, 0x0 }, | |
| 2682 | + { 0x900ae, 0x7c8 }, | |
| 2683 | + { 0x900af, 0x109 }, | |
| 2684 | + { 0x900b0, 0x10 }, | |
| 2685 | + { 0x900b1, 0x10 }, | |
| 2686 | + { 0x900b2, 0x109 }, | |
| 2687 | + { 0x900b3, 0x10 }, | |
| 2688 | + { 0x900b4, 0x2a8 }, | |
| 2689 | + { 0x900b5, 0x129 }, | |
| 2690 | + { 0x900b6, 0x8 }, | |
| 2691 | + { 0x900b7, 0x370 }, | |
| 2692 | + { 0x900b8, 0x129 }, | |
| 2693 | + { 0x900b9, 0xa }, | |
| 2694 | + { 0x900ba, 0x3c8 }, | |
| 2695 | + { 0x900bb, 0x1a9 }, | |
| 2696 | + { 0x900bc, 0xc }, | |
| 2697 | + { 0x900bd, 0x408 }, | |
| 2698 | + { 0x900be, 0x199 }, | |
| 2699 | + { 0x900bf, 0x14 }, | |
| 2700 | + { 0x900c0, 0x790 }, | |
| 2701 | + { 0x900c1, 0x11a }, | |
| 2702 | + { 0x900c2, 0x8 }, | |
| 2703 | + { 0x900c3, 0x4 }, | |
| 2704 | + { 0x900c4, 0x18 }, | |
| 2705 | + { 0x900c5, 0xe }, | |
| 2706 | + { 0x900c6, 0x408 }, | |
| 2707 | + { 0x900c7, 0x199 }, | |
| 2708 | + { 0x900c8, 0x8 }, | |
| 2709 | + { 0x900c9, 0x8568 }, | |
| 2710 | + { 0x900ca, 0x108 }, | |
| 2711 | + { 0x900cb, 0x18 }, | |
| 2712 | + { 0x900cc, 0x790 }, | |
| 2713 | + { 0x900cd, 0x16a }, | |
| 2714 | + { 0x900ce, 0x8 }, | |
| 2715 | + { 0x900cf, 0x1d8 }, | |
| 2716 | + { 0x900d0, 0x169 }, | |
| 2717 | + { 0x900d1, 0x10 }, | |
| 2718 | + { 0x900d2, 0x8558 }, | |
| 2719 | + { 0x900d3, 0x168 }, | |
| 2720 | + { 0x900d4, 0x70 }, | |
| 2721 | + { 0x900d5, 0x788 }, | |
| 2722 | + { 0x900d6, 0x16a }, | |
| 2723 | + { 0x900d7, 0x1ff8 }, | |
| 2724 | + { 0x900d8, 0x85a8 }, | |
| 2725 | + { 0x900d9, 0x1e8 }, | |
| 2726 | + { 0x900da, 0x50 }, | |
| 2727 | + { 0x900db, 0x798 }, | |
| 2728 | + { 0x900dc, 0x16a }, | |
| 2729 | + { 0x900dd, 0x60 }, | |
| 2730 | + { 0x900de, 0x7a0 }, | |
| 2731 | + { 0x900df, 0x16a }, | |
| 2732 | + { 0x900e0, 0x8 }, | |
| 2733 | + { 0x900e1, 0x8310 }, | |
| 2734 | + { 0x900e2, 0x168 }, | |
| 2735 | + { 0x900e3, 0x8 }, | |
| 2736 | + { 0x900e4, 0xa310 }, | |
| 2737 | + { 0x900e5, 0x168 }, | |
| 2738 | + { 0x900e6, 0xa }, | |
| 2739 | + { 0x900e7, 0x408 }, | |
| 2740 | + { 0x900e8, 0x169 }, | |
| 2741 | + { 0x900e9, 0x6e }, | |
| 2742 | + { 0x900ea, 0x0 }, | |
| 2743 | + { 0x900eb, 0x68 }, | |
| 2744 | + { 0x900ec, 0x0 }, | |
| 2745 | + { 0x900ed, 0x408 }, | |
| 2746 | + { 0x900ee, 0x169 }, | |
| 2747 | + { 0x900ef, 0x0 }, | |
| 2748 | + { 0x900f0, 0x8310 }, | |
| 2749 | + { 0x900f1, 0x168 }, | |
| 2750 | + { 0x900f2, 0x0 }, | |
| 2751 | + { 0x900f3, 0xa310 }, | |
| 2752 | + { 0x900f4, 0x168 }, | |
| 2753 | + { 0x900f5, 0x1ff8 }, | |
| 2754 | + { 0x900f6, 0x85a8 }, | |
| 2755 | + { 0x900f7, 0x1e8 }, | |
| 2756 | + { 0x900f8, 0x68 }, | |
| 2757 | + { 0x900f9, 0x798 }, | |
| 2758 | + { 0x900fa, 0x16a }, | |
| 2759 | + { 0x900fb, 0x78 }, | |
| 2760 | + { 0x900fc, 0x7a0 }, | |
| 2761 | + { 0x900fd, 0x16a }, | |
| 2762 | + { 0x900fe, 0x68 }, | |
| 2763 | + { 0x900ff, 0x790 }, | |
| 2764 | + { 0x90100, 0x16a }, | |
| 2765 | + { 0x90101, 0x8 }, | |
| 2766 | + { 0x90102, 0x8b10 }, | |
| 2767 | + { 0x90103, 0x168 }, | |
| 2768 | + { 0x90104, 0x8 }, | |
| 2769 | + { 0x90105, 0xab10 }, | |
| 2770 | + { 0x90106, 0x168 }, | |
| 2771 | + { 0x90107, 0xa }, | |
| 2772 | + { 0x90108, 0x408 }, | |
| 2773 | + { 0x90109, 0x169 }, | |
| 2774 | + { 0x9010a, 0x58 }, | |
| 2775 | + { 0x9010b, 0x0 }, | |
| 2776 | + { 0x9010c, 0x68 }, | |
| 2777 | + { 0x9010d, 0x0 }, | |
| 2778 | + { 0x9010e, 0x408 }, | |
| 2779 | + { 0x9010f, 0x169 }, | |
| 2780 | + { 0x90110, 0x0 }, | |
| 2781 | + { 0x90111, 0x8b10 }, | |
| 2782 | + { 0x90112, 0x168 }, | |
| 2783 | + { 0x90113, 0x1 }, | |
| 2784 | + { 0x90114, 0xab10 }, | |
| 2785 | + { 0x90115, 0x168 }, | |
| 2786 | + { 0x90116, 0x0 }, | |
| 2787 | + { 0x90117, 0x1d8 }, | |
| 2788 | + { 0x90118, 0x169 }, | |
| 2789 | + { 0x90119, 0x80 }, | |
| 2790 | + { 0x9011a, 0x790 }, | |
| 2791 | + { 0x9011b, 0x16a }, | |
| 2792 | + { 0x9011c, 0x18 }, | |
| 2793 | + { 0x9011d, 0x7aa }, | |
| 2794 | + { 0x9011e, 0x6a }, | |
| 2795 | + { 0x9011f, 0xa }, | |
| 2796 | + { 0x90120, 0x0 }, | |
| 2797 | + { 0x90121, 0x1e9 }, | |
| 2798 | + { 0x90122, 0x8 }, | |
| 2799 | + { 0x90123, 0x8080 }, | |
| 2800 | + { 0x90124, 0x108 }, | |
| 2801 | + { 0x90125, 0xf }, | |
| 2802 | + { 0x90126, 0x408 }, | |
| 2803 | + { 0x90127, 0x169 }, | |
| 2804 | + { 0x90128, 0xc }, | |
| 2805 | + { 0x90129, 0x0 }, | |
| 2806 | + { 0x9012a, 0x68 }, | |
| 2807 | + { 0x9012b, 0x9 }, | |
| 2808 | + { 0x9012c, 0x0 }, | |
| 2809 | + { 0x9012d, 0x1a9 }, | |
| 2810 | + { 0x9012e, 0x0 }, | |
| 2811 | + { 0x9012f, 0x408 }, | |
| 2812 | + { 0x90130, 0x169 }, | |
| 2813 | + { 0x90131, 0x0 }, | |
| 2814 | + { 0x90132, 0x8080 }, | |
| 2815 | + { 0x90133, 0x108 }, | |
| 2816 | + { 0x90134, 0x8 }, | |
| 2817 | + { 0x90135, 0x7aa }, | |
| 2818 | + { 0x90136, 0x6a }, | |
| 2819 | + { 0x90137, 0x0 }, | |
| 2820 | + { 0x90138, 0x8568 }, | |
| 2821 | + { 0x90139, 0x108 }, | |
| 2822 | + { 0x9013a, 0xb7 }, | |
| 2823 | + { 0x9013b, 0x790 }, | |
| 2824 | + { 0x9013c, 0x16a }, | |
| 2825 | + { 0x9013d, 0x1f }, | |
| 2826 | + { 0x9013e, 0x0 }, | |
| 2827 | + { 0x9013f, 0x68 }, | |
| 2828 | + { 0x90140, 0x8 }, | |
| 2829 | + { 0x90141, 0x8558 }, | |
| 2830 | + { 0x90142, 0x168 }, | |
| 2831 | + { 0x90143, 0xf }, | |
| 2832 | + { 0x90144, 0x408 }, | |
| 2833 | + { 0x90145, 0x169 }, | |
| 2834 | + { 0x90146, 0xd }, | |
| 2835 | + { 0x90147, 0x0 }, | |
| 2836 | + { 0x90148, 0x68 }, | |
| 2837 | + { 0x90149, 0x0 }, | |
| 2838 | + { 0x9014a, 0x408 }, | |
| 2839 | + { 0x9014b, 0x169 }, | |
| 2840 | + { 0x9014c, 0x0 }, | |
| 2841 | + { 0x9014d, 0x8558 }, | |
| 2842 | + { 0x9014e, 0x168 }, | |
| 2843 | + { 0x9014f, 0x8 }, | |
| 2844 | + { 0x90150, 0x3c8 }, | |
| 2845 | + { 0x90151, 0x1a9 }, | |
| 2846 | + { 0x90152, 0x3 }, | |
| 2847 | + { 0x90153, 0x370 }, | |
| 2848 | + { 0x90154, 0x129 }, | |
| 2849 | + { 0x90155, 0x20 }, | |
| 2850 | + { 0x90156, 0x2aa }, | |
| 2851 | + { 0x90157, 0x9 }, | |
| 2852 | + { 0x90158, 0x8 }, | |
| 2853 | + { 0x90159, 0xe8 }, | |
| 2854 | + { 0x9015a, 0x109 }, | |
| 2855 | + { 0x9015b, 0x0 }, | |
| 2856 | + { 0x9015c, 0x8140 }, | |
| 2857 | + { 0x9015d, 0x10c }, | |
| 2858 | + { 0x9015e, 0x10 }, | |
| 2859 | + { 0x9015f, 0x8138 }, | |
| 2860 | + { 0x90160, 0x104 }, | |
| 2861 | + { 0x90161, 0x8 }, | |
| 2862 | + { 0x90162, 0x448 }, | |
| 2863 | + { 0x90163, 0x109 }, | |
| 2864 | + { 0x90164, 0xf }, | |
| 2865 | + { 0x90165, 0x7c0 }, | |
| 2866 | + { 0x90166, 0x109 }, | |
| 2867 | + { 0x90167, 0x0 }, | |
| 2868 | + { 0x90168, 0xe8 }, | |
| 2869 | + { 0x90169, 0x109 }, | |
| 2870 | + { 0x9016a, 0x47 }, | |
| 2871 | + { 0x9016b, 0x630 }, | |
| 2872 | + { 0x9016c, 0x109 }, | |
| 2873 | + { 0x9016d, 0x8 }, | |
| 2874 | + { 0x9016e, 0x618 }, | |
| 2875 | + { 0x9016f, 0x109 }, | |
| 2876 | + { 0x90170, 0x8 }, | |
| 2877 | + { 0x90171, 0xe0 }, | |
| 2878 | + { 0x90172, 0x109 }, | |
| 2879 | + { 0x90173, 0x0 }, | |
| 2880 | + { 0x90174, 0x7c8 }, | |
| 2881 | + { 0x90175, 0x109 }, | |
| 2882 | + { 0x90176, 0x8 }, | |
| 2883 | + { 0x90177, 0x8140 }, | |
| 2884 | + { 0x90178, 0x10c }, | |
| 2885 | + { 0x90179, 0x0 }, | |
| 2886 | + { 0x9017a, 0x478 }, | |
| 2887 | + { 0x9017b, 0x109 }, | |
| 2888 | + { 0x9017c, 0x0 }, | |
| 2889 | + { 0x9017d, 0x1 }, | |
| 2890 | + { 0x9017e, 0x8 }, | |
| 2891 | + { 0x9017f, 0x8 }, | |
| 2892 | + { 0x90180, 0x4 }, | |
| 2893 | + { 0x90181, 0x0 }, | |
| 2894 | + { 0x90006, 0x8 }, | |
| 2895 | + { 0x90007, 0x7c8 }, | |
| 2896 | + { 0x90008, 0x109 }, | |
| 2897 | + { 0x90009, 0x0 }, | |
| 2898 | + { 0x9000a, 0x400 }, | |
| 2899 | + { 0x9000b, 0x106 }, | |
| 2900 | + { 0xd00e7, 0x400 }, | |
| 2901 | + { 0x90017, 0x0 }, | |
| 2902 | + { 0x9001f, 0x29 }, | |
| 2903 | + { 0x90026, 0x68 }, | |
| 2904 | + { 0x400d0, 0x0 }, | |
| 2905 | + { 0x400d1, 0x101 }, | |
| 2906 | + { 0x400d2, 0x105 }, | |
| 2907 | + { 0x400d3, 0x107 }, | |
| 2908 | + { 0x400d4, 0x10f }, | |
| 2909 | + { 0x400d5, 0x202 }, | |
| 2910 | + { 0x400d6, 0x20a }, | |
| 2911 | + { 0x400d7, 0x20b }, | |
| 2912 | + { 0x2003a, 0x2 }, | |
| 2913 | + { 0x200be, 0x3 }, | |
| 84751c | 2914 | + { 0x2000b, 0x34b }, |
| G | 2915 | + { 0x2000c, 0xbb }, |
| 2916 | + { 0x2000d, 0x753 }, | |
| be049f | 2917 | + { 0x2000e, 0x2c }, |
| 84751c | 2918 | + { 0x12000b, 0x70 }, |
| be049f | 2919 | + { 0x12000c, 0x19 }, |
| W | 2920 | + { 0x12000d, 0xfa }, |
| 2921 | + { 0x12000e, 0x10 }, | |
| 84751c | 2922 | + { 0x22000b, 0x1c }, |
| be049f | 2923 | + { 0x22000c, 0x6 }, |
| W | 2924 | + { 0x22000d, 0x3e }, |
| 2925 | + { 0x22000e, 0x10 }, | |
| 2926 | + { 0x9000c, 0x0 }, | |
| 2927 | + { 0x9000d, 0x173 }, | |
| 2928 | + { 0x9000e, 0x60 }, | |
| 2929 | + { 0x9000f, 0x6110 }, | |
| 2930 | + { 0x90010, 0x2152 }, | |
| 2931 | + { 0x90011, 0xdfbd }, | |
| 2932 | + { 0x90012, 0x2060 }, | |
| 2933 | + { 0x90013, 0x6152 }, | |
| 2934 | + { 0x20010, 0x5a }, | |
| 2935 | + { 0x20011, 0x3 }, | |
| 2936 | + { 0x40080, 0xe0 }, | |
| 2937 | + { 0x40081, 0x12 }, | |
| 2938 | + { 0x40082, 0xe0 }, | |
| 2939 | + { 0x40083, 0x12 }, | |
| 2940 | + { 0x40084, 0xe0 }, | |
| 2941 | + { 0x40085, 0x12 }, | |
| 2942 | + { 0x140080, 0xe0 }, | |
| 2943 | + { 0x140081, 0x12 }, | |
| 2944 | + { 0x140082, 0xe0 }, | |
| 2945 | + { 0x140083, 0x12 }, | |
| 2946 | + { 0x140084, 0xe0 }, | |
| 2947 | + { 0x140085, 0x12 }, | |
| 2948 | + { 0x240080, 0xe0 }, | |
| 2949 | + { 0x240081, 0x12 }, | |
| 2950 | + { 0x240082, 0xe0 }, | |
| 2951 | + { 0x240083, 0x12 }, | |
| 2952 | + { 0x240084, 0xe0 }, | |
| 2953 | + { 0x240085, 0x12 }, | |
| 2954 | + { 0x400fd, 0xf }, | |
| 2955 | + { 0x10011, 0x1 }, | |
| 2956 | + { 0x10012, 0x1 }, | |
| 2957 | + { 0x10013, 0x180 }, | |
| 2958 | + { 0x10018, 0x1 }, | |
| 2959 | + { 0x10002, 0x6209 }, | |
| 2960 | + { 0x100b2, 0x1 }, | |
| 2961 | + { 0x101b4, 0x1 }, | |
| 2962 | + { 0x102b4, 0x1 }, | |
| 2963 | + { 0x103b4, 0x1 }, | |
| 2964 | + { 0x104b4, 0x1 }, | |
| 2965 | + { 0x105b4, 0x1 }, | |
| 2966 | + { 0x106b4, 0x1 }, | |
| 2967 | + { 0x107b4, 0x1 }, | |
| 2968 | + { 0x108b4, 0x1 }, | |
| 2969 | + { 0x11011, 0x1 }, | |
| 2970 | + { 0x11012, 0x1 }, | |
| 2971 | + { 0x11013, 0x180 }, | |
| 2972 | + { 0x11018, 0x1 }, | |
| 2973 | + { 0x11002, 0x6209 }, | |
| 2974 | + { 0x110b2, 0x1 }, | |
| 2975 | + { 0x111b4, 0x1 }, | |
| 2976 | + { 0x112b4, 0x1 }, | |
| 2977 | + { 0x113b4, 0x1 }, | |
| 2978 | + { 0x114b4, 0x1 }, | |
| 2979 | + { 0x115b4, 0x1 }, | |
| 2980 | + { 0x116b4, 0x1 }, | |
| 2981 | + { 0x117b4, 0x1 }, | |
| 2982 | + { 0x118b4, 0x1 }, | |
| 2983 | + { 0x12011, 0x1 }, | |
| 2984 | + { 0x12012, 0x1 }, | |
| 2985 | + { 0x12013, 0x180 }, | |
| 2986 | + { 0x12018, 0x1 }, | |
| 2987 | + { 0x12002, 0x6209 }, | |
| 2988 | + { 0x120b2, 0x1 }, | |
| 2989 | + { 0x121b4, 0x1 }, | |
| 2990 | + { 0x122b4, 0x1 }, | |
| 2991 | + { 0x123b4, 0x1 }, | |
| 2992 | + { 0x124b4, 0x1 }, | |
| 2993 | + { 0x125b4, 0x1 }, | |
| 2994 | + { 0x126b4, 0x1 }, | |
| 2995 | + { 0x127b4, 0x1 }, | |
| 2996 | + { 0x128b4, 0x1 }, | |
| 2997 | + { 0x13011, 0x1 }, | |
| 2998 | + { 0x13012, 0x1 }, | |
| 2999 | + { 0x13013, 0x180 }, | |
| 3000 | + { 0x13018, 0x1 }, | |
| 3001 | + { 0x13002, 0x6209 }, | |
| 3002 | + { 0x130b2, 0x1 }, | |
| 3003 | + { 0x131b4, 0x1 }, | |
| 3004 | + { 0x132b4, 0x1 }, | |
| 3005 | + { 0x133b4, 0x1 }, | |
| 3006 | + { 0x134b4, 0x1 }, | |
| 3007 | + { 0x135b4, 0x1 }, | |
| 3008 | + { 0x136b4, 0x1 }, | |
| 3009 | + { 0x137b4, 0x1 }, | |
| 3010 | + { 0x138b4, 0x1 }, | |
| 3011 | + { 0x20089, 0x1 }, | |
| 3012 | + { 0x20088, 0x19 }, | |
| 3013 | + { 0xc0080, 0x2 }, | |
| 3014 | + { 0xd0000, 0x1 } | |
| 3015 | +}; | |
| 3016 | + | |
| 3017 | +struct dram_fsp_msg ddr_dram_fsp_msg[] = { | |
| 3018 | + { | |
| 84751c | 3019 | + /* P0 3000mts 1D */ |
| G | 3020 | + .drate = 3000, |
| be049f | 3021 | + .fw_type = FW_1D_IMAGE, |
| W | 3022 | + .fsp_cfg = ddr_fsp0_cfg, |
| 3023 | + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), | |
| 3024 | + }, | |
| 3025 | + { | |
| 3026 | + /* P1 400mts 1D */ | |
| 3027 | + .drate = 400, | |
| 3028 | + .fw_type = FW_1D_IMAGE, | |
| 3029 | + .fsp_cfg = ddr_fsp1_cfg, | |
| 3030 | + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), | |
| 3031 | + }, | |
| 3032 | + { | |
| 3033 | + /* P2 100mts 1D */ | |
| 3034 | + .drate = 100, | |
| 3035 | + .fw_type = FW_1D_IMAGE, | |
| 3036 | + .fsp_cfg = ddr_fsp2_cfg, | |
| 3037 | + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), | |
| 3038 | + }, | |
| 3039 | + { | |
| 84751c | 3040 | + /* P0 3000mts 2D */ |
| G | 3041 | + .drate = 3000, |
| be049f | 3042 | + .fw_type = FW_2D_IMAGE, |
| W | 3043 | + .fsp_cfg = ddr_fsp0_2d_cfg, |
| 3044 | + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), | |
| 3045 | + }, | |
| 3046 | +}; | |
| 3047 | + | |
| 3048 | +/* ddr timing config params */ | |
| 3049 | +struct dram_timing_info dram_timing = { | |
| 3050 | + .ddrc_cfg = ddr_ddrc_cfg, | |
| 3051 | + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), | |
| 3052 | + .ddrphy_cfg = ddr_ddrphy_cfg, | |
| 3053 | + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), | |
| 3054 | + .fsp_msg = ddr_dram_fsp_msg, | |
| 3055 | + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), | |
| 3056 | + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, | |
| 3057 | + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), | |
| 3058 | + .ddrphy_pie = ddr_phy_pie, | |
| 3059 | + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), | |
| 84751c | 3060 | + .fsp_table = { 3000, 400, 100, }, |
| be049f | 3061 | +}; |
| 84751c | 3062 | + |
| be049f | 3063 | diff --git a/board/lingyun/igkboard-imx8mp/spl.c b/board/lingyun/igkboard-imx8mp/spl.c |
| W | 3064 | new file mode 100644 |
| 3065 | index 00000000..362751e2 | |
| 3066 | --- /dev/null | |
| 3067 | +++ b/board/lingyun/igkboard-imx8mp/spl.c | |
| 3068 | @@ -0,0 +1,179 @@ | |
| 3069 | +// SPDX-License-Identifier: GPL-2.0-or-later | |
| 3070 | +/* | |
| 3071 | + * Copyright 2018-2019, 2021 NXP | |
| 3072 | + * | |
| 3073 | + */ | |
| 3074 | + | |
| 3075 | +#include <common.h> | |
| 3076 | +#include <hang.h> | |
| 3077 | +#include <init.h> | |
| 3078 | +#include <log.h> | |
| 3079 | +#include <spl.h> | |
| 3080 | +#include <asm/global_data.h> | |
| 3081 | +#include <asm/arch/imx8mp_pins.h> | |
| 3082 | +#include <asm/arch/sys_proto.h> | |
| 3083 | +#include <asm/mach-imx/boot_mode.h> | |
| 3084 | +#include <power/pmic.h> | |
| 3085 | + | |
| 3086 | +#include <power/pca9450.h> | |
| 3087 | +#include <asm/arch/clock.h> | |
| 3088 | +#include <dm/uclass.h> | |
| 3089 | +#include <dm/device.h> | |
| 3090 | +#include <dm/uclass-internal.h> | |
| 3091 | +#include <dm/device-internal.h> | |
| 3092 | +#include <asm/mach-imx/gpio.h> | |
| 3093 | +#include <asm/mach-imx/iomux-v3.h> | |
| 3094 | +#include <asm/mach-imx/mxc_i2c.h> | |
| 3095 | +#include <fsl_esdhc_imx.h> | |
| 3096 | +#include <mmc.h> | |
| 3097 | +#include <asm/arch/ddr.h> | |
| 3098 | + | |
| 3099 | +DECLARE_GLOBAL_DATA_PTR; | |
| 3100 | + | |
| 3101 | +int spl_board_boot_device(enum boot_device boot_dev_spl) | |
| 3102 | +{ | |
| 3103 | +#ifdef CONFIG_SPL_BOOTROM_SUPPORT | |
| 3104 | + return BOOT_DEVICE_BOOTROM; | |
| 3105 | +#else | |
| 3106 | + switch (boot_dev_spl) { | |
| 3107 | + case SD1_BOOT: | |
| 3108 | + case MMC1_BOOT: | |
| 3109 | + case SD2_BOOT: | |
| 3110 | + case MMC2_BOOT: | |
| 3111 | + return BOOT_DEVICE_MMC1; | |
| 3112 | + case SD3_BOOT: | |
| 3113 | + case MMC3_BOOT: | |
| 3114 | + return BOOT_DEVICE_MMC2; | |
| 3115 | + case QSPI_BOOT: | |
| 3116 | + return BOOT_DEVICE_NOR; | |
| 3117 | + case NAND_BOOT: | |
| 3118 | + return BOOT_DEVICE_NAND; | |
| 3119 | + case USB_BOOT: | |
| 3120 | + return BOOT_DEVICE_BOARD; | |
| 3121 | + default: | |
| 3122 | + return BOOT_DEVICE_NONE; | |
| 3123 | + } | |
| 3124 | +#endif | |
| 3125 | +} | |
| 3126 | + | |
| 3127 | +void spl_dram_init(void) | |
| 3128 | +{ | |
| 3129 | + ddr_init(&dram_timing); | |
| 3130 | +} | |
| 3131 | + | |
| 3132 | +void spl_board_init(void) | |
| 3133 | +{ | |
| 3134 | + arch_misc_init(); | |
| 3135 | + | |
| 3136 | + /* | |
| 3137 | + * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does | |
| 3138 | + * not allow to change it. Should set the clock after PMIC | |
| 3139 | + * setting done. Default is 400Mhz (system_pll1_800m with div = 2) | |
| 3140 | + * set by ROM for ND VDD_SOC | |
| 3141 | + */ | |
| 3142 | +#if defined(CONFIG_IMX8M_LPDDR4) && !defined(CONFIG_IMX8M_VDD_SOC_850MV) | |
| 3143 | + clock_enable(CCGR_GIC, 0); | |
| 3144 | + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); | |
| 3145 | + clock_enable(CCGR_GIC, 1); | |
| 3146 | + | |
| 3147 | + puts("Normal Boot\n"); | |
| 3148 | +#endif | |
| 3149 | +} | |
| 3150 | + | |
| 3151 | +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) | |
| 3152 | +int power_init_board(void) | |
| 3153 | +{ | |
| 3154 | + struct udevice *dev; | |
| 3155 | + int ret; | |
| 3156 | + | |
| 3157 | + ret = pmic_get("pmic@25", &dev); | |
| 3158 | + if (ret == -ENODEV) { | |
| 3159 | + puts("No pca9450@25\n"); | |
| 3160 | + return 0; | |
| 3161 | + } | |
| 3162 | + if (ret != 0) | |
| 3163 | + return ret; | |
| 3164 | + | |
| 3165 | + /* BUCKxOUT_DVS0/1 control BUCK123 output */ | |
| 3166 | + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); | |
| 3167 | + | |
| 3168 | +#ifdef CONFIG_IMX8M_LPDDR4 | |
| 3169 | + /* | |
| 3170 | + * increase VDD_SOC to typical value 0.95V before first | |
| 3171 | + * DRAM access, set DVS1 to 0.85v for suspend. | |
| 3172 | + * Enable DVS control through PMIC_STBY_REQ and | |
| 3173 | + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) | |
| 3174 | + */ | |
| 3175 | +#ifdef CONFIG_IMX8M_VDD_SOC_850MV | |
| 3176 | + /* set DVS0 to 0.85v for special case*/ | |
| 3177 | + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); | |
| 3178 | +#else | |
| 3179 | + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); | |
| 3180 | +#endif | |
| 3181 | + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); | |
| 3182 | + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); | |
| 3183 | + | |
| 3184 | + /* Kernel uses OD/OD freq for SOC */ | |
| 3185 | + /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ | |
| 3186 | + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); | |
| 3187 | +#elif defined(CONFIG_IMX8M_DDR4) | |
| 3188 | + /* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */ | |
| 3189 | + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); | |
| 3190 | + | |
| 3191 | + /* Set NVCC_DRAM to 1.2v for DDR4 */ | |
| 3192 | + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x18); | |
| 3193 | +#endif | |
| 3194 | + | |
| 3195 | + return 0; | |
| 3196 | +} | |
| 3197 | +#endif | |
| 3198 | + | |
| 3199 | +#ifdef CONFIG_SPL_LOAD_FIT | |
| 3200 | +int board_fit_config_name_match(const char *name) | |
| 3201 | +{ | |
| 3202 | + /* Just empty function now - can't decide what to choose */ | |
| 3203 | + debug("%s: %s\n", __func__, name); | |
| 3204 | + | |
| 3205 | + return 0; | |
| 3206 | +} | |
| 3207 | +#endif | |
| 3208 | + | |
| 3209 | +void board_init_f(ulong dummy) | |
| 3210 | +{ | |
| 3211 | + struct udevice *dev; | |
| 3212 | + int ret; | |
| 3213 | + | |
| 3214 | + /* Clear the BSS. */ | |
| 3215 | + memset(__bss_start, 0, __bss_end - __bss_start); | |
| 3216 | + | |
| 3217 | + arch_cpu_init(); | |
| 3218 | + | |
| 3219 | + board_early_init_f(); | |
| 3220 | + | |
| 3221 | + timer_init(); | |
| 3222 | + | |
| 3223 | + ret = spl_early_init(); | |
| 3224 | + if (ret) { | |
| 3225 | + debug("spl_early_init() failed: %d\n", ret); | |
| 3226 | + hang(); | |
| 3227 | + } | |
| 3228 | + | |
| 3229 | + ret = uclass_get_device_by_name(UCLASS_CLK, | |
| 3230 | + "clock-controller@30380000", | |
| 3231 | + &dev); | |
| 3232 | + if (ret < 0) { | |
| 3233 | + printf("Failed to find clock node. Check device tree\n"); | |
| 3234 | + hang(); | |
| 3235 | + } | |
| 3236 | + | |
| 3237 | + preloader_console_init(); | |
| 3238 | + | |
| 3239 | + enable_tzc380(); | |
| 3240 | + | |
| 3241 | + power_init_board(); | |
| 3242 | + | |
| 3243 | + /* DDR initialization */ | |
| 3244 | + spl_dram_init(); | |
| 3245 | + | |
| 3246 | + board_init_r(NULL, 0); | |
| 3247 | +} | |
| 3248 | diff --git a/configs/igkboard-imx8mp_defconfig b/configs/igkboard-imx8mp_defconfig | |
| 3249 | new file mode 100644 | |
| e14437 | 3250 | index 00000000..bea65054 |
| be049f | 3251 | --- /dev/null |
| W | 3252 | +++ b/configs/igkboard-imx8mp_defconfig |
| e14437 | 3253 | @@ -0,0 +1,173 @@ |
| be049f | 3254 | +CONFIG_ARM=y |
| W | 3255 | +CONFIG_ARCH_IMX8M=y |
| 3256 | +CONFIG_TEXT_BASE=0x40200000 | |
| 3257 | +CONFIG_SYS_MALLOC_LEN=0x2000000 | |
| 3258 | +CONFIG_SPL_GPIO=y | |
| 3259 | +CONFIG_SPL_LIBCOMMON_SUPPORT=y | |
| 3260 | +CONFIG_SPL_LIBGENERIC_SUPPORT=y | |
| 2c3d96 | 3261 | +CONFIG_NR_DRAM_BANKS=3 |
| be049f | 3262 | +CONFIG_ENV_SIZE=0x4000 |
| W | 3263 | +CONFIG_ENV_OFFSET=0x700000 |
| 3264 | +CONFIG_DM_GPIO=y | |
| 2c3d96 | 3265 | +CONFIG_DEFAULT_DEVICE_TREE="igkboard-imx8mp" |
| be049f | 3266 | +CONFIG_SPL_TEXT_BASE=0x920000 |
| W | 3267 | +CONFIG_TARGET_IGKBOARD_IMX8MP=y |
| 3268 | +CONFIG_SYS_PROMPT="u-boot=> " | |
| 3269 | +CONFIG_SPL_SERIAL=y | |
| 3270 | +CONFIG_SPL_DRIVERS_MISC=y | |
| 2c3d96 | 3271 | +CONFIG_SPL_STACK=0x96dff0 |
| be049f | 3272 | +CONFIG_SPL=y |
| 2c3d96 | 3273 | +CONFIG_IMX_BOOTAUX=y |
| be049f | 3274 | +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| W | 3275 | +CONFIG_SYS_LOAD_ADDR=0x40400000 |
| 2c3d96 | 3276 | +CONFIG_OF_BOARD_FIXUP=y |
| G | 3277 | +CONFIG_SYS_MEMTEST_START=0x60000000 |
| 3278 | +CONFIG_SYS_MEMTEST_END=0xC0000000 | |
| 3279 | +CONFIG_REMAKE_ELF=y | |
| be049f | 3280 | +CONFIG_SYS_MONITOR_LEN=524288 |
| W | 3281 | +CONFIG_FIT=y |
| 3282 | +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | |
| 3283 | +CONFIG_SPL_LOAD_FIT=y | |
| 2c3d96 | 3284 | +CONFIG_OF_BOARD_SETUP=y |
| be049f | 3285 | +CONFIG_OF_SYSTEM_SETUP=y |
| 2c3d96 | 3286 | +CONFIG_DISTRO_DEFAULTS=y |
| G | 3287 | +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" |
| be049f | 3288 | +CONFIG_DEFAULT_FDT_FILE="igkboard-imx8mp.dtb" |
| W | 3289 | +CONFIG_ARCH_MISC_INIT=y |
| 3290 | +CONFIG_BOARD_EARLY_INIT_F=y | |
| 3291 | +CONFIG_BOARD_LATE_INIT=y | |
| 3292 | +CONFIG_SPL_MAX_SIZE=0x26000 | |
| 3293 | +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y | |
| 3294 | +CONFIG_SPL_BSS_START_ADDR=0x96e000 | |
| 3295 | +CONFIG_SPL_BSS_MAX_SIZE=0x2000 | |
| 3296 | +CONFIG_SPL_BOARD_INIT=y | |
| 3297 | +CONFIG_SPL_BOOTROM_SUPPORT=y | |
| 3298 | +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set | |
| 3299 | +CONFIG_SYS_SPL_MALLOC=y | |
| 3300 | +CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y | |
| 3301 | +CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 | |
| 3302 | +CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 | |
| 3303 | +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y | |
| 3304 | +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 | |
| 3305 | +CONFIG_SPL_I2C=y | |
| 3306 | +CONFIG_SPL_POWER=y | |
| 3307 | +CONFIG_SPL_WATCHDOG=y | |
| 3308 | +CONFIG_SYS_MAXARGS=64 | |
| 3309 | +CONFIG_SYS_CBSIZE=2048 | |
| 3310 | +CONFIG_SYS_PBSIZE=2074 | |
| 2c3d96 | 3311 | +# CONFIG_BOOTM_NETBSD is not set |
| be049f | 3312 | +CONFIG_SYS_BOOTM_LEN=0x2000000 |
| W | 3313 | +# CONFIG_CMD_EXPORTENV is not set |
| 3314 | +# CONFIG_CMD_IMPORTENV is not set | |
| 3315 | +CONFIG_CMD_ERASEENV=y | |
| 3316 | +CONFIG_CRC32_VERIFY=y | |
| 2c3d96 | 3317 | +CONFIG_CMD_MEMTEST=y |
| be049f | 3318 | +CONFIG_CMD_CLK=y |
| W | 3319 | +CONFIG_CMD_FUSE=y |
| 3320 | +CONFIG_CMD_GPIO=y | |
| 3321 | +CONFIG_CMD_I2C=y | |
| 3322 | +CONFIG_CMD_MMC=y | |
| 2c3d96 | 3323 | +CONFIG_CMD_NAND_TRIMFFS=y |
| be049f | 3324 | +CONFIG_CMD_USB=y |
| W | 3325 | +CONFIG_CMD_USB_MASS_STORAGE=y |
| 2c3d96 | 3326 | +CONFIG_CMD_BMP=y |
| G | 3327 | +CONFIG_CMD_CACHE=y |
| 3328 | +CONFIG_CMD_REGULATOR=y | |
| 3329 | +CONFIG_CMD_EXT4_WRITE=y | |
| 3330 | +CONFIG_CMD_MTDPARTS=y | |
| 3331 | +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" | |
| 3332 | +CONFIG_MTDPARTS_SKIP_INVALID=y | |
| 3333 | +CONFIG_CMD_UBI=y | |
| be049f | 3334 | +CONFIG_OF_CONTROL=y |
| W | 3335 | +CONFIG_SPL_OF_CONTROL=y |
| 3336 | +CONFIG_ENV_OVERWRITE=y | |
| 3337 | +CONFIG_ENV_IS_NOWHERE=y | |
| 3338 | +CONFIG_ENV_IS_IN_MMC=y | |
| 3339 | +CONFIG_ENV_IS_IN_NAND=y | |
| 3340 | +CONFIG_SYS_RELOC_GD_ENV_ADDR=y | |
| 3341 | +CONFIG_SYS_MMC_ENV_DEV=1 | |
| 3342 | +CONFIG_USE_ETHPRIME=y | |
| 3343 | +CONFIG_ETHPRIME="eth1" | |
| e14437 | 3344 | +CONFIG_NET_RANDOM_ETHADDR=y |
| G | 3345 | +CONFIG_USE_IPADDR=y |
| 3346 | +CONFIG_IPADDR="192.168.2.28" | |
| 3347 | +CONFIG_USE_NETMASK=y | |
| 3348 | +CONFIG_NETMASK="255.255.255.0" | |
| 3349 | +CONFIG_USE_SERVERIP=y | |
| 3350 | +CONFIG_SERVERIP="192.168.2.2" | |
| be049f | 3351 | +CONFIG_SPL_DM=y |
| W | 3352 | +CONFIG_SPL_CLK_COMPOSITE_CCF=y |
| 3353 | +CONFIG_CLK_COMPOSITE_CCF=y | |
| 3354 | +CONFIG_SPL_CLK_IMX8MP=y | |
| 3355 | +CONFIG_CLK_IMX8MP=y | |
| 3356 | +CONFIG_USB_FUNCTION_FASTBOOT=y | |
| 3357 | +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | |
| 3358 | +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | |
| 3359 | +CONFIG_FASTBOOT_FLASH=y | |
| 2c3d96 | 3360 | +CONFIG_MXC_GPIO=y |
| G | 3361 | +CONFIG_DM_PCA953X=y |
| be049f | 3362 | +CONFIG_DM_I2C=y |
| W | 3363 | +CONFIG_LED=y |
| 3364 | +CONFIG_LED_GPIO=y | |
| 3365 | +CONFIG_SUPPORT_EMMC_BOOT=y | |
| 3366 | +CONFIG_MMC_IO_VOLTAGE=y | |
| 3367 | +CONFIG_MMC_UHS_SUPPORT=y | |
| 3368 | +CONFIG_MMC_HS400_ES_SUPPORT=y | |
| 3369 | +CONFIG_MMC_HS400_SUPPORT=y | |
| 3370 | +CONFIG_FSL_USDHC=y | |
| 2c3d96 | 3371 | +CONFIG_MTD=y |
| G | 3372 | +CONFIG_DM_MTD=y |
| 3373 | +CONFIG_MTD_RAW_NAND=y | |
| 3374 | +CONFIG_SYS_NAND_USE_FLASH_BBT=y | |
| 3375 | +CONFIG_NAND_MXS=y | |
| 3376 | +CONFIG_NAND_MXS_DT=y | |
| 3377 | +CONFIG_NAND_MXS_USE_MINIMUM_ECC=y | |
| 3378 | +CONFIG_SYS_NAND_ONFI_DETECTION=y | |
| be049f | 3379 | +CONFIG_PHY_REALTEK=y |
| W | 3380 | +CONFIG_DM_ETH_PHY=y |
| 3381 | +CONFIG_PHY_GIGE=y | |
| 3382 | +CONFIG_DWC_ETH_QOS=y | |
| 3383 | +CONFIG_DWC_ETH_QOS_IMX=y | |
| 3384 | +CONFIG_FEC_MXC=y | |
| 3385 | +CONFIG_MII=y | |
| 2c3d96 | 3386 | +CONFIG_PHY=y |
| G | 3387 | +CONFIG_PHY_IMX8MQ_USB=y |
| be049f | 3388 | +CONFIG_PINCTRL=y |
| W | 3389 | +CONFIG_SPL_PINCTRL=y |
| 3390 | +CONFIG_PINCTRL_IMX8M=y | |
| 3391 | +CONFIG_POWER_DOMAIN=y | |
| 3392 | +CONFIG_IMX8M_POWER_DOMAIN=y | |
| 2c3d96 | 3393 | +CONFIG_IMX8M_BLK_CTRL=y |
| be049f | 3394 | +CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y |
| W | 3395 | +CONFIG_DM_PMIC=y |
| 3396 | +CONFIG_SPL_DM_PMIC_PCA9450=y | |
| 3397 | +CONFIG_DM_REGULATOR=y | |
| 3398 | +CONFIG_DM_REGULATOR_FIXED=y | |
| 3399 | +CONFIG_DM_REGULATOR_GPIO=y | |
| 3400 | +CONFIG_DM_SERIAL=y | |
| 3401 | +CONFIG_MXC_UART=y | |
| 3402 | +CONFIG_SYSRESET=y | |
| 3403 | +CONFIG_SYSRESET_PSCI=y | |
| 3404 | +CONFIG_DM_THERMAL=y | |
| 3405 | +CONFIG_IMX_TMU=y | |
| 3406 | +CONFIG_USB=y | |
| 2c3d96 | 3407 | +CONFIG_USB_XHCI_HCD=y |
| G | 3408 | +CONFIG_USB_XHCI_DWC3=y |
| 3409 | +CONFIG_USB_DWC3=y | |
| be049f | 3410 | +CONFIG_USB_GADGET=y |
| W | 3411 | +CONFIG_USB_GADGET_MANUFACTURER="FSL" |
| 3412 | +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 | |
| 3413 | +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 | |
| 3414 | +CONFIG_VIDEO=y | |
| 2c3d96 | 3415 | +CONFIG_VIDEO_LOGO=y |
| G | 3416 | +CONFIG_SYS_WHITE_ON_BLACK=y |
| 3417 | +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y | |
| 3418 | +CONFIG_VIDEO_IMX_SEC_DSI=y | |
| 3419 | +CONFIG_VIDEO_IMX_LCDIFV3=y | |
| 3420 | +CONFIG_SPLASH_SCREEN=y | |
| 3421 | +CONFIG_SPLASH_SCREEN_ALIGN=y | |
| be049f | 3422 | +CONFIG_BMP_16BPP=y |
| W | 3423 | +CONFIG_BMP_24BPP=y |
| 3424 | +CONFIG_BMP_32BPP=y | |
| 3425 | +CONFIG_VIDEO_ADV7535=y | |
| 2c3d96 | 3426 | +CONFIG_OF_LIBFDT_OVERLAY=y |
| be049f | 3427 | diff --git a/include/configs/igkboard-imx8mp.h b/include/configs/igkboard-imx8mp.h |
| W | 3428 | new file mode 100644 |
| 335041 | 3429 | index 00000000..17d20930 |
| be049f | 3430 | --- /dev/null |
| W | 3431 | +++ b/include/configs/igkboard-imx8mp.h |
| 335041 | 3432 | @@ -0,0 +1,81 @@ |
| be049f | 3433 | +/* SPDX-License-Identifier: GPL-2.0+ */ |
| W | 3434 | +/* |
| e14437 | 3435 | + * Copyright (C) 2023 LingYun IoT System Studio |
| G | 3436 | + * |
| 3437 | + * Configuration settings for LingYun IGKBoard(IoT Gateway Kits Board) based on i.MX8MP | |
| be049f | 3438 | + */ |
| W | 3439 | + |
| 3440 | +#ifndef __IGKBOARD_IMX8MP_H | |
| 3441 | +#define __IGKBOARD_IMX8MP_H | |
| 3442 | + | |
| 3443 | +#include <linux/sizes.h> | |
| 3444 | +#include <linux/stringify.h> | |
| 3445 | +#include <asm/arch/imx-regs.h> | |
| 3446 | +#include "imx_env.h" | |
| 3447 | + | |
| 3448 | +#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) | |
| 3449 | + | |
| 3450 | +#if defined(CONFIG_CMD_NET) | |
| e14437 | 3451 | +#define CFG_FEC_MXC_PHYADDR -1 |
| G | 3452 | +#define PHY_ANEG_TIMEOUT 20000 |
| be049f | 3453 | +#endif |
| W | 3454 | + |
| 3455 | +#define CFG_MFG_ENV_SETTINGS \ | |
| 3456 | + CFG_MFG_ENV_SETTINGS_DEFAULT \ | |
| 3457 | + "initrd_addr=0x43800000\0" \ | |
| 3458 | + "initrd_high=0xffffffffffffffff\0" \ | |
| 3459 | + "emmc_dev=2\0"\ | |
| 3460 | + "sd_dev=1\0" | |
| 3461 | + | |
| 3462 | + | |
| 3463 | +/* Initial environment variables */ | |
| 3464 | +#define CFG_EXTRA_ENV_SETTINGS \ | |
| 3465 | + CFG_MFG_ENV_SETTINGS \ | |
| 3466 | + "prepare_mcore=setenv mcore_clk clk-imx8mp.mcore_booted;\0" \ | |
| 3467 | + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ | |
| 3468 | + "image=Image\0" \ | |
| 3469 | + "splashimage=0x50000000\0" \ | |
| 3470 | + "console=ttymxc1,115200\0" \ | |
| 3471 | + "fdt_addr_r=0x43000000\0" \ | |
| 3472 | + "fdt_addr=0x43000000\0" \ | |
| e14437 | 3473 | + "board=igkboard-imx8mp\0" \ |
| be049f | 3474 | + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ |
| W | 3475 | + "bootm_size=0x10000000\0" \ |
| 335041 | 3476 | + "mmcautodetect=yes\0" \ |
| be049f | 3477 | + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ |
| W | 3478 | + "mmcpart=1\0" \ |
| 335041 | 3479 | + "mmcroot=/dev/mmcblk${mmcdev}p2 rootwait rw\0" \ |
| G | 3480 | + "mmcargs=setenv bootargs console=${console} root=${mmcroot} net.ifnames=0\0" \ |
| be049f | 3481 | + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ |
| e14437 | 3482 | + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile}\0" \ |
| G | 3483 | + "bootos=booti ${loadaddr} - ${fdt_addr}\0" \ |
| 3484 | + "mmcboot=mmc dev ${mmcdev};run mmcargs;run loadimage;run loadfdt;run bootos\0" \ | |
| 3485 | + "netboot=tftp $loadaddr $image; tftp $fdt_addr ${fdtfile}; run mmcargs; run bootos\0" \ | |
| 3486 | + "bbl=tftp ${loadaddr} u-boot-${board}.imx && mmc dev ${mmcdev} 1 && mmc write ${loadaddr} 2 0x800\0" \ | |
| 3487 | + "bdtb=tftp $fdt_addr $fdtfile && fatwrite mmc 1:1 $fdt_addr $fdtfile $filesize\0" \ | |
| 3488 | + "bker=tftp $loadaddr $image&& fatwrite mmc 1:1 $loadaddr $image $filesize\0" \ | |
| 3489 | + "bsys=run bdtb && run bker\0" | |
| 3490 | + | |
| 3491 | +#undef CONFIG_BOOTCOMMAND | |
| 3492 | +#define CONFIG_BOOTCOMMAND "mmc dev ${mmcdev}; mmc rescan; run mmcargs; run loadimage; run loadfdt; run bootos" | |
| be049f | 3493 | + |
| W | 3494 | +/* Link Definitions */ |
| 3495 | + | |
| 3496 | +#define CFG_SYS_INIT_RAM_ADDR 0x40000000 | |
| 3497 | +#define CFG_SYS_INIT_RAM_SIZE 0x80000 | |
| 3498 | + | |
| 3499 | + | |
| 7640c6 | 3500 | +/* Totally 2GB DDR */ |
| be049f | 3501 | +#define CFG_SYS_SDRAM_BASE 0x40000000 |
| 7640c6 | 3502 | +#define PHYS_SDRAM 0x40000000 |
| G | 3503 | +#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */ |
| be049f | 3504 | + |
| W | 3505 | +#define CFG_MXC_UART_BASE UART2_BASE_ADDR |
| 3506 | + | |
| 3507 | +#define CFG_SYS_FSL_USDHC_NUM 2 | |
| 3508 | + | |
| 3509 | +#ifdef CONFIG_ANDROID_SUPPORT | |
| 3510 | +#include "imx8mp_evk_android.h" | |
| 3511 | +#endif | |
| 3512 | + | |
| 3513 | +#endif | |
