build-imxboard.git

Patch:IGKBoard-IMX8MP: Add MS1112 ADC driver

guowenxue

2024-07-17 2f7a23d91dbc2c1c0a29839d791b73eb516c0002

commit \| author \| age
7d0d56	1	diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
W	2	index 7b1a129e6..1d5c6e770 100644
	3	--- a/arch/arm64/boot/dts/freescale/Makefile
	4	+++ b/arch/arm64/boot/dts/freescale/Makefile
	5	@@ -412,3 +412,5 @@ dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb \
	6	s32v234-sbc.dtb
	7	dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-sof-cs42888.dtb imx8qm-mek-sof-wm8960.dtb \
	8	imx8qm-mek-revd-sof-wm8962.dtb imx8qm-mek-sof.dtb
	9	+
	10	+dtb-$(CONFIG_ARCH_MXC) += igkboard-imx8mp.dtb
	11	diff --git a/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts b/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts
	12	new file mode 100644
2f7a23	13	index 000000000..8ce653b69
7d0d56	14	--- /dev/null
W	15	+++ b/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts
2f7a23	16	@@ -0,0 +1,712 @@
7d0d56	17	+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6f4428	18	+/*
G	19	+ * Device Tree Source for LingYun IGKBoard(IoT Gateway Kits Board) - imx8mp
7d0d56	20	+ * Copyright 2023 LingYun IoT System Studio.
W	21	+ */
	22	+
	23	+/dts-v1/;
	24	+
	25	+#include <dt-bindings/usb/pd.h>
	26	+#include "imx8mp.dtsi"
	27	+
	28	+/*+------------------------+
	29	+ \| root node \|
	30	+ +------------------------+*/
	31	+/ {
	32	+ model = "LingYun IoT Gateway Kits Board based on i.MX8MP";
	33	+ compatible = "lingyun,igkboard-imx8mp", "fsl,imx8mp";
	34	+
6f4428	35	+ /* console */
7d0d56	36	+ chosen {
W	37	+ stdout-path = &uart2;
	38	+ };
	39	+
	40	+ /* MT53D512M32D2DS-053 WT:D, 2GB LPDDR4 */
	41	+ memory@80000000 {
	42	+ device_type = "memory";
6f4428	43	+ reg = <0x0 0x80000000 0 0x40000000>;
7d0d56	44	+ };
W	45	+
	46	+ leds {
	47	+ compatible = "gpio-leds";
	48	+ pinctrl-names = "default";
	49	+ pinctrl-0 = <&pinctrl_leds>;
	50	+ status = "okay";
	51	+
	52	+ sysled {
	53	+ label = "sysled";
	54	+ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
7872ca	55	+ default-state = "on";
G	56	+ linux,default-trigger = "heartbeat";
	57	+ };
	58	+
	59	+ ledred {
	60	+ label = "redled";
	61	+ gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
	62	+ default-state = "off";
	63	+ };
	64	+
	65	+ ledgreen {
	66	+ label = "greenled";
	67	+ gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
	68	+ default-state = "off";
	69	+ };
	70	+
	71	+ ledblue {
	72	+ label = "blueled";
	73	+ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
	74	+ default-state = "on";
f77a70	75	+ linux,default-trigger = "timer";
7872ca	76	+ };
G	77	+ };
	78	+
	79	+ keys {
	80	+ compatible = "gpio-keys";
	81	+ pinctrl-names = "default";
	82	+ pinctrl-0 = <&pinctrl_keys>;
	83	+ status = "okay";
	84	+
	85	+ key1 {
	86	+ label = "K1";
	87	+ gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
	88	+ linux,code = <BTN_1>;
	89	+ };
	90	+
	91	+ key2 {
	92	+ label = "K2";
	93	+ gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
	94	+ linux,code = <BTN_2>;
	95	+ };
	96	+
	97	+ key3 {
	98	+ label = "K3";
	99	+ gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
	100	+ linux,code = <BTN_3>;
	101	+ };
	102	+
	103	+ key4 {
	104	+ label = "K4";
	105	+ gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
	106	+ linux,code = <BTN_4>;
7d0d56	107	+ };
W	108	+ };
	109	+};
	110	+
	111	+/*+------------------------+
	112	+ \| power key & reset \|
	113	+ +------------------------+*/
	114	+
	115	+&snvs_pwrkey {
	116	+ status = "okay";
	117	+};
	118	+
	119	+&wdog1 {
	120	+ pinctrl-names = "default";
	121	+ pinctrl-0 = <&pinctrl_wdog>;
	122	+ fsl,ext-reset-output;
	123	+ status = "okay";
	124	+};
	125	+
	126	+/*+------------------------+
	127	+ \| console usart2 \|
	128	+ +------------------------+*/
	129	+&uart2 {
	130	+ pinctrl-names = "default";
	131	+ pinctrl-0 = <&pinctrl_uart2>;
	132	+ status = "okay";
	133	+};
	134	+
	135	+/*+------------------------+
	136	+ \| 8GB eMMC on SD3 \|
	137	+ +------------------------+*/
	138	+
	139	+/* KLM8G1GETF-B041 8GB eMMC */
	140	+&usdhc3 {
	141	+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
	142	+ pinctrl-0 = <&pinctrl_usdhc3>;
	143	+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	144	+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	145	+ bus-width = <8>;
	146	+ non-removable;
	147	+ status = "okay";
	148	+};
	149	+
	150	+/*+------------------------+
	151	+ \| TF Card on SD2 \|
	152	+ +------------------------+*/
	153	+
	154	+&usdhc2 {
	155	+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
	156	+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	157	+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	158	+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	159	+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	160	+ bus-width = <4>;
	161	+ no-1-8-v;
	162	+ status = "okay";
	163	+};
	164	+
	165	+/*+------------------------+
	166	+ \| Typec USB for download \|
	167	+ +------------------------+*/
	168	+
	169	+&usb3_phy0 {
	170	+ fsl,phy-tx-vref-tune = <6>;
	171	+ fsl,phy-tx-rise-tune = <0>;
	172	+ fsl,phy-tx-preemp-amp-tune = <3>;
	173	+ fsl,phy-comp-dis-tune = <7>;
	174	+ fsl,pcs-tx-deemph-3p5db = <0x21>;
	175	+ fsl,phy-pcs-tx-swing-full = <0x7f>;
	176	+ status = "okay";
	177	+};
	178	+
	179	+&usb3_0 {
	180	+ status = "okay";
	181	+};
	182	+
	183	+&usb_dwc3_0 {
	184	+ dr_mode = "peripheral";
	185	+ hnp-disable;
	186	+ srp-disable;
	187	+ adp-disable;
	188	+ status = "okay";
	189	+};
	190	+
	191	+/*+------------------------+
	192	+ \| 2xUSB Host on USB Hub \|
	193	+ +------------------------+*/
	194	+
	195	+/* Renesas USB 3.0 Hub uPD720210 */
	196	+&usb3_phy1 {
	197	+ fsl,phy-tx-preemp-amp-tune = <2>;
	198	+ status = "okay";
	199	+};
	200	+
	201	+&usb3_1 {
	202	+ status = "okay";
	203	+};
	204	+
	205	+&usb_dwc3_1 {
	206	+ dr_mode = "host";
	207	+ status = "okay";
	208	+};
	209	+
	210	+/*+------------------------+
	211	+ \| Ethernet \|
	212	+ +------------------------+*/
	213	+
	214	+/* First 1000Mbps Ethernet For TSN on ENET */
	215	+&eqos {
	216	+ pinctrl-names = "default";
	217	+ pinctrl-0 = <&pinctrl_eqos>;
	218	+ phy-mode = "rgmii-id";
	219	+ phy-handle = <&ethphy0>;
	220	+ status = "okay";
	221	+
	222	+ mdio {
	223	+ compatible = "snps,dwmac-mdio";
	224	+ #address-cells = <1>;
	225	+ #size-cells = <0>;
6f4428	226	+ clock-frequency = <5000000>;
7d0d56	227	+
W	228	+ ethphy0: ethernet-phy@0 { /* YT8521SH-CA */
	229	+ compatible = "ethernet-phy-ieee802.3-c22";
	230	+ reg = <0>;
	231	+ eee-broken-1000t;
	232	+ };
	233	+ };
	234	+};
	235	+
6f4428	236	+/* Second 1000Mbps Ethernet on ENET1, test okay */
7d0d56	237	+&fec {
W	238	+ pinctrl-names = "default";
	239	+ pinctrl-0 = <&pinctrl_fec>;
	240	+ phy-mode = "rgmii-id";
	241	+ phy-handle = <&ethphy1>;
	242	+ fsl,magic-packet;
	243	+ status = "okay";
	244	+
	245	+ mdio {
	246	+ #address-cells = <1>;
	247	+ #size-cells = <0>;
6f4428	248	+ clock-frequency = <5000000>;
7d0d56	249	+
W	250	+ ethphy1: ethernet-phy@0 { /* YT8521SH-CA */
	251	+ compatible = "ethernet-phy-ieee802.3-c22";
	252	+ reg = <0>;
	253	+ eee-broken-1000t;
	254	+ };
	255	+ };
	256	+};
	257	+
	258	+/*+------------------------+
500850	259	+ \| Misc Devices \|
G	260	+ +------------------------+*/
	261	+
	262	+/* Buzzer */
	263	+&pwm1 {
	264	+ pinctrl-names = "default";
	265	+ pinctrl-0 = <&pinctrl_pwm1>;
	266	+ status = "okay";
	267	+};
	268	+
2b23f8	269	+&i2c2 {
G	270	+ clock-frequency = <100000>;
	271	+ pinctrl-names = "default";
	272	+ pinctrl-0 = <&pinctrl_i2c2>;
	273	+ status = "okay";
	274	+
	275	+ rtc1208@6f {
	276	+ compatible = "isil,isl1208";
	277	+ reg = <0x6f>;
	278	+ status = "okay";
2f7a23	279	+ };
G	280	+
	281	+ ms1112@4a {
	282	+ compatible = "ms,ms1112";
	283	+ reg = <0x4a>;
	284	+ status = "okay";
	285	+ #address-cells = <1>;
	286	+ #size-cells = <0>;
	287	+
	288	+ channel@2 {
	289	+ reg = <2>;
	290	+ ti,gain = <0>;
	291	+ ti,datarate = <3>;
	292	+ ti,mode = <1>;
	293	+ };
	294	+
	295	+ channel@3{
	296	+ reg = <3>;
	297	+ ti,gain = <0>;
	298	+ ti,datarate = <3>;
	299	+ ti,mode = <1>;
	300	+ };
2b23f8	301	+ };
G	302	+};
	303	+
500850	304	+/*+------------------------+
ac4b9f	305	+ \| CAN/RS485 interface \|
G	306	+ +------------------------+*/
	307	+/* RS485 */
	308	+&uart3 {
	309	+ pinctrl-names = "default";
	310	+ pinctrl-0 = <&pinctrl_uart3>;
	311	+ status = "okay";
	312	+};
	313	+
	314	+/* CAN */
	315	+&flexcan1 {
	316	+ pinctrl-names = "default";
	317	+ pinctrl-0 = <&pinctrl_flexcan1>;
	318	+ status = "okay";
	319	+};
	320	+
	321	+&flexcan2 {
	322	+ pinctrl-names = "default";
	323	+ pinctrl-0 = <&pinctrl_flexcan2>;
	324	+ status = "okay";
	325	+};
	326	+
	327	+/*+------------------------+
500850	328	+ \| MikroBUS interface \|
G	329	+ +------------------------+*/
	330	+
	331	+/* Same as RPi 40Pin extend interface: #32 */
	332	+&pwm3 {
	333	+ pinctrl-names = "default";
	334	+ pinctrl-0 = <&pinctrl_pwm3>;
	335	+ status = "okay";
	336	+};
	337	+
	338	+/* Same as RPi 40Pin extend interface: #19, #21, #23, #24 */
	339	+&uart1 {
	340	+ pinctrl-names = "default";
	341	+ pinctrl-0 = <&pinctrl_uart1>;
	342	+ assigned-clocks = <&clk IMX8MP_CLK_UART1>;
	343	+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
	344	+ status = "okay";
	345	+};
	346	+
	347	+/* Same as RPi 40Pin extend interface */
	348	+&ecspi2 {
	349	+ #address-cells = <1>;
	350	+ #size-cells = <0>;
	351	+ fsl,spi-num-chipselects = <1>;
	352	+ pinctrl-names = "default";
	353	+ pinctrl-0 = <&pinctrl_ecspi2>;
	354	+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
	355	+ status = "okay";
	356	+
	357	+ spidev@0 {
	358	+ compatible = "fsl,spidev", "semtech,sx1301";
	359	+ reg = <0>;
	360	+ spi-max-frequency = <2000000>;
	361	+ };
	362	+};
	363	+
	364	+/* Same as RPi 40Pin extend interface: #3, #5 */
	365	+&i2c5 {
	366	+ clock-frequency = <100000>;
	367	+ pinctrl-names = "default";
	368	+ pinctrl-0 = <&pinctrl_i2c5>;
	369	+ status = "okay";
2b23f8	370	+
G	371	+ hdc1080@40 {
	372	+ compatible = "ti,hdc1080";
	373	+ reg = <0x40>;
	374	+ status = "okay";
	375	+ };
	376	+
	377	+ eeprom@50 {
	378	+ compatible = "microchip,24c32", "atmel,24c32";
	379	+ reg = <0x50>;
	380	+ pagesize = <32>;
	381	+ num-addresses = <8>;
	382	+ };
500850	383	+};
G	384	+
	385	+/*+------------------------+
7d0d56	386	+ \| PCA9450CHN PMIC \|
W	387	+ +------------------------+*/
	388	+
	389	+&i2c1 {
	390	+ clock-frequency = <400000>;
500850	391	+ pinctrl-names = "default";
7d0d56	392	+ pinctrl-0 = <&pinctrl_i2c1>;
W	393	+ status = "okay";
	394	+
	395	+ pmic@25 {
	396	+ compatible = "nxp,pca9450c";
	397	+ reg = <0x25>;
	398	+ pinctrl-names = "default";
	399	+ pinctrl-0 = <&pinctrl_pmic>;
	400	+ interrupt-parent = <&gpio1>;
	401	+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
	402	+
	403	+ regulators {
	404	+ buck1: BUCK1 {
	405	+ regulator-name = "BUCK1";
	406	+ regulator-min-microvolt = <600000>;
	407	+ regulator-max-microvolt = <2187500>;
	408	+ regulator-boot-on;
	409	+ regulator-always-on;
	410	+ regulator-ramp-delay = <3125>;
	411	+ };
	412	+
	413	+ buck2: BUCK2 {
	414	+ regulator-name = "BUCK2";
	415	+ regulator-min-microvolt = <600000>;
	416	+ regulator-max-microvolt = <2187500>;
	417	+ regulator-boot-on;
	418	+ regulator-always-on;
	419	+ regulator-ramp-delay = <3125>;
	420	+ nxp,dvs-run-voltage = <950000>;
	421	+ nxp,dvs-standby-voltage = <850000>;
	422	+ };
	423	+
	424	+ buck4: BUCK4{
	425	+ regulator-name = "BUCK4";
	426	+ regulator-min-microvolt = <600000>;
	427	+ regulator-max-microvolt = <3400000>;
	428	+ regulator-boot-on;
	429	+ regulator-always-on;
	430	+ };
	431	+
	432	+ buck5: BUCK5{
	433	+ regulator-name = "BUCK5";
	434	+ regulator-min-microvolt = <600000>;
	435	+ regulator-max-microvolt = <3400000>;
	436	+ regulator-boot-on;
	437	+ regulator-always-on;
	438	+ };
	439	+
	440	+ buck6: BUCK6 {
	441	+ regulator-name = "BUCK6";
	442	+ regulator-min-microvolt = <600000>;
	443	+ regulator-max-microvolt = <3400000>;
	444	+ regulator-boot-on;
	445	+ regulator-always-on;
	446	+ };
	447	+
	448	+ ldo1: LDO1 {
	449	+ regulator-name = "LDO1";
	450	+ regulator-min-microvolt = <1600000>;
	451	+ regulator-max-microvolt = <3300000>;
	452	+ regulator-boot-on;
	453	+ regulator-always-on;
	454	+ };
	455	+
	456	+ ldo2: LDO2 {
	457	+ regulator-name = "LDO2";
	458	+ regulator-min-microvolt = <800000>;
	459	+ regulator-max-microvolt = <1150000>;
	460	+ regulator-boot-on;
	461	+ regulator-always-on;
	462	+ };
	463	+
	464	+ ldo3: LDO3 {
	465	+ regulator-name = "LDO3";
	466	+ regulator-min-microvolt = <800000>;
	467	+ regulator-max-microvolt = <3300000>;
	468	+ regulator-boot-on;
	469	+ regulator-always-on;
	470	+ };
	471	+
	472	+ ldo4: LDO4 {
	473	+ regulator-name = "LDO4";
	474	+ regulator-min-microvolt = <800000>;
	475	+ regulator-max-microvolt = <3300000>;
	476	+ regulator-boot-on;
	477	+ regulator-always-on;
	478	+ };
	479	+
	480	+ ldo5: LDO5 {
	481	+ regulator-name = "LDO5";
	482	+ regulator-min-microvolt = <1800000>;
	483	+ regulator-max-microvolt = <3300000>;
	484	+ regulator-boot-on;
	485	+ regulator-always-on;
	486	+ };
	487	+ };
	488	+ };
	489	+};
	490	+
	491	+&iomuxc {
	492	+ pinctrl-names = "default";
	493	+
500850	494	+ pinctrl_wdog: wdoggrp {
G	495	+ fsl,pins = <
	496	+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
	497	+ >;
	498	+ };
	499	+
7d0d56	500	+ pinctrl_leds: ledsgrp {
W	501	+ fsl,pins = <
	502	+ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
7872ca	503	+ MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x140
G	504	+ MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x140
	505	+ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140
	506	+ >;
	507	+ };
	508	+
	509	+ pinctrl_keys: keysgrp {
	510	+ fsl,pins = <
	511	+ MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x140
	512	+ MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140
	513	+ MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x140
	514	+ MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x140
7d0d56	515	+ >;
W	516	+ };
	517	+
500850	518	+ pinctrl_pwm1: pwm1grp {
7d0d56	519	+ fsl,pins = <
500850	520	+ MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT 0x116
G	521	+ >;
	522	+ };
	523	+
	524	+ pinctrl_pwm3: pwm3grp {
	525	+ fsl,pins = <
	526	+ MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x116
	527	+ >;
	528	+ };
	529	+
	530	+ pinctrl_uart1: uart1grp {
	531	+ fsl,pins = <
	532	+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
	533	+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
7d0d56	534	+ >;
W	535	+ };
	536	+
	537	+ pinctrl_uart2: uart2grp {
	538	+ fsl,pins = <
	539	+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
	540	+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
	541	+ >;
	542	+ };
	543	+
ac4b9f	544	+ pinctrl_uart3: uart3grp {
G	545	+ fsl,pins = <
	546	+ MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x82
	547	+ MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x82
	548	+ >;
	549	+ };
	550	+
	551	+ pinctrl_flexcan1: flexcan1grp {
	552	+ fsl,pins = <
	553	+ MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
	554	+ MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
	555	+ >;
	556	+ };
	557	+
	558	+ pinctrl_flexcan2: flexcan2grp {
	559	+ fsl,pins = <
	560	+ MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
	561	+ MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
	562	+ >;
	563	+ };
	564	+
500850	565	+ pinctrl_ecspi2: ecspi2grp {
G	566	+ fsl,pins = <
	567	+ MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
	568	+ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
	569	+ MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
	570	+ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000
	571	+ >;
	572	+ };
	573	+
7d0d56	574	+ pinctrl_i2c1: i2c1grp {
W	575	+ fsl,pins = <
	576	+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
	577	+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
	578	+ >;
	579	+ };
	580	+
2b23f8	581	+ pinctrl_i2c2: i2c2grp {
G	582	+ fsl,pins = <
	583	+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
	584	+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
	585	+ >;
	586	+ };
	587	+
500850	588	+ pinctrl_i2c5: i2c5grp {
7d0d56	589	+ fsl,pins = <
500850	590	+ MX8MP_IOMUXC_SD1_CMD__I2C5_SDA 0x400001c2
G	591	+ MX8MP_IOMUXC_SD1_CLK__I2C5_SCL 0x400001c2
7d0d56	592	+ >;
W	593	+ };
	594	+
	595	+ pinctrl_pmic: pmicirq {
	596	+ fsl,pins = <
	597	+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
	598	+ >;
	599	+ };
	600	+
	601	+ pinctrl_usdhc2_gpio: usdhc2grp-gpio {
	602	+ fsl,pins = <
	603	+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
	604	+ >;
	605	+ };
	606	+
	607	+ pinctrl_usdhc2: usdhc2grp {
	608	+ fsl,pins = <
	609	+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
	610	+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
	611	+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
	612	+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
	613	+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
	614	+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
	615	+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
	616	+ >;
	617	+ };
	618	+
	619	+ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
	620	+ fsl,pins = <
	621	+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
	622	+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
	623	+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
	624	+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
	625	+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
	626	+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
	627	+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
	628	+ >;
	629	+ };
	630	+
	631	+ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
	632	+ fsl,pins = <
	633	+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
	634	+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
	635	+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
	636	+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
	637	+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
	638	+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
	639	+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
	640	+ >;
	641	+ };
	642	+
	643	+ pinctrl_usdhc3: usdhc3grp {
	644	+ fsl,pins = <
	645	+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
	646	+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
	647	+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
	648	+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
	649	+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
	650	+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
	651	+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
	652	+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
	653	+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
	654	+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
	655	+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
	656	+ >;
	657	+ };
	658	+
	659	+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
	660	+ fsl,pins = <
	661	+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
	662	+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
	663	+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
	664	+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
	665	+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
	666	+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
	667	+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
	668	+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
	669	+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
	670	+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
	671	+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
	672	+ >;
	673	+ };
	674	+
	675	+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
	676	+ fsl,pins = <
	677	+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
	678	+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
	679	+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
	680	+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
	681	+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
	682	+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
	683	+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
	684	+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
	685	+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
	686	+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
	687	+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
	688	+ >;
	689	+ };
	690	+
	691	+ pinctrl_eqos: eqosgrp {
	692	+ fsl,pins = <
	693	+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
	694	+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
	695	+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
	696	+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
	697	+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
	698	+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
	699	+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
	700	+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
	701	+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
	702	+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
	703	+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
	704	+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
	705	+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
	706	+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
	707	+ >;
	708	+ };
	709	+
	710	+ pinctrl_fec: fecgrp {
	711	+ fsl,pins = <
	712	+ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
	713	+ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
	714	+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
	715	+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
	716	+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
	717	+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
	718	+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
	719	+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
	720	+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
	721	+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
	722	+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
	723	+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
	724	+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
	725	+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
	726	+ >;
	727	+ };
	728	+};
	729	diff --git a/arch/arm64/configs/igkboard-imx8mp_defconfig b/arch/arm64/configs/igkboard-imx8mp_defconfig
	730	new file mode 100644
2f7a23	731	index 000000000..b0f923742
7d0d56	732	--- /dev/null
W	733	+++ b/arch/arm64/configs/igkboard-imx8mp_defconfig
2f7a23	734	@@ -0,0 +1,1103 @@
7d0d56	735	+CONFIG_SYSVIPC=y
W	736	+CONFIG_POSIX_MQUEUE=y
	737	+CONFIG_AUDIT=y
	738	+CONFIG_NO_HZ_IDLE=y
	739	+CONFIG_HIGH_RES_TIMERS=y
	740	+CONFIG_BPF_SYSCALL=y
	741	+CONFIG_BPF_JIT=y
	742	+CONFIG_PREEMPT=y
	743	+CONFIG_IRQ_TIME_ACCOUNTING=y
	744	+CONFIG_BSD_PROCESS_ACCT=y
	745	+CONFIG_BSD_PROCESS_ACCT_V3=y
	746	+CONFIG_TASKSTATS=y
	747	+CONFIG_TASK_XACCT=y
	748	+CONFIG_TASK_IO_ACCOUNTING=y
	749	+CONFIG_IKCONFIG=y
	750	+CONFIG_IKCONFIG_PROC=y
	751	+CONFIG_NUMA_BALANCING=y
	752	+CONFIG_MEMCG=y
	753	+CONFIG_BLK_CGROUP=y
	754	+CONFIG_CGROUP_PIDS=y
	755	+CONFIG_CGROUP_FREEZER=y
	756	+CONFIG_CGROUP_HUGETLB=y
	757	+CONFIG_CPUSETS=y
	758	+CONFIG_CGROUP_DEVICE=y
	759	+CONFIG_CGROUP_CPUACCT=y
	760	+CONFIG_CGROUP_PERF=y
	761	+CONFIG_CGROUP_BPF=y
f77a70	762	+CONFIG_NAMESPACES=y
7d0d56	763	+CONFIG_USER_NS=y
W	764	+CONFIG_SCHED_AUTOGROUP=y
	765	+CONFIG_RELAY=y
	766	+CONFIG_BLK_DEV_INITRD=y
f77a70	767	+CONFIG_EXPERT=y
7d0d56	768	+CONFIG_KALLSYMS_ALL=y
W	769	+CONFIG_PROFILING=y
	770	+CONFIG_ARCH_KEEMBAY=y
	771	+CONFIG_ARCH_NXP=y
	772	+CONFIG_ARCH_LAYERSCAPE=y
	773	+CONFIG_ARCH_MXC=y
	774	+CONFIG_ARCH_S32=y
	775	+CONFIG_SOC_S32V234=y
	776	+CONFIG_ARM64_VA_BITS_48=y
	777	+CONFIG_SCHED_MC=y
	778	+CONFIG_SCHED_SMT=y
	779	+CONFIG_NUMA=y
	780	+CONFIG_KEXEC=y
	781	+CONFIG_KEXEC_FILE=y
	782	+CONFIG_CRASH_DUMP=y
	783	+CONFIG_XEN=y
	784	+CONFIG_ARCH_FORCE_MAX_ORDER=14
	785	+CONFIG_COMPAT=y
	786	+CONFIG_RANDOMIZE_BASE=y
	787	+CONFIG_PM_DEBUG=y
	788	+CONFIG_PM_TEST_SUSPEND=y
	789	+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
	790	+CONFIG_ENERGY_MODEL=y
	791	+CONFIG_ARM_PSCI_CPUIDLE=y
	792	+CONFIG_CPU_FREQ=y
	793	+CONFIG_CPU_FREQ_STAT=y
	794	+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
	795	+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
	796	+CONFIG_CPU_FREQ_GOV_USERSPACE=y
	797	+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
	798	+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
	799	+CONFIG_CPUFREQ_DT=y
	800	+CONFIG_ACPI_CPPC_CPUFREQ=m
	801	+CONFIG_ARM_SCPI_CPUFREQ=y
	802	+CONFIG_ARM_IMX_CPUFREQ_DT=y
	803	+CONFIG_ARM_SCMI_CPUFREQ=y
	804	+CONFIG_QORIQ_CPUFREQ=y
	805	+CONFIG_ACPI=y
	806	+CONFIG_ACPI_APEI=y
	807	+CONFIG_ACPI_APEI_GHES=y
	808	+CONFIG_ACPI_APEI_MEMORY_FAILURE=y
	809	+CONFIG_ACPI_APEI_EINJ=y
	810	+CONFIG_VIRTUALIZATION=y
	811	+CONFIG_KVM=y
	812	+CONFIG_JUMP_LABEL=y
	813	+CONFIG_MODULES=y
	814	+CONFIG_MODULE_UNLOAD=y
	815	+CONFIG_MODVERSIONS=y
	816	+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
	817	+# CONFIG_COMPAT_BRK is not set
	818	+CONFIG_KSM=y
	819	+CONFIG_MEMORY_FAILURE=y
	820	+CONFIG_TRANSPARENT_HUGEPAGE=y
	821	+CONFIG_NET=y
	822	+CONFIG_PACKET=y
	823	+CONFIG_UNIX=y
	824	+CONFIG_TLS=y
	825	+CONFIG_TLS_DEVICE=y
	826	+CONFIG_INET=y
	827	+CONFIG_IP_MULTICAST=y
	828	+CONFIG_IP_PNP=y
	829	+CONFIG_IP_PNP_DHCP=y
	830	+CONFIG_IP_PNP_BOOTP=y
	831	+CONFIG_IPV6_SIT=m
	832	+CONFIG_NETFILTER=y
	833	+CONFIG_BRIDGE_NETFILTER=m
	834	+CONFIG_NETFILTER_NETLINK_OSF=m
	835	+CONFIG_NF_CONNTRACK=m
	836	+CONFIG_NF_CONNTRACK_EVENTS=y
	837	+CONFIG_NF_TABLES=y
	838	+CONFIG_NF_TABLES_INET=y
	839	+CONFIG_NF_TABLES_NETDEV=y
	840	+CONFIG_NFT_CT=m
	841	+CONFIG_NFT_MASQ=m
	842	+CONFIG_NFT_NAT=m
	843	+CONFIG_NFT_COMPAT=m
	844	+CONFIG_NFT_DUP_NETDEV=m
	845	+CONFIG_NFT_FWD_NETDEV=m
	846	+CONFIG_NF_FLOW_TABLE=m
	847	+CONFIG_NETFILTER_XT_MARK=m
	848	+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
	849	+CONFIG_NETFILTER_XT_TARGET_LOG=m
	850	+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
	851	+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
	852	+CONFIG_NETFILTER_XT_MATCH_IPVS=m
	853	+CONFIG_IP_VS=m
	854	+CONFIG_NF_SOCKET_IPV4=m
	855	+CONFIG_NF_TPROXY_IPV4=m
	856	+CONFIG_IP_NF_IPTABLES=m
	857	+CONFIG_IP_NF_FILTER=m
	858	+CONFIG_IP_NF_TARGET_REJECT=m
	859	+CONFIG_IP_NF_NAT=m
	860	+CONFIG_IP_NF_TARGET_MASQUERADE=m
	861	+CONFIG_IP_NF_MANGLE=m
	862	+CONFIG_NF_SOCKET_IPV6=m
	863	+CONFIG_NF_TPROXY_IPV6=m
	864	+CONFIG_IP6_NF_IPTABLES=m
	865	+CONFIG_IP6_NF_FILTER=m
	866	+CONFIG_IP6_NF_TARGET_REJECT=m
	867	+CONFIG_IP6_NF_MANGLE=m
	868	+CONFIG_IP6_NF_NAT=m
	869	+CONFIG_IP6_NF_TARGET_MASQUERADE=m
	870	+CONFIG_NF_TABLES_BRIDGE=m
	871	+CONFIG_BRIDGE_NF_EBTABLES=m
	872	+CONFIG_BRIDGE=y
	873	+CONFIG_BRIDGE_VLAN_FILTERING=y
	874	+CONFIG_NET_DSA=m
	875	+CONFIG_VLAN_8021Q_GVRP=y
	876	+CONFIG_VLAN_8021Q_MVRP=y
	877	+CONFIG_LLC2=y
	878	+CONFIG_NET_SCHED=y
	879	+CONFIG_NET_SCH_MULTIQ=m
	880	+CONFIG_NET_SCH_CBS=m
	881	+CONFIG_NET_SCH_ETF=m
	882	+CONFIG_NET_SCH_TAPRIO=m
	883	+CONFIG_NET_SCH_MQPRIO=m
	884	+CONFIG_NET_SCH_INGRESS=m
	885	+CONFIG_NET_CLS_BASIC=m
	886	+CONFIG_NET_CLS_U32=m
	887	+CONFIG_NET_CLS_FLOWER=m
	888	+CONFIG_NET_CLS_ACT=y
	889	+CONFIG_NET_ACT_GACT=m
	890	+CONFIG_NET_ACT_MIRRED=m
	891	+CONFIG_NET_ACT_SKBEDIT=m
	892	+CONFIG_NET_ACT_GATE=m
	893	+CONFIG_TSN=y
	894	+CONFIG_QRTR=m
	895	+CONFIG_QRTR_SMD=m
	896	+CONFIG_QRTR_TUN=m
	897	+CONFIG_NET_PKTGEN=m
ac4b9f	898	+CONFIG_CAN=y
G	899	+CONFIG_CAN_ISOTP=y
7d0d56	900	+CONFIG_BT=y
W	901	+CONFIG_BT_RFCOMM=y
	902	+CONFIG_BT_RFCOMM_TTY=y
	903	+CONFIG_BT_BNEP=y
	904	+CONFIG_BT_BNEP_MC_FILTER=y
	905	+CONFIG_BT_BNEP_PROTO_FILTER=y
	906	+CONFIG_BT_HIDP=y
	907	+CONFIG_BT_LEDS=y
	908	+# CONFIG_BT_DEBUGFS is not set
	909	+CONFIG_BT_HCIBTUSB=m
	910	+CONFIG_BT_HCIUART=y
	911	+CONFIG_BT_HCIUART_BCSP=y
	912	+CONFIG_BT_HCIUART_ATH3K=y
	913	+CONFIG_BT_HCIUART_LL=y
	914	+CONFIG_BT_HCIUART_3WIRE=y
	915	+CONFIG_BT_HCIUART_BCM=y
	916	+CONFIG_BT_HCIUART_QCA=y
	917	+CONFIG_BT_HCIVHCI=y
	918	+CONFIG_BT_NXPUART=m
	919	+CONFIG_CFG80211=y
	920	+CONFIG_NL80211_TESTMODE=y
	921	+CONFIG_CFG80211_WEXT=y
	922	+CONFIG_MAC80211=y
	923	+CONFIG_MAC80211_LEDS=y
	924	+CONFIG_NFC=m
	925	+CONFIG_NFC_NCI=m
	926	+CONFIG_NFC_S3FWRN5_I2C=m
	927	+CONFIG_PCI=y
	928	+CONFIG_PCIEPORTBUS=y
	929	+CONFIG_PCI_IOV=y
	930	+CONFIG_PCI_PASID=y
	931	+CONFIG_HOTPLUG_PCI=y
	932	+CONFIG_HOTPLUG_PCI_ACPI=y
	933	+CONFIG_PCI_HOST_GENERIC=y
	934	+CONFIG_PCI_XGENE=y
	935	+CONFIG_PCIE_ALTERA=y
	936	+CONFIG_PCIE_ALTERA_MSI=y
	937	+CONFIG_PCI_HOST_THUNDER_PEM=y
	938	+CONFIG_PCI_HOST_THUNDER_ECAM=y
	939	+CONFIG_PCI_IMX6_HOST=y
	940	+CONFIG_PCI_IMX6_EP=y
	941	+CONFIG_PCI_LAYERSCAPE=y
	942	+CONFIG_PCI_HISI=y
	943	+CONFIG_PCIE_KIRIN=y
	944	+CONFIG_PCI_MESON=m
	945	+CONFIG_PCIE_LAYERSCAPE_GEN4=y
	946	+CONFIG_PCI_ENDPOINT=y
	947	+CONFIG_PCI_ENDPOINT_CONFIGFS=y
	948	+CONFIG_PCI_EPF_TEST=y
	949	+CONFIG_DEVTMPFS=y
	950	+CONFIG_DEVTMPFS_MOUNT=y
	951	+CONFIG_FW_LOADER_USER_HELPER=y
	952	+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
	953	+CONFIG_BRCMSTB_GISB_ARB=y
	954	+CONFIG_VEXPRESS_CONFIG=y
	955	+CONFIG_FSL_MC_UAPI_SUPPORT=y
	956	+CONFIG_ARM_SCMI_PROTOCOL=y
	957	+CONFIG_ARM_SCPI_PROTOCOL=y
	958	+CONFIG_EFI_CAPSULE_LOADER=y
	959	+CONFIG_IMX_DSP=y
	960	+CONFIG_IMX_SCU=y
	961	+CONFIG_IMX_SCU_PD=y
	962	+CONFIG_IMX_EL_ENCLAVE=y
	963	+CONFIG_GNSS=m
	964	+CONFIG_GNSS_MTK_SERIAL=m
	965	+CONFIG_MTD=y
	966	+CONFIG_MTD_CMDLINE_PARTS=y
	967	+CONFIG_MTD_BLOCK=y
	968	+CONFIG_MTD_CFI=y
	969	+CONFIG_MTD_CFI_ADV_OPTIONS=y
	970	+CONFIG_MTD_CFI_INTELEXT=y
	971	+CONFIG_MTD_CFI_AMDSTD=y
	972	+CONFIG_MTD_CFI_STAA=y
	973	+CONFIG_MTD_PHYSMAP=y
	974	+CONFIG_MTD_PHYSMAP_OF=y
	975	+CONFIG_MTD_DATAFLASH=y
	976	+CONFIG_MTD_SST25L=y
	977	+CONFIG_MTD_RAW_NAND=y
	978	+CONFIG_MTD_NAND_DENALI_DT=y
	979	+CONFIG_MTD_NAND_GPMI_NAND=y
	980	+CONFIG_MTD_NAND_FSL_IFC=y
	981	+CONFIG_MTD_SPI_NAND=y
	982	+CONFIG_MTD_SPI_NOR=y
	983	+# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
	984	+CONFIG_MTD_UBI=y
	985	+CONFIG_BLK_DEV_LOOP=y
	986	+CONFIG_BLK_DEV_NBD=m
	987	+CONFIG_XEN_BLKDEV_BACKEND=m
	988	+CONFIG_VIRTIO_BLK=y
	989	+CONFIG_BLK_DEV_NVME=y
	990	+CONFIG_SRAM=y
	991	+CONFIG_PCI_ENDPOINT_TEST=y
2b23f8	992	+CONFIG_EEPROM_AT24=y
7d0d56	993	+CONFIG_UACCE=m
W	994	+# CONFIG_SCSI_PROC_FS is not set
	995	+CONFIG_BLK_DEV_SD=y
	996	+CONFIG_SCSI_SAS_ATA=y
	997	+CONFIG_SCSI_HISI_SAS=y
	998	+CONFIG_SCSI_HISI_SAS_PCI=y
	999	+CONFIG_MEGARAID_SAS=y
	1000	+CONFIG_SCSI_MPT3SAS=m
	1001	+CONFIG_ATA=y
	1002	+CONFIG_SATA_AHCI=y
	1003	+CONFIG_SATA_AHCI_PLATFORM=y
	1004	+CONFIG_AHCI_IMX=y
	1005	+CONFIG_AHCI_CEVA=y
	1006	+CONFIG_AHCI_XGENE=y
	1007	+CONFIG_AHCI_QORIQ=y
	1008	+CONFIG_SATA_SIL24=y
	1009	+CONFIG_PATA_OF_PLATFORM=y
	1010	+CONFIG_MD=y
	1011	+CONFIG_BLK_DEV_MD=m
	1012	+CONFIG_BLK_DEV_DM=m
	1013	+CONFIG_DM_CRYPT=m
	1014	+CONFIG_DM_MIRROR=m
	1015	+CONFIG_DM_ZERO=m
	1016	+CONFIG_NETDEVICES=y
	1017	+CONFIG_MACVLAN=m
	1018	+CONFIG_MACVTAP=m
	1019	+CONFIG_TUN=y
	1020	+CONFIG_VETH=m
	1021	+CONFIG_VIRTIO_NET=y
	1022	+CONFIG_NET_DSA_MSCC_FELIX=m
	1023	+CONFIG_NET_DSA_SJA1105=m
	1024	+CONFIG_NET_DSA_SJA1105_PTP=y
	1025	+CONFIG_NET_DSA_SJA1105_TAS=y
	1026	+CONFIG_NET_DSA_SJA1105_VL=y
	1027	+CONFIG_AMD_XGBE=y
	1028	+CONFIG_ATL1C=m
	1029	+CONFIG_BCMGENET=m
	1030	+CONFIG_BNX2X=m
	1031	+CONFIG_SYSTEMPORT=m
	1032	+CONFIG_MACB=y
	1033	+CONFIG_THUNDER_NIC_PF=y
	1034	+CONFIG_FEC=y
	1035	+CONFIG_FEC_UIO=y
	1036	+CONFIG_FSL_FMAN=y
	1037	+CONFIG_FSL_DPAA_ETH=y
	1038	+CONFIG_FSL_DPAA2_ETH=y
	1039	+CONFIG_FSL_DPAA2_MAC=y
	1040	+CONFIG_FSL_DPAA2_SWITCH=y
	1041	+CONFIG_FSL_ENETC=y
	1042	+CONFIG_FSL_ENETC_VF=y
	1043	+CONFIG_FSL_ENETC_QOS=y
	1044	+CONFIG_ENETC_TSN=y
	1045	+CONFIG_HIX5HD2_GMAC=y
	1046	+CONFIG_HNS_DSAF=y
	1047	+CONFIG_HNS_ENET=y
	1048	+CONFIG_HNS3=y
	1049	+CONFIG_HNS3_HCLGE=y
	1050	+CONFIG_HNS3_ENET=y
	1051	+CONFIG_E1000=y
	1052	+CONFIG_E1000E=y
	1053	+CONFIG_IGB=y
	1054	+CONFIG_IGBVF=y
	1055	+CONFIG_MVMDIO=y
	1056	+CONFIG_SKY2=y
	1057	+CONFIG_MLX4_EN=m
	1058	+CONFIG_MLX5_CORE=m
	1059	+CONFIG_MLX5_CORE_EN=y
	1060	+CONFIG_MSCC_OCELOT_SWITCH=y
	1061	+CONFIG_QCOM_EMAC=m
	1062	+CONFIG_RMNET=m
	1063	+CONFIG_SMC91X=y
	1064	+CONFIG_SMSC911X=y
	1065	+CONFIG_STMMAC_ETH=y
	1066	+CONFIG_DWMAC_GENERIC=m
	1067	+CONFIG_AQUANTIA_PHY=y
	1068	+CONFIG_BROADCOM_PHY=m
	1069	+CONFIG_BCM54140_PHY=m
	1070	+CONFIG_MARVELL_PHY=m
	1071	+CONFIG_MARVELL_10G_PHY=m
	1072	+CONFIG_MICREL_PHY=y
	1073	+CONFIG_MICROSEMI_PHY=y
	1074	+CONFIG_NXP_C45_TJA11XX_PHY=y
	1075	+CONFIG_NXP_TJA11XX_PHY=y
	1076	+CONFIG_AT803X_PHY=y
	1077	+CONFIG_REALTEK_PHY=y
	1078	+CONFIG_ROCKCHIP_PHY=y
	1079	+CONFIG_VITESSE_PHY=y
ac4b9f	1080	+CONFIG_CAN_FLEXCAN=y
7d0d56	1081	+CONFIG_MDIO_BITBANG=y
W	1082	+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
	1083	+CONFIG_MDIO_BUS_MUX_MMIOREG=y
	1084	+CONFIG_USB_PEGASUS=m
	1085	+CONFIG_USB_RTL8150=m
	1086	+CONFIG_USB_RTL8152=y
	1087	+CONFIG_USB_LAN78XX=m
	1088	+CONFIG_USB_USBNET=y
	1089	+CONFIG_USB_NET_AX8817X=m
	1090	+CONFIG_USB_NET_AX88179_178A=m
	1091	+CONFIG_USB_NET_CDCETHER=m
	1092	+CONFIG_USB_NET_CDC_NCM=m
	1093	+CONFIG_USB_NET_DM9601=m
	1094	+CONFIG_USB_NET_SR9800=m
	1095	+CONFIG_USB_NET_SMSC75XX=m
	1096	+CONFIG_USB_NET_SMSC95XX=m
	1097	+CONFIG_USB_NET_NET1080=m
	1098	+CONFIG_USB_NET_PLUSB=m
	1099	+CONFIG_USB_NET_MCS7830=m
	1100	+CONFIG_USB_NET_CDC_SUBSET=m
	1101	+CONFIG_USB_NET_ZAURUS=m
	1102	+CONFIG_HOSTAP=y
	1103	+CONFIG_WL18XX=m
	1104	+CONFIG_WLCORE_SDIO=m
	1105	+CONFIG_XEN_NETDEV_BACKEND=m
	1106	+CONFIG_IVSHMEM_NET=y
	1107	+CONFIG_INPUT_EVDEV=y
	1108	+CONFIG_KEYBOARD_ADC=m
	1109	+CONFIG_KEYBOARD_GPIO=y
	1110	+CONFIG_KEYBOARD_RPMSG=y
	1111	+CONFIG_KEYBOARD_SNVS_PWRKEY=y
	1112	+CONFIG_KEYBOARD_BBNSM_PWRKEY=y
	1113	+CONFIG_KEYBOARD_IMX_SC_KEY=y
	1114	+CONFIG_KEYBOARD_CROS_EC=y
	1115	+CONFIG_INPUT_TOUCHSCREEN=y
	1116	+CONFIG_TOUCHSCREEN_ATMEL_MXT=m
	1117	+CONFIG_TOUCHSCREEN_EXC3000=m
	1118	+CONFIG_TOUCHSCREEN_GOODIX=m
	1119	+CONFIG_TOUCHSCREEN_EDT_FT5X06=m
	1120	+CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=m
	1121	+CONFIG_INPUT_MISC=y
	1122	+CONFIG_INPUT_PWM_BEEPER=m
	1123	+CONFIG_INPUT_PWM_VIBRA=m
	1124	+# CONFIG_SERIO_SERPORT is not set
	1125	+CONFIG_SERIO_AMBAKMI=y
	1126	+CONFIG_LEGACY_PTY_COUNT=16
	1127	+CONFIG_SERIAL_8250=y
	1128	+CONFIG_SERIAL_8250_CONSOLE=y
	1129	+CONFIG_SERIAL_8250_EXTENDED=y
	1130	+CONFIG_SERIAL_8250_SHARE_IRQ=y
	1131	+CONFIG_SERIAL_8250_DW=y
	1132	+CONFIG_SERIAL_OF_PLATFORM=y
	1133	+CONFIG_SERIAL_AMBA_PL011=y
	1134	+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
	1135	+CONFIG_SERIAL_IMX=y
	1136	+CONFIG_SERIAL_IMX_CONSOLE=y
	1137	+CONFIG_SERIAL_XILINX_PS_UART=y
	1138	+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
	1139	+CONFIG_SERIAL_FSL_LPUART=y
	1140	+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
	1141	+CONFIG_SERIAL_FSL_LINFLEXUART=y
	1142	+CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
	1143	+CONFIG_SERIAL_DEV_BUS=y
	1144	+CONFIG_VIRTIO_CONSOLE=y
	1145	+CONFIG_IPMI_HANDLER=m
	1146	+CONFIG_IPMI_DEVICE_INTERFACE=m
	1147	+CONFIG_IPMI_SI=m
	1148	+CONFIG_TCG_TPM=y
	1149	+CONFIG_TCG_TIS_I2C_INFINEON=y
	1150	+CONFIG_I2C_CHARDEV=y
	1151	+CONFIG_I2C_MUX=y
	1152	+CONFIG_I2C_MUX_GPIO=y
	1153	+CONFIG_I2C_MUX_PCA954x=y
	1154	+CONFIG_I2C_DESIGNWARE_PLATFORM=y
	1155	+CONFIG_I2C_GPIO=m
	1156	+CONFIG_I2C_IMX=y
	1157	+CONFIG_I2C_IMX_LPI2C=y
	1158	+CONFIG_I2C_RK3X=y
	1159	+CONFIG_I2C_RPBUS=y
	1160	+CONFIG_I2C_CROS_EC_TUNNEL=y
	1161	+CONFIG_I2C_SLAVE_EEPROM=y
	1162	+CONFIG_I3C=y
	1163	+CONFIG_SVC_I3C_MASTER=y
	1164	+CONFIG_SPI=y
	1165	+CONFIG_SPI_CADENCE_QUADSPI=y
	1166	+CONFIG_SPI_DESIGNWARE=m
	1167	+CONFIG_SPI_DW_DMA=y
	1168	+CONFIG_SPI_DW_MMIO=m
	1169	+CONFIG_SPI_FSL_LPSPI=y
	1170	+CONFIG_SPI_FSL_QUADSPI=y
	1171	+CONFIG_SPI_NXP_FLEXSPI=y
	1172	+CONFIG_SPI_IMX=y
	1173	+CONFIG_SPI_FSL_DSPI=y
	1174	+CONFIG_SPI_PL022=y
	1175	+CONFIG_SPI_ROCKCHIP=y
	1176	+CONFIG_SPI_SPIDEV=y
	1177	+CONFIG_SPI_SLAVE=y
	1178	+CONFIG_SPI_SLAVE_TIME=y
	1179	+CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y
	1180	+CONFIG_SPMI=y
	1181	+CONFIG_PPS_CLIENT_GPIO=y
	1182	+CONFIG_PINCTRL_MAX77620=y
	1183	+CONFIG_PINCTRL_SINGLE=y
	1184	+CONFIG_PINCTRL_IMX8MM=y
	1185	+CONFIG_PINCTRL_IMX8MN=y
	1186	+CONFIG_PINCTRL_IMX8MP=y
	1187	+CONFIG_PINCTRL_IMX8MQ=y
	1188	+CONFIG_PINCTRL_IMX8QM=y
	1189	+CONFIG_PINCTRL_IMX8QXP=y
	1190	+CONFIG_PINCTRL_IMX8DXL=y
	1191	+CONFIG_PINCTRL_IMX8ULP=y
	1192	+CONFIG_PINCTRL_IMX93=y
	1193	+CONFIG_PINCTRL_S32V234=y
f77a70	1194	+CONFIG_GPIO_SYSFS=y
7d0d56	1195	+CONFIG_GPIO_MXC=y
W	1196	+CONFIG_POWER_RESET_BRCMSTB=y
	1197	+CONFIG_POWER_RESET_XGENE=y
	1198	+CONFIG_POWER_RESET_SYSCON=y
	1199	+CONFIG_SYSCON_REBOOT_MODE=y
	1200	+CONFIG_BATTERY_SBS=m
	1201	+CONFIG_BATTERY_BQ27XXX=y
	1202	+CONFIG_BATTERY_MAX17042=m
	1203	+CONFIG_CHARGER_BQ25890=m
	1204	+CONFIG_CHARGER_BQ25980=m
	1205	+CONFIG_SENSORS_ARM_SCMI=y
	1206	+CONFIG_SENSORS_ARM_SCPI=y
	1207	+CONFIG_SENSORS_FP9931=y
	1208	+CONFIG_SENSORS_LM90=m
	1209	+CONFIG_SENSORS_PWM_FAN=m
	1210	+CONFIG_SENSORS_SL28CPLD=m
	1211	+CONFIG_SENSORS_INA2XX=m
	1212	+CONFIG_SENSORS_INA3221=m
	1213	+CONFIG_THERMAL_WRITABLE_TRIPS=y
	1214	+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
	1215	+CONFIG_CPU_THERMAL=y
	1216	+CONFIG_THERMAL_EMULATION=y
	1217	+CONFIG_IMX_SC_THERMAL=y
	1218	+CONFIG_IMX8MM_THERMAL=y
	1219	+CONFIG_DEVICE_THERMAL=y
	1220	+CONFIG_QORIQ_THERMAL=y
	1221	+CONFIG_WATCHDOG=y
	1222	+CONFIG_SL28CPLD_WATCHDOG=m
	1223	+CONFIG_ARM_SP805_WATCHDOG=y
	1224	+CONFIG_ARM_SBSA_WATCHDOG=y
	1225	+CONFIG_DW_WATCHDOG=y
	1226	+CONFIG_IMX2_WDT=y
	1227	+CONFIG_IMX_SC_WDT=y
	1228	+CONFIG_IMX7ULP_WDT=y
	1229	+CONFIG_ARM_SMC_WATCHDOG=y
	1230	+CONFIG_XEN_WDT=y
	1231	+CONFIG_MFD_ADP5585=y
	1232	+CONFIG_MFD_BD9571MWV=y
	1233	+CONFIG_MFD_AXP20X_I2C=y
	1234	+CONFIG_MFD_IMX_FLEXIO=y
	1235	+CONFIG_MFD_HI6421_PMIC=y
	1236	+CONFIG_MFD_FP9931=y
	1237	+CONFIG_MFD_MAX77620=y
	1238	+CONFIG_MFD_MT6397=y
	1239	+CONFIG_MFD_RK808=y
	1240	+CONFIG_MFD_SEC_CORE=y
	1241	+CONFIG_MFD_SL28CPLD=y
	1242	+CONFIG_MFD_ROHM_BD718XX=y
	1243	+CONFIG_MFD_WCD934X=m
	1244	+CONFIG_REGULATOR_FIXED_VOLTAGE=y
	1245	+CONFIG_REGULATOR_AXP20X=y
	1246	+CONFIG_REGULATOR_BD718XX=y
	1247	+CONFIG_REGULATOR_BD9571MWV=y
	1248	+CONFIG_REGULATOR_FAN53555=y
	1249	+CONFIG_REGULATOR_GPIO=y
	1250	+CONFIG_REGULATOR_HI6421V530=y
	1251	+CONFIG_REGULATOR_MAX77620=y
	1252	+CONFIG_REGULATOR_MAX8973=y
	1253	+CONFIG_REGULATOR_FP9931=y
	1254	+CONFIG_REGULATOR_MP8859=y
	1255	+CONFIG_REGULATOR_MT6358=y
	1256	+CONFIG_REGULATOR_MT6397=y
	1257	+CONFIG_REGULATOR_PCA9450=y
	1258	+CONFIG_REGULATOR_PF8X00=y
	1259	+CONFIG_REGULATOR_PFUZE100=y
	1260	+CONFIG_REGULATOR_PWM=y
	1261	+CONFIG_REGULATOR_QCOM_SPMI=y
	1262	+CONFIG_REGULATOR_RK808=y
	1263	+CONFIG_REGULATOR_S2MPS11=y
	1264	+CONFIG_REGULATOR_TPS65132=m
	1265	+CONFIG_REGULATOR_VCTRL=m
	1266	+CONFIG_RC_CORE=m
	1267	+CONFIG_RC_DECODERS=y
	1268	+CONFIG_IR_IMON_DECODER=m
	1269	+CONFIG_IR_JVC_DECODER=m
	1270	+CONFIG_IR_MCE_KBD_DECODER=m
	1271	+CONFIG_IR_NEC_DECODER=m
	1272	+CONFIG_IR_RC5_DECODER=m
	1273	+CONFIG_IR_RC6_DECODER=m
	1274	+CONFIG_IR_RCMM_DECODER=m
	1275	+CONFIG_IR_SANYO_DECODER=m
	1276	+CONFIG_IR_SHARP_DECODER=m
	1277	+CONFIG_IR_SONY_DECODER=m
	1278	+CONFIG_IR_XMP_DECODER=m
	1279	+CONFIG_RC_DEVICES=y
	1280	+CONFIG_IR_GPIO_CIR=m
	1281	+CONFIG_MEDIA_SUPPORT=y
f77a70	1282	+CONFIG_MEDIA_SUPPORT_FILTER=y
7d0d56	1283	+CONFIG_MEDIA_CAMERA_SUPPORT=y
W	1284	+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
	1285	+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
	1286	+CONFIG_MEDIA_SDR_SUPPORT=y
	1287	+CONFIG_MEDIA_PLATFORM_SUPPORT=y
	1288	+# CONFIG_DVB_NET is not set
	1289	+CONFIG_MEDIA_USB_SUPPORT=y
	1290	+CONFIG_USB_VIDEO_CLASS=m
	1291	+CONFIG_V4L_PLATFORM_DRIVERS=y
	1292	+CONFIG_SDR_PLATFORM_DRIVERS=y
	1293	+CONFIG_V4L_MEM2MEM_DRIVERS=y
	1294	+CONFIG_VIDEO_MX8_CAPTURE=y
	1295	+CONFIG_VIDEO_MXC_CAPTURE=y
	1296	+CONFIG_VIDEO_MXC_CSI_CAMERA=y
	1297	+CONFIG_MXC_MIPI_CSI=y
	1298	+CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y
	1299	+CONFIG_VIDEO_AMPHION_VPU=y
	1300	+CONFIG_VIDEO_IMX8_JPEG=m
	1301	+CONFIG_VIDEO_HANTRO=m
	1302	+CONFIG_VIDEO_IMX219=m
	1303	+CONFIG_VIDEO_OV5640=y
	1304	+CONFIG_VIDEO_OV5645=m
	1305	+CONFIG_VIDEO_AP1302=y
	1306	+CONFIG_VIDEO_MT9M114=y
	1307	+CONFIG_IMX_DPU_CORE=y
	1308	+CONFIG_IMX8MM_LCDIF_CORE=y
	1309	+CONFIG_IMX_LCDIFV3_CORE=y
	1310	+CONFIG_DRM=y
	1311	+CONFIG_DRM_I2C_NXP_TDA998X=m
	1312	+CONFIG_DRM_MALI_DISPLAY=m
	1313	+CONFIG_DRM_NOUVEAU=m
	1314	+CONFIG_DRM_RCAR_DW_HDMI=m
	1315	+CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
	1316	+CONFIG_DRM_PANEL_LVDS=m
	1317	+CONFIG_DRM_PANEL_SIMPLE=y
	1318	+CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
	1319	+CONFIG_DRM_PANEL_RAYDIUM_RM67191=y
	1320	+CONFIG_DRM_PANEL_RAYDIUM_RM68200=y
	1321	+CONFIG_DRM_PANEL_ROCKTECK_HIMAX8394F=y
	1322	+CONFIG_DRM_PANEL_SEIKO_43WVF1G=y
	1323	+CONFIG_DRM_PANEL_SITRONIX_ST7703=m
	1324	+CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
	1325	+CONFIG_DRM_PANEL_WKS_101WX001=y
	1326	+CONFIG_DRM_DISPLAY_CONNECTOR=m
	1327	+CONFIG_DRM_LONTIUM_LT8912B=m
	1328	+CONFIG_DRM_LONTIUM_LT9611=m
	1329	+CONFIG_DRM_LONTIUM_LT9611UXC=m
	1330	+CONFIG_DRM_FSL_IMX_LVDS_BRIDGE=y
	1331	+CONFIG_DRM_NWL_MIPI_DSI=y
	1332	+CONFIG_DRM_NXP_SEIKO_43WVFIG=y
	1333	+CONFIG_DRM_PARADE_PS8640=m
	1334	+CONFIG_DRM_SII902X=m
	1335	+CONFIG_DRM_SIMPLE_BRIDGE=m
	1336	+CONFIG_DRM_THINE_THC63LVD1024=m
	1337	+CONFIG_DRM_TI_SN65DSI86=m
	1338	+CONFIG_DRM_I2C_ADV7511=y
	1339	+CONFIG_DRM_I2C_ADV7511_AUDIO=y
	1340	+CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
	1341	+CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
	1342	+CONFIG_DRM_DW_HDMI_GP_AUDIO=y
	1343	+CONFIG_DRM_DW_HDMI_CEC=m
	1344	+CONFIG_DRM_ITE_IT6263=y
	1345	+CONFIG_DRM_ITE_IT6161=y
	1346	+CONFIG_DRM_IMX=y
	1347	+CONFIG_DRM_IMX_LCDIF_MUX_DISPLAY=y
	1348	+CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
	1349	+CONFIG_DRM_IMX_TVE=y
	1350	+CONFIG_DRM_IMX_LDB=y
	1351	+CONFIG_DRM_IMX8QM_LDB=y
	1352	+CONFIG_DRM_IMX8QXP_LDB=y
	1353	+CONFIG_DRM_IMX8MP_LDB=y
	1354	+CONFIG_DRM_IMX93_LDB=y
	1355	+CONFIG_DRM_IMX_DW_MIPI_DSI=y
	1356	+CONFIG_DRM_IMX93_PARALLEL_DISPLAY_FORMAT=y
	1357	+CONFIG_DRM_IMX_HDMI=y
	1358	+CONFIG_DRM_IMX_SEC_DSIM=y
	1359	+CONFIG_DRM_IMX_DCNANO=y
	1360	+CONFIG_DRM_IMX_DCSS=y
	1361	+CONFIG_DRM_IMX_CDNS_MHDP=y
	1362	+CONFIG_DRM_ETNAVIV=m
	1363	+CONFIG_DRM_HISI_HIBMC=m
	1364	+CONFIG_DRM_HISI_KIRIN=m
	1365	+CONFIG_DRM_MXSFB=y
	1366	+CONFIG_DRM_PL111=m
	1367	+CONFIG_DRM_LIMA=m
	1368	+CONFIG_DRM_PANFROST=m
	1369	+CONFIG_FB=y
	1370	+CONFIG_FB_ARMCLCD=y
	1371	+CONFIG_FB_EFI=y
	1372	+CONFIG_FB_MXC_EINK_V2_PANEL=y
	1373	+CONFIG_BACKLIGHT_PWM=y
	1374	+CONFIG_BACKLIGHT_LP855X=m
	1375	+CONFIG_BACKLIGHT_GPIO=y
f77a70	1376	+CONFIG_FRAMEBUFFER_CONSOLE=y
7d0d56	1377	+CONFIG_LOGO=y
W	1378	+# CONFIG_LOGO_LINUX_MONO is not set
	1379	+# CONFIG_LOGO_LINUX_VGA16 is not set
	1380	+CONFIG_SOUND=y
	1381	+CONFIG_SND=y
	1382	+CONFIG_SND_ALOOP=m
	1383	+CONFIG_SND_USB_AUDIO=m
	1384	+CONFIG_SND_SOC=y
	1385	+CONFIG_SND_SOC_FSL_ASRC=m
	1386	+CONFIG_SND_SOC_FSL_MQS=m
	1387	+CONFIG_SND_SOC_FSL_MICFIL=m
	1388	+CONFIG_SND_SOC_FSL_EASRC=m
	1389	+CONFIG_SND_SOC_FSL_XCVR=m
	1390	+CONFIG_SND_SOC_FSL_ESAI_CLIENT=y
	1391	+CONFIG_SND_SOC_FSL_RPMSG=m
	1392	+CONFIG_SND_IMX_SOC=m
	1393	+CONFIG_SND_SOC_IMX_SGTL5000=m
	1394	+CONFIG_SND_SOC_IMX_SPDIF=m
	1395	+CONFIG_SND_SOC_FSL_ASOC_CARD=m
	1396	+CONFIG_SND_SOC_IMX_AUDMIX=m
	1397	+CONFIG_SND_SOC_IMX_HDMI=m
	1398	+CONFIG_SND_SOC_IMX_CARD=m
	1399	+CONFIG_SND_SOC_IMX_PCM512X=m
	1400	+CONFIG_SND_SOC_SOF_TOPLEVEL=y
	1401	+CONFIG_SND_SOC_SOF_OF=m
	1402	+CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y
	1403	+CONFIG_SND_SOC_SOF_IMX8=m
	1404	+CONFIG_SND_SOC_SOF_IMX8M=m
	1405	+CONFIG_SND_SOC_SOF_IMX8ULP=m
	1406	+CONFIG_SND_SOC_AK4613=m
	1407	+CONFIG_SND_SOC_BT_SCO=y
	1408	+CONFIG_SND_SOC_CROS_EC_CODEC=m
	1409	+CONFIG_SND_SOC_CS42XX8_I2C=y
	1410	+CONFIG_SND_SOC_DMIC=m
	1411	+CONFIG_SND_SOC_ES7134=m
	1412	+CONFIG_SND_SOC_ES7241=m
	1413	+CONFIG_SND_SOC_GTM601=m
	1414	+CONFIG_SND_SOC_MAX98357A=m
	1415	+CONFIG_SND_SOC_MAX98927=m
	1416	+CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
	1417	+CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
	1418	+CONFIG_SND_SOC_PCM3168A_I2C=m
	1419	+CONFIG_SND_SOC_RT5659=m
	1420	+CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
	1421	+CONFIG_SND_SOC_SIMPLE_MUX=m
	1422	+CONFIG_SND_SOC_SPDIF=m
	1423	+CONFIG_SND_SOC_TAS571X=m
	1424	+CONFIG_SND_SOC_WCD934X=m
	1425	+CONFIG_SND_SOC_WM8524=y
	1426	+CONFIG_SND_SOC_WM8904=m
	1427	+CONFIG_SND_SOC_WM8960=m
	1428	+CONFIG_SND_SOC_WM8962=m
	1429	+CONFIG_SND_SOC_WSA881X=m
	1430	+CONFIG_SND_SOC_RPMSG_WM8960=m
	1431	+CONFIG_SND_SOC_RPMSG_AK4497=m
	1432	+CONFIG_SND_SOC_LPASS_WSA_MACRO=m
	1433	+CONFIG_SND_SOC_LPASS_VA_MACRO=m
	1434	+CONFIG_SND_SIMPLE_CARD=y
	1435	+CONFIG_SND_AUDIO_GRAPH_CARD=y
f77a70	1436	+CONFIG_HID_A4TECH=y
G	1437	+CONFIG_HID_APPLE=y
	1438	+CONFIG_HID_BELKIN=y
	1439	+CONFIG_HID_CHERRY=y
	1440	+CONFIG_HID_CHICONY=y
	1441	+CONFIG_HID_CYPRESS=y
	1442	+CONFIG_HID_EZKEY=y
	1443	+CONFIG_HID_ITE=y
	1444	+CONFIG_HID_KENSINGTON=y
	1445	+CONFIG_HID_LOGITECH=y
	1446	+CONFIG_HID_REDRAGON=y
	1447	+CONFIG_HID_MICROSOFT=y
	1448	+CONFIG_HID_MONTEREY=y
7d0d56	1449	+CONFIG_HID_MULTITOUCH=m
W	1450	+CONFIG_I2C_HID_ACPI=m
	1451	+CONFIG_I2C_HID_OF=m
	1452	+CONFIG_USB_CONN_GPIO=y
	1453	+CONFIG_USB=y
	1454	+CONFIG_USB_OTG=y
	1455	+CONFIG_USB_XHCI_HCD=y
	1456	+CONFIG_USB_XHCI_PCI_RENESAS=m
	1457	+CONFIG_USB_EHCI_HCD=y
	1458	+CONFIG_USB_EHCI_HCD_PLATFORM=y
	1459	+CONFIG_USB_OHCI_HCD=y
	1460	+CONFIG_USB_OHCI_HCD_PLATFORM=y
	1461	+CONFIG_USB_HCD_TEST_MODE=y
	1462	+CONFIG_USB_ACM=m
	1463	+CONFIG_USB_STORAGE=y
	1464	+CONFIG_USB_UAS=y
	1465	+CONFIG_USB_CDNS_SUPPORT=y
	1466	+CONFIG_USB_CDNS3=y
	1467	+CONFIG_USB_CDNS3_GADGET=y
	1468	+CONFIG_USB_CDNS3_HOST=y
	1469	+CONFIG_USB_MUSB_HDRC=y
	1470	+CONFIG_USB_DWC3=y
	1471	+CONFIG_USB_DWC2=y
	1472	+CONFIG_USB_CHIPIDEA=y
	1473	+CONFIG_USB_CHIPIDEA_UDC=y
	1474	+CONFIG_USB_CHIPIDEA_HOST=y
	1475	+CONFIG_USB_ISP1760=y
	1476	+CONFIG_USB_SERIAL=y
	1477	+CONFIG_USB_SERIAL_CONSOLE=y
	1478	+CONFIG_USB_SERIAL_GENERIC=y
	1479	+CONFIG_USB_SERIAL_SIMPLE=y
	1480	+CONFIG_USB_SERIAL_CP210X=m
	1481	+CONFIG_USB_SERIAL_FTDI_SIO=y
	1482	+CONFIG_USB_SERIAL_OPTION=m
	1483	+CONFIG_USB_TEST=m
	1484	+CONFIG_USB_EHSET_TEST_FIXTURE=y
	1485	+CONFIG_USB_HSIC_USB3503=y
	1486	+CONFIG_NOP_USB_XCEIV=y
	1487	+CONFIG_USB_MXS_PHY=y
	1488	+CONFIG_USB_ULPI=y
	1489	+CONFIG_USB_GADGET=y
	1490	+CONFIG_USB_SNP_UDC_PLAT=y
	1491	+CONFIG_USB_BDC_UDC=y
	1492	+CONFIG_USB_CONFIGFS=y
	1493	+CONFIG_USB_CONFIGFS_SERIAL=y
	1494	+CONFIG_USB_CONFIGFS_ACM=y
	1495	+CONFIG_USB_CONFIGFS_OBEX=y
	1496	+CONFIG_USB_CONFIGFS_NCM=y
	1497	+CONFIG_USB_CONFIGFS_ECM=y
	1498	+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
	1499	+CONFIG_USB_CONFIGFS_RNDIS=y
	1500	+CONFIG_USB_CONFIGFS_EEM=y
	1501	+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
	1502	+CONFIG_USB_CONFIGFS_F_LB_SS=y
	1503	+CONFIG_USB_CONFIGFS_F_FS=y
	1504	+CONFIG_USB_CONFIGFS_F_UAC1=y
	1505	+CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
	1506	+CONFIG_USB_CONFIGFS_F_UAC2=y
	1507	+CONFIG_USB_CONFIGFS_F_MIDI=y
	1508	+CONFIG_USB_CONFIGFS_F_HID=y
	1509	+CONFIG_USB_CONFIGFS_F_UVC=y
	1510	+CONFIG_USB_ZERO=m
	1511	+CONFIG_USB_AUDIO=m
	1512	+CONFIG_USB_ETH=m
	1513	+CONFIG_USB_MASS_STORAGE=m
	1514	+CONFIG_USB_G_SERIAL=m
	1515	+CONFIG_TYPEC=y
	1516	+CONFIG_TYPEC_TCPM=y
	1517	+CONFIG_TYPEC_TCPCI=y
	1518	+CONFIG_TYPEC_FUSB302=m
	1519	+CONFIG_TYPEC_TPS6598X=m
	1520	+CONFIG_TYPEC_HD3SS3220=m
	1521	+CONFIG_TYPEC_SWITCH_GPIO=y
	1522	+CONFIG_MMC=y
	1523	+CONFIG_MMC_BLOCK_MINORS=32
	1524	+CONFIG_MMC_ARMMMCI=y
	1525	+CONFIG_MMC_SDHCI=y
	1526	+CONFIG_MMC_SDHCI_ACPI=y
	1527	+CONFIG_MMC_SDHCI_PLTFM=y
	1528	+CONFIG_MMC_SDHCI_OF_ARASAN=y
	1529	+CONFIG_MMC_SDHCI_OF_ESDHC=y
	1530	+CONFIG_MMC_SDHCI_CADENCE=y
	1531	+CONFIG_MMC_SDHCI_ESDHC_IMX=y
	1532	+CONFIG_MMC_SDHCI_F_SDH30=y
	1533	+CONFIG_MMC_SPI=y
	1534	+CONFIG_MMC_DW=y
	1535	+CONFIG_MMC_DW_EXYNOS=y
	1536	+CONFIG_MMC_DW_HI3798CV200=y
	1537	+CONFIG_MMC_DW_K3=y
	1538	+CONFIG_MMC_MTK=y
	1539	+CONFIG_MMC_SDHCI_XENON=y
	1540	+CONFIG_MMC_SDHCI_AM654=y
	1541	+CONFIG_SCSI_UFSHCD=y
	1542	+CONFIG_SCSI_UFSHCD_PLATFORM=y
	1543	+CONFIG_NEW_LEDS=y
	1544	+CONFIG_LEDS_CLASS=y
	1545	+CONFIG_LEDS_CLASS_MULTICOLOR=m
	1546	+CONFIG_LEDS_LM3692X=m
	1547	+CONFIG_LEDS_PCA9532=m
	1548	+CONFIG_LEDS_GPIO=y
	1549	+CONFIG_LEDS_PCA995X=m
	1550	+CONFIG_LEDS_PWM=y
	1551	+CONFIG_LEDS_SYSCON=y
	1552	+CONFIG_LEDS_TRIGGER_TIMER=y
	1553	+CONFIG_LEDS_TRIGGER_DISK=y
	1554	+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
	1555	+CONFIG_LEDS_TRIGGER_CPU=y
	1556	+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
	1557	+CONFIG_LEDS_TRIGGER_PANIC=y
	1558	+CONFIG_EDAC=y
	1559	+CONFIG_EDAC_GHES=y
	1560	+CONFIG_EDAC_LAYERSCAPE=m
	1561	+CONFIG_EDAC_SYNOPSYS=y
	1562	+CONFIG_RTC_CLASS=y
2b23f8	1563	+CONFIG_RTC_DRV_ISL1208=y
7d0d56	1564	+CONFIG_DMADEVICES=y
W	1565	+CONFIG_FSL_EDMA=y
	1566	+CONFIG_FSL_QDMA=m
	1567	+CONFIG_FSL_EDMA_V3=y
	1568	+CONFIG_IMX_SDMA=y
	1569	+CONFIG_MV_XOR_V2=y
	1570	+CONFIG_MXS_DMA=y
	1571	+CONFIG_MXC_PXP_V3=y
	1572	+CONFIG_PL330_DMA=y
	1573	+CONFIG_QCOM_HIDMA_MGMT=y
	1574	+CONFIG_QCOM_HIDMA=y
	1575	+CONFIG_DW_EDMA=y
	1576	+CONFIG_DW_EDMA_PCIE=y
	1577	+CONFIG_FSL_DPAA2_QDMA=m
	1578	+CONFIG_DMATEST=y
	1579	+CONFIG_DMABUF_HEAPS=y
	1580	+CONFIG_DMABUF_HEAPS_SYSTEM=y
	1581	+CONFIG_DMABUF_HEAPS_CMA=y
	1582	+CONFIG_DMABUF_HEAPS_DSP=y
	1583	+CONFIG_UIO_PCI_GENERIC=y
	1584	+CONFIG_UIO_IVSHMEM=y
	1585	+CONFIG_VFIO=y
	1586	+CONFIG_VFIO_PCI=y
	1587	+CONFIG_VFIO_FSL_MC=y
	1588	+CONFIG_VIRTIO_PCI=y
	1589	+CONFIG_VIRTIO_BALLOON=y
	1590	+CONFIG_VIRTIO_MMIO=y
	1591	+CONFIG_VIRTIO_IVSHMEM=y
	1592	+CONFIG_XEN_GNTDEV=y
	1593	+CONFIG_XEN_GRANT_DEV_ALLOC=y
	1594	+CONFIG_STAGING=y
	1595	+CONFIG_STAGING_MEDIA=y
	1596	+CONFIG_VIDEO_IMX_CAPTURE=y
	1597	+CONFIG_IMX8_MEDIA_DEVICE=m
	1598	+CONFIG_MHDP_HDMIRX=y
	1599	+CONFIG_MHDP_HDMIRX_CEC=y
	1600	+CONFIG_FSL_DPAA2=y
	1601	+CONFIG_FSL_PPFE=y
	1602	+CONFIG_FSL_PPFE_UTIL_DISABLED=y
	1603	+CONFIG_ETHOSU=y
	1604	+CONFIG_CHROME_PLATFORMS=y
	1605	+CONFIG_CROS_EC=y
	1606	+CONFIG_CROS_EC_I2C=y
	1607	+CONFIG_CROS_EC_SPI=y
	1608	+CONFIG_CROS_EC_CHARDEV=m
	1609	+CONFIG_CLK_VEXPRESS_OSC=y
	1610	+CONFIG_COMMON_CLK_RK808=y
	1611	+CONFIG_COMMON_CLK_SCMI=y
	1612	+CONFIG_COMMON_CLK_SCPI=y
	1613	+CONFIG_COMMON_CLK_CS2000_CP=y
	1614	+CONFIG_COMMON_CLK_FSL_SAI=y
	1615	+CONFIG_COMMON_CLK_S2MPS11=y
	1616	+CONFIG_COMMON_CLK_XGENE=y
	1617	+CONFIG_COMMON_CLK_PWM=y
	1618	+CONFIG_COMMON_CLK_VC5=y
	1619	+CONFIG_CLK_IMX8MM=y
	1620	+CONFIG_CLK_IMX8MN=y
	1621	+CONFIG_CLK_IMX8MP=y
	1622	+CONFIG_CLK_IMX8MQ=y
	1623	+CONFIG_CLK_IMX8QXP=y
	1624	+CONFIG_CLK_IMX8ULP=y
	1625	+CONFIG_CLK_IMX93=y
	1626	+CONFIG_HWSPINLOCK=y
	1627	+CONFIG_ARM_MHU=y
	1628	+CONFIG_IMX_MBOX=y
	1629	+CONFIG_PLATFORM_MHU=y
	1630	+CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
	1631	+CONFIG_ARM_SMMU=y
	1632	+CONFIG_ARM_SMMU_V3=y
	1633	+CONFIG_REMOTEPROC=y
	1634	+CONFIG_IMX_REMOTEPROC=y
	1635	+CONFIG_IMX_DSP_REMOTEPROC=m
	1636	+CONFIG_RPMSG_CHAR=m
	1637	+CONFIG_RPMSG_CTRL=m
	1638	+CONFIG_RPMSG_QCOM_GLINK_RPM=y
	1639	+CONFIG_SOUNDWIRE=m
	1640	+CONFIG_SOUNDWIRE_QCOM=m
	1641	+CONFIG_SOC_BRCMSTB=y
	1642	+CONFIG_FSL_DPAA=y
	1643	+CONFIG_FSL_MC_DPIO=y
	1644	+CONFIG_FSL_RCPM=y
	1645	+CONFIG_FSL_QIXIS=y
	1646	+CONFIG_SOC_TI=y
	1647	+CONFIG_EXTCON_PTN5150=m
	1648	+CONFIG_EXTCON_USB_GPIO=y
	1649	+CONFIG_EXTCON_USBC_CROS_EC=y
	1650	+CONFIG_IIO=y
	1651	+CONFIG_FXLS8962AF_I2C=m
	1652	+CONFIG_IIO_ST_ACCEL_3AXIS=m
	1653	+CONFIG_IMX8QXP_ADC=y
	1654	+CONFIG_IMX93_ADC=y
2f7a23	1655	+CONFIG_MS1112=y
2b23f8	1656	+CONFIG_BMG160=m
7d0d56	1657	+CONFIG_IIO_ST_GYRO_3AXIS=m
2b23f8	1658	+CONFIG_MAX30100=m
G	1659	+CONFIG_MAX30102=m
	1660	+CONFIG_DHT11=y
	1661	+CONFIG_HDC100X=y
	1662	+CONFIG_HTS221=y
7d0d56	1663	+CONFIG_FXOS8700_I2C=y
W	1664	+CONFIG_RPMSG_IIO_PEDOMETER=m
	1665	+CONFIG_INV_MPU6050_I2C=m
	1666	+CONFIG_IIO_ST_LSM6DSX=y
	1667	+CONFIG_SENSORS_ISL29018=y
	1668	+CONFIG_IIO_ST_MAGN_3AXIS=m
	1669	+CONFIG_MPL3115=y
	1670	+CONFIG_MS5611=m
	1671	+CONFIG_MS5611_I2C=m
	1672	+CONFIG_PWM=y
	1673	+CONFIG_PWM_ADP5585=y
	1674	+CONFIG_PWM_CROS_EC=m
	1675	+CONFIG_PWM_FSL_FTM=m
	1676	+CONFIG_PWM_IMX27=y
	1677	+CONFIG_PWM_RPCHIP=y
	1678	+CONFIG_PWM_SL28CPLD=m
	1679	+CONFIG_SL28CPLD_INTC=y
	1680	+CONFIG_RESET_IMX7=y
	1681	+CONFIG_RESET_IMX8ULP_SIM=y
	1682	+CONFIG_PHY_XGENE=y
	1683	+CONFIG_PHY_MIXEL_LVDS=y
	1684	+CONFIG_PHY_MIXEL_LVDS_COMBO=y
	1685	+CONFIG_PHY_CADENCE_SALVO=y
	1686	+CONFIG_PHY_FSL_IMX8MP_LVDS=y
	1687	+CONFIG_PHY_FSL_IMX93_MIPI_DPHY=y
	1688	+CONFIG_PHY_MIXEL_MIPI_DPHY=y
	1689	+CONFIG_PHY_FSL_IMX8M_PCIE=y
	1690	+CONFIG_PHY_FSL_IMX8Q_PCIE=y
	1691	+CONFIG_PHY_SAMSUNG_HDMI_PHY=y
	1692	+CONFIG_PHY_QCOM_USB_HS=y
	1693	+CONFIG_PHY_SAMSUNG_USB2=y
	1694	+CONFIG_ARM_CCI_PMU=m
	1695	+CONFIG_ARM_CCN=m
	1696	+CONFIG_ARM_CMN=m
	1697	+CONFIG_ARM_SMMU_V3_PMU=m
	1698	+CONFIG_ARM_DSU_PMU=m
	1699	+CONFIG_FSL_IMX8_DDR_PMU=y
	1700	+CONFIG_FSL_IMX9_DDR_PMU=y
	1701	+CONFIG_ARM_SPE_PMU=m
	1702	+CONFIG_ARM_DMC620_PMU=m
	1703	+CONFIG_HISI_PMU=y
	1704	+CONFIG_NVMEM_IMX_OCOTP=y
	1705	+CONFIG_NVMEM_IMX_OCOTP_SCU=y
	1706	+CONFIG_NVMEM_RMEM=m
	1707	+CONFIG_FPGA=y
	1708	+CONFIG_FPGA_BRIDGE=m
	1709	+CONFIG_ALTERA_FREEZE_BRIDGE=m
	1710	+CONFIG_FPGA_REGION=m
	1711	+CONFIG_OF_FPGA_REGION=m
	1712	+CONFIG_TEE=y
	1713	+CONFIG_OPTEE=y
	1714	+CONFIG_MUX_MMIO=y
	1715	+CONFIG_SLIM_QCOM_CTRL=m
	1716	+CONFIG_MXC_SIM=y
	1717	+CONFIG_MXC_GPU_VIV=y
	1718	+CONFIG_MXC_EMVSIM=y
	1719	+CONFIG_EXT2_FS=y
	1720	+CONFIG_EXT3_FS=y
	1721	+CONFIG_EXT4_FS_POSIX_ACL=y
	1722	+CONFIG_FANOTIFY=y
	1723	+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
	1724	+CONFIG_QUOTA=y
	1725	+CONFIG_AUTOFS4_FS=y
	1726	+CONFIG_FUSE_FS=m
	1727	+CONFIG_CUSE=m
	1728	+CONFIG_OVERLAY_FS=m
	1729	+CONFIG_VFAT_FS=y
f77a70	1730	+CONFIG_EXFAT_FS=y
G	1731	+CONFIG_NTFS_FS=y
	1732	+CONFIG_NTFS_RW=y
	1733	+CONFIG_NTFS3_FS=y
	1734	+CONFIG_NTFS3_64BIT_CLUSTER=y
	1735	+CONFIG_NTFS3_LZX_XPRESS=y
	1736	+CONFIG_NTFS3_FS_POSIX_ACL=y
7d0d56	1737	+CONFIG_TMPFS_POSIX_ACL=y
W	1738	+CONFIG_HUGETLBFS=y
	1739	+CONFIG_EFIVAR_FS=y
	1740	+CONFIG_JFFS2_FS=y
	1741	+CONFIG_NFS_FS=y
	1742	+CONFIG_NFS_V4=y
	1743	+CONFIG_NFS_V4_1=y
	1744	+CONFIG_NFS_V4_2=y
	1745	+CONFIG_ROOT_NFS=y
	1746	+CONFIG_NLS_CODEPAGE_437=y
f77a70	1747	+CONFIG_NLS_CODEPAGE_936=y
G	1748	+CONFIG_NLS_CODEPAGE_950=y
	1749	+CONFIG_NLS_CODEPAGE_874=y
7d0d56	1750	+CONFIG_NLS_ISO8859_1=y
f77a70	1751	+CONFIG_NLS_UTF8=y
7d0d56	1752	+CONFIG_TRUSTED_KEYS=m
W	1753	+# CONFIG_TRUSTED_KEYS_TPM is not set
	1754	+# CONFIG_TRUSTED_KEYS_TEE is not set
	1755	+CONFIG_SECURITY=y
	1756	+CONFIG_CRYPTO_USER=y
	1757	+CONFIG_CRYPTO_TEST=m
	1758	+CONFIG_CRYPTO_ANUBIS=m
	1759	+CONFIG_CRYPTO_ARIA=m
	1760	+CONFIG_CRYPTO_BLOWFISH=m
	1761	+CONFIG_CRYPTO_CAMELLIA=m
	1762	+CONFIG_CRYPTO_CAST5=m
	1763	+CONFIG_CRYPTO_CAST6=m
	1764	+CONFIG_CRYPTO_FCRYPT=m
	1765	+CONFIG_CRYPTO_KHAZAD=m
	1766	+CONFIG_CRYPTO_SEED=m
	1767	+CONFIG_CRYPTO_SERPENT=m
	1768	+CONFIG_CRYPTO_TEA=m
	1769	+CONFIG_CRYPTO_TWOFISH=m
	1770	+CONFIG_CRYPTO_ARC4=m
	1771	+CONFIG_CRYPTO_CFB=m
	1772	+CONFIG_CRYPTO_CTS=m
	1773	+CONFIG_CRYPTO_LRW=m
	1774	+CONFIG_CRYPTO_OFB=m
	1775	+CONFIG_CRYPTO_PCBC=m
	1776	+CONFIG_CRYPTO_CHACHA20POLY1305=m
	1777	+CONFIG_CRYPTO_ECHAINIV=y
	1778	+CONFIG_CRYPTO_TLS=m
f77a70	1779	+CONFIG_CRYPTO_BLAKE2B=m
7d0d56	1780	+CONFIG_CRYPTO_MD4=m
W	1781	+CONFIG_CRYPTO_RMD160=m
	1782	+CONFIG_CRYPTO_STREEBOG=m
	1783	+CONFIG_CRYPTO_VMAC=m
	1784	+CONFIG_CRYPTO_WP512=m
	1785	+CONFIG_CRYPTO_XCBC=m
f77a70	1786	+CONFIG_CRYPTO_XXHASH=m
G	1787	+CONFIG_CRYPTO_LZO=y
	1788	+CONFIG_CRYPTO_ZSTD=y
7d0d56	1789	+CONFIG_CRYPTO_ANSI_CPRNG=y
W	1790	+CONFIG_CRYPTO_USER_API_HASH=m
	1791	+CONFIG_CRYPTO_USER_API_SKCIPHER=m
	1792	+CONFIG_CRYPTO_USER_API_RNG=m
	1793	+CONFIG_CRYPTO_USER_API_AEAD=m
	1794	+CONFIG_CRYPTO_CHACHA20_NEON=m
	1795	+CONFIG_CRYPTO_GHASH_ARM64_CE=y
	1796	+CONFIG_CRYPTO_SHA1_ARM64_CE=y
	1797	+CONFIG_CRYPTO_SHA2_ARM64_CE=y
	1798	+CONFIG_CRYPTO_SHA512_ARM64_CE=m
	1799	+CONFIG_CRYPTO_SHA3_ARM64=m
	1800	+CONFIG_CRYPTO_SM3_ARM64_CE=m
	1801	+CONFIG_CRYPTO_POLYVAL_ARM64_CE=m
	1802	+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
	1803	+CONFIG_CRYPTO_AES_ARM64_BS=m
	1804	+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
	1805	+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
	1806	+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=m
	1807	+CONFIG_CRYPTO_DEV_FSL_CAAM=m
	1808	+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m
	1809	+CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m
	1810	+CONFIG_CRYPTO_DEV_CCREE=m
	1811	+CONFIG_CRYPTO_DEV_HISI_SEC2=m
	1812	+CONFIG_CRYPTO_DEV_HISI_ZIP=m
	1813	+CONFIG_CRYPTO_DEV_HISI_HPRE=m
	1814	+CONFIG_CRYPTO_DEV_HISI_TRNG=m
	1815	+CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
	1816	+CONFIG_INDIRECT_PIO=y
	1817	+CONFIG_CRC_CCITT=m
	1818	+CONFIG_CRC8=y
	1819	+CONFIG_CMA_SIZE_MBYTES=32
	1820	+CONFIG_PRINTK_TIME=y
	1821	+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
	1822	+CONFIG_DEBUG_INFO_REDUCED=y
	1823	+CONFIG_MAGIC_SYSRQ=y
	1824	+CONFIG_DEBUG_FS=y
	1825	+# CONFIG_SCHED_DEBUG is not set
	1826	+# CONFIG_DEBUG_PREEMPT is not set
	1827	+# CONFIG_FTRACE is not set
	1828	+CONFIG_CORESIGHT=y
	1829	+CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
	1830	+CONFIG_CORESIGHT_CATU=m
	1831	+CONFIG_CORESIGHT_SINK_TPIU=m
	1832	+CONFIG_CORESIGHT_SINK_ETBV10=m
	1833	+CONFIG_CORESIGHT_SOURCE_ETM4X=y
	1834	+CONFIG_CORESIGHT_STM=m
	1835	+CONFIG_CORESIGHT_CPU_DEBUG=m
	1836	+CONFIG_CORESIGHT_CTI=m
	1837	+CONFIG_MEMTEST=y
2f7a23	1838	diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
G	1839	index 3946eb595..15278c13c 100644
	1840	--- a/drivers/iio/adc/Kconfig
	1841	+++ b/drivers/iio/adc/Kconfig
	1842	@@ -1164,6 +1164,18 @@ config TI_ADC161S626
	1843	This driver can also be built as a module. If so, the module will be
	1844	called ti-adc161s626.
	1845
	1846	+config MS1112
	1847	+ tristate "Ruimeng Technology MS1112 ADC"
	1848	+ depends on I2C
	1849	+ select IIO_BUFFER
	1850	+ select IIO_TRIGGERED_BUFFER
	1851	+ help
	1852	+ If you say yes here you get support for Ruimeng Technology ADS1015
	1853	+ ADC chip.
	1854	+
	1855	+ This driver can also be built as a module. If so, the module will be
	1856	+ called ms1112.
	1857	+
	1858	config TI_ADS1015
	1859	tristate "Texas Instruments ADS1015 ADC"
	1860	depends on I2C
	1861	diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
	1862	index 83233c38c..f403164cf 100644
	1863	--- a/drivers/iio/adc/Makefile
	1864	+++ b/drivers/iio/adc/Makefile
	1865	@@ -104,6 +104,7 @@ obj-$(CONFIG_TI_ADC12138) += ti-adc12138.o
	1866	obj-$(CONFIG_TI_ADC108S102) += ti-adc108s102.o
	1867	obj-$(CONFIG_TI_ADC128S052) += ti-adc128s052.o
	1868	obj-$(CONFIG_TI_ADC161S626) += ti-adc161s626.o
	1869	+obj-$(CONFIG_MS1112) += ms1112.o
	1870	obj-$(CONFIG_TI_ADS1015) += ti-ads1015.o
	1871	obj-$(CONFIG_TI_ADS7950) += ti-ads7950.o
	1872	obj-$(CONFIG_TI_ADS8344) += ti-ads8344.o
	1873	diff --git a/drivers/iio/adc/ms1112.c b/drivers/iio/adc/ms1112.c
	1874	new file mode 100644
	1875	index 000000000..cf8ea5c66
	1876	--- /dev/null
	1877	+++ b/drivers/iio/adc/ms1112.c
	1878	@@ -0,0 +1,569 @@
	1879	+// SPDX-License-Identifier: GPL-2.0-only
	1880	+/*
	1881	+ * MS1112 - Ruimeng Technology Analog-to-Digital Converter
	1882	+ *
	1883	+ * Copyright (c) 2024, LingYun IoT System Studio.
	1884	+ *
	1885	+ * IIO driver for MS1112 ADC 7-bit I2C slave address: 0x4A
	1886	+ */
	1887	+
	1888	+#include <linux/init.h>
	1889	+#include <linux/module.h>
	1890	+#include <linux/errno.h>
	1891	+#include <linux/gpio.h>
	1892	+#include <linux/cdev.h>
	1893	+#include <linux/device.h>
	1894	+#include <linux/of_gpio.h>
	1895	+#include <linux/semaphore.h>
	1896	+#include <linux/timer.h>
	1897	+#include <linux/i2c.h>
	1898	+#include <asm/uaccess.h>
	1899	+#include <asm/io.h>
	1900	+#include <linux/iio/iio.h>
	1901	+#include <linux/iio/driver.h>
	1902	+
	1903	+#define MS1112_DRV_NAME "ms1112"
	1904	+
	1905	+#define MS1112_CONV_REG 0x00
	1906	+#define MS1112_CFG_REG 0x01
	1907	+#define MS1112_DEFAULT_CONFIG 0xFC
	1908	+
	1909	+#define MS1112_CHANNELS 4
	1910	+#define MS1112_CFG_DR_SHIFT 2
	1911	+#define MS1112_CFG_MOD_SHIFT 4
	1912	+#define MS1112_CFG_PGA_SHIFT 0
	1913	+#define MS1112_CFG_MUX_SHIFT 5
	1914	+
	1915	+#define MS1112_CFG_DR_MASK GENMASK(3, 2)
	1916	+#define MS1112_CFG_MOD_MASK BIT(4)
	1917	+#define MS1112_CFG_PGA_MASK GENMASK(1, 0)
	1918	+#define MS1112_CFG_MUX_MASK GENMASK(6, 5)
	1919	+
	1920	+#define MS1112_DEFAULT_PGA 0
	1921	+#define MS1112_DEFAULT_DATA_RATE 3
	1922	+#define MS1112_DEFAULT_CHAN 2
	1923	+#define MS1112_DEFAULT_MODE 1
	1924	+
	1925	+#define MS1112_CONTINUOUS 0
	1926	+#define MS1112_SINGLESHOT 1
	1927	+
	1928	+struct ms1112_chip_data {
	1929	+ struct iio_chan_spec const *channels;
	1930	+ int num_channels;
	1931	+ const struct iio_info *info;
	1932	+ const int *data_rate;
	1933	+ const int data_rate_len;
	1934	+ const int *scale;
	1935	+ const int scale_len;
	1936	+ bool has_comparator;
	1937	+};
	1938	+
	1939	+enum ms1112_channels {
	1940	+ MS1112_AIN0_AIN1 = 0,
	1941	+ MS1112_AIN2,
	1942	+ MS1112_AIN0,
	1943	+ MS1112_AIN1,
	1944	+ MS1112_TIMESTAMP,
	1945	+};
	1946	+
	1947	+static const int ms1112_data_rate[] = {
	1948	+ 240,60,30,15
	1949	+};
	1950	+
	1951	+static const int ms1112_fullscale_range[] = {
	1952	+ 2048
	1953	+};
	1954	+
	1955	+static const int ms1112_scale[] = { /* 12bit ADC */
	1956	+ 2048,11,
	1957	+ 2048,13,
	1958	+ 2048,14,
	1959	+ 2048,15
	1960	+};
	1961	+
	1962	+#define FIT_CHECK(_testbits, _fitbits) \
	1963	+ ( \
	1964	+ (_fitbits) * \
	1965	+ !!sizeof(struct { \
	1966	+ static_assert((_testbits) <= (_fitbits)); \
	1967	+ int pad; \
	1968	+ }) \
	1969	+ )
	1970	+
	1971	+#define MS1112_V_CHAN(_chan, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \
	1972	+ .type = IIO_VOLTAGE, \
	1973	+ .indexed = 1, \
	1974	+ .address = _addr, \
	1975	+ .channel = _chan, \
	1976	+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \| \
	1977	+ BIT(IIO_CHAN_INFO_SCALE) \| \
	1978	+ BIT(IIO_CHAN_INFO_SAMP_FREQ), \
	1979	+ .info_mask_shared_by_all_available = \
	1980	+ BIT(IIO_CHAN_INFO_SCALE) \| \
	1981	+ BIT(IIO_CHAN_INFO_SAMP_FREQ), \
	1982	+ .scan_index = _addr, \
	1983	+ .scan_type = { \
	1984	+ .sign = 's', \
	1985	+ .realbits = (_realbits), \
	1986	+ .storagebits = FIT_CHECK((_realbits) + (_shift), 16), \
	1987	+ .shift = (_shift), \
	1988	+ .endianness = IIO_CPU, \
	1989	+ }, \
	1990	+ .event_spec = (_event_spec), \
	1991	+ .num_event_specs = (_num_event_specs), \
	1992	+ .datasheet_name = "AIN"#_chan, \
	1993	+}
	1994	+
	1995	+#define MS1112_V_DIFF_CHAN(_chan, _chan2, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \
	1996	+ .type = IIO_VOLTAGE, \
	1997	+ .differential = 1, \
	1998	+ .indexed = 1, \
	1999	+ .address = _addr, \
	2000	+ .channel = _chan, \
	2001	+ .channel2 = _chan2, \
	2002	+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \| \
	2003	+ BIT(IIO_CHAN_INFO_SCALE) \| \
	2004	+ BIT(IIO_CHAN_INFO_SAMP_FREQ), \
	2005	+ .info_mask_shared_by_all_available = \
	2006	+ BIT(IIO_CHAN_INFO_SCALE) \| \
	2007	+ BIT(IIO_CHAN_INFO_SAMP_FREQ), \
	2008	+ .scan_index = _addr, \
	2009	+ .scan_type = { \
	2010	+ .sign = 's', \
	2011	+ .realbits = (_realbits), \
	2012	+ .storagebits = FIT_CHECK((_realbits) + (_shift), 16), \
	2013	+ .shift = (_shift), \
	2014	+ .endianness = IIO_CPU, \
	2015	+ }, \
	2016	+ .event_spec = (_event_spec), \
	2017	+ .num_event_specs = (_num_event_specs), \
	2018	+ .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
	2019	+}
	2020	+
	2021	+struct ms1112_channel_data {
	2022	+ bool enabled;
	2023	+ unsigned int pga;
	2024	+ unsigned int data_rate;
	2025	+ unsigned int mode;
	2026	+};
	2027	+
	2028	+struct ms1112_thresh_data {
	2029	+ int high_thresh;
	2030	+ int low_thresh;
	2031	+};
	2032	+
	2033	+struct ms1112_data {
	2034	+ struct ms1112_channel_data channel_data[MS1112_CHANNELS];
	2035	+ struct ms1112_thresh_data thresh_data[MS1112_CHANNELS];
	2036	+ const struct ms1112_chip_data *chip;
	2037	+ struct mutex lock;
	2038	+ void *private_data;
	2039	+ struct i2c_client *client;
	2040	+};
	2041	+
	2042	+/* MS1112 don't use the register address */
	2043	+static int ms1112_read_regs(struct ms1112_data dev, uint8_t reg, void buf, uint8_t size)
	2044	+{
	2045	+ int ret = 0;
	2046	+ struct i2c_msg msg[1];
	2047	+ struct i2c_client *client = dev->client;
	2048	+
	2049	+ msg[0].addr = client->addr;
	2050	+ msg[0].flags = I2C_M_RD;
	2051	+ msg[0].buf = buf;
	2052	+ msg[0].len = size;
	2053	+
	2054	+ ret = i2c_transfer(client->adapter, msg, 1);
	2055	+ if(ret != 1) {
	2056	+ dev_err(&dev->client->dev, "%s() i2c_transfer error, ret=%d\n", __func__, ret);
	2057	+ ret = -EREMOTEIO;
	2058	+ }
	2059	+
	2060	+ return ret;
	2061	+}
	2062	+
	2063	+/* MS1112 don't use the register address */
	2064	+static s32 ms1112_write_regs(struct ms1112_data dev, uint8_t reg, uint8_t data, uint8_t bytes)
	2065	+{
	2066	+ int ret = 0;
	2067	+ struct i2c_msg msg;
	2068	+ struct i2c_client *client = dev->client;
	2069	+
	2070	+ msg.addr = client->addr;
	2071	+ msg.flags = 0;
	2072	+ msg.buf = data;
	2073	+ msg.len = bytes;
	2074	+
	2075	+ ret = i2c_transfer(client->adapter, &msg, 1);
	2076	+ if(ret != 1) {
	2077	+ dev_err(&dev->client->dev, "%s() i2c_transfer error, ret=%d\n", __func__, ret);
	2078	+ ret = -EREMOTEIO;
	2079	+ }
	2080	+
	2081	+ return ret;
	2082	+}
	2083	+
	2084	+static int ms1112_readdata(struct ms1112_data dev,unsigned int val)
	2085	+{
	2086	+ unsigned char buf[3];
	2087	+ unsigned char rx_data[3];
	2088	+ int rv = 0;
	2089	+
	2090	+ rv = ms1112_read_regs(dev, MS1112_CONV_REG, rx_data, 3);
	2091	+ if(rv<0) {
	2092	+ return rv;
	2093	+ }
	2094	+
	2095	+ buf[0] = rx_data[0];
	2096	+ buf[1] = rx_data[1];
	2097	+ buf[2] = rx_data[2];
	2098	+
	2099	+ *val = (buf[0]<<8) \| buf[1];
	2100	+ return rv;
	2101	+}
	2102	+
	2103	+static int ms1112_get_adc_result(struct ms1112_data data, int chan, int val)
	2104	+{
	2105	+ int ret = 0;
	2106	+ int pga, dr , mode;
	2107	+ uint8_t mask, cfg;
	2108	+
	2109	+ if (chan < 0 \|\| chan >= MS1112_CHANNELS)
	2110	+ return -EINVAL;
	2111	+
	2112	+ mode = data->channel_data[chan].mode;
	2113	+ pga = data->channel_data[chan].pga;
	2114	+ dr = data->channel_data[chan].data_rate;
	2115	+
	2116	+ mask = MS1112_CFG_MUX_MASK \| MS1112_CFG_PGA_MASK \|
	2117	+ MS1112_CFG_DR_MASK \| MS1112_CFG_MOD_MASK \| MS1112_SINGLESHOT << 7;
	2118	+
	2119	+ cfg = chan << MS1112_CFG_MUX_SHIFT \| pga << MS1112_CFG_PGA_SHIFT \|
	2120	+ dr << MS1112_CFG_DR_SHIFT \| mode << MS1112_CFG_MOD_SHIFT \| MS1112_SINGLESHOT << 7;
	2121	+
	2122	+ cfg = (cfg & mask);
	2123	+
	2124	+ ms1112_write_regs(data, MS1112_CFG_REG, &cfg, 1);
	2125	+
	2126	+ ret = ms1112_readdata(data,val);
	2127	+ return ret;
	2128	+}
	2129	+
	2130	+static int ms1112_set_scale(struct ms1112_data data, struct iio_chan_spec const chan,
	2131	+ int scale, int uscale)
	2132	+{
	2133	+ int i;
	2134	+ int fullscale = div_s64((scale * 1000000LL + uscale) <<
	2135	+ (chan->scan_type.realbits - 1), 1000000);
	2136	+
	2137	+ for (i = 0; i < ARRAY_SIZE(ms1112_fullscale_range); i++) {
	2138	+ if (ms1112_fullscale_range[i] == fullscale) {
	2139	+ data->channel_data[chan->address].pga = i;
	2140	+ return 0;
	2141	+ }
	2142	+ }
	2143	+
	2144	+ return -EINVAL;
	2145	+}
	2146	+
	2147	+static int ms1112_set_data_rate(struct ms1112_data *data, int chan, int rate)
	2148	+{
	2149	+ int i;
	2150	+
	2151	+ for (i = 0; i < data->chip->data_rate_len; i++) {
	2152	+ if (data->chip->data_rate[i] == rate) {
	2153	+ data->channel_data[chan].data_rate = i;
	2154	+ return 0;
	2155	+ }
	2156	+ }
	2157	+
	2158	+ return -EINVAL;
	2159	+}
	2160	+
	2161	+static int ms1112_read_avail(struct iio_dev *indio_dev,
	2162	+ struct iio_chan_spec const *chan,
	2163	+ const int *vals, int type, int *length,
	2164	+ long mask)
	2165	+{
	2166	+ struct ms1112_data *data = iio_priv(indio_dev);
	2167	+
	2168	+ if (chan->type != IIO_VOLTAGE)
	2169	+ return -EINVAL;
	2170	+
	2171	+ switch (mask) {
	2172	+ case IIO_CHAN_INFO_SCALE:
	2173	+ *type = IIO_VAL_FRACTIONAL_LOG2;
	2174	+ *vals = data->chip->scale;
	2175	+ *length = data->chip->scale_len;
	2176	+ return IIO_AVAIL_LIST;
	2177	+ case IIO_CHAN_INFO_SAMP_FREQ:
	2178	+ *type = IIO_VAL_INT;
	2179	+ *vals = data->chip->data_rate;
	2180	+ *length = data->chip->data_rate_len;
	2181	+ return IIO_AVAIL_LIST;
	2182	+ default:
	2183	+ return -EINVAL;
	2184	+ }
	2185	+}
	2186	+
	2187	+static int ms1112_read_raw(struct iio_dev indio_dev, struct iio_chan_spec const chan, int val, int val2, long mask)
	2188	+{
	2189	+ int ret, idx;
	2190	+ struct ms1112_data *data = iio_priv(indio_dev);
	2191	+
	2192	+ mutex_lock(&data->lock);
	2193	+ switch (mask) {
	2194	+ case IIO_CHAN_INFO_RAW:
	2195	+
	2196	+ ret = iio_device_claim_direct_mode(indio_dev);
	2197	+ if (ret)
	2198	+ break;
	2199	+
	2200	+ ret = ms1112_get_adc_result(data, chan->address, val);
	2201	+ if (ret < 0) {
	2202	+ goto release_direct;
	2203	+ }
	2204	+
	2205	+ val = sign_extend32(val >> chan->scan_type.shift,
	2206	+ chan->scan_type.realbits - 1);
	2207	+
	2208	+ ret = IIO_VAL_INT;
	2209	+release_direct:
	2210	+ iio_device_release_direct_mode(indio_dev);
	2211	+ break;
	2212	+
	2213	+ case IIO_CHAN_INFO_SCALE:
	2214	+ idx = data->channel_data[chan->address].pga;
	2215	+ *val = ms1112_fullscale_range[idx];
	2216	+ *val2 = chan->scan_type.realbits - 1;
	2217	+ ret = IIO_VAL_FRACTIONAL_LOG2;
	2218	+ break;
	2219	+ case IIO_CHAN_INFO_SAMP_FREQ:
	2220	+ idx = data->channel_data[chan->address].data_rate;
	2221	+ *val = data->chip->data_rate[idx];
	2222	+ ret = IIO_VAL_INT;
	2223	+ break;
	2224	+ default:
	2225	+ ret = -EINVAL;
	2226	+ break;
	2227	+ }
	2228	+ mutex_unlock(&data->lock);
	2229	+
	2230	+ return ret;
	2231	+}
	2232	+
	2233	+static int ms1112_write_raw(struct iio_dev *indio_dev,
	2234	+ struct iio_chan_spec const *chan, int val,
	2235	+ int val2, long mask)
	2236	+{
	2237	+ struct ms1112_data *data = iio_priv(indio_dev);
	2238	+ int ret;
	2239	+
	2240	+ mutex_lock(&data->lock);
	2241	+ switch (mask) {
	2242	+ case IIO_CHAN_INFO_SCALE:
	2243	+ ret = ms1112_set_scale(data, chan, val, val2);
	2244	+ break;
	2245	+ case IIO_CHAN_INFO_SAMP_FREQ:
	2246	+ ret = ms1112_set_data_rate(data, chan->address, val);
	2247	+ break;
	2248	+ default:
	2249	+ ret = -EINVAL;
	2250	+ break;
	2251	+ }
	2252	+ mutex_unlock(&data->lock);
	2253	+
	2254	+ return ret;
	2255	+}
	2256	+
	2257	+static const struct iio_info ms1112_info = {
	2258	+ .read_raw = ms1112_read_raw,
	2259	+ .write_raw = ms1112_write_raw,
	2260	+ .read_avail = ms1112_read_avail,
	2261	+};
	2262	+
	2263	+
	2264	+static const struct iio_chan_spec ms1112_channels[] = {
	2265	+ MS1112_V_DIFF_CHAN(0, 1, MS1112_AIN0_AIN1, 16, 0, NULL, 0),
	2266	+ MS1112_V_CHAN(2, MS1112_AIN2, 16, 0, NULL, 0),
	2267	+ MS1112_V_CHAN(0, MS1112_AIN0, 16, 0, NULL, 0),
	2268	+ MS1112_V_CHAN(1, MS1112_AIN1, 16, 0, NULL, 0),
	2269	+ IIO_CHAN_SOFT_TIMESTAMP(MS1112_TIMESTAMP),
	2270	+};
	2271	+
	2272	+static int ms1112_client_get_channels_config(struct i2c_client *client)
	2273	+{
	2274	+ struct iio_dev *indio_dev = i2c_get_clientdata(client);
	2275	+ struct ms1112_data *data = iio_priv(indio_dev);
	2276	+ struct device *dev = &client->dev;
	2277	+ struct fwnode_handle *node;
	2278	+ int i = -1;
	2279	+
	2280	+ device_for_each_child_node(dev, node) {
	2281	+ u32 pval;
	2282	+ unsigned int channel;
	2283	+ unsigned int pga = MS1112_DEFAULT_PGA;
	2284	+ unsigned int data_rate = MS1112_DEFAULT_DATA_RATE;
	2285	+ unsigned int mode = MS1112_DEFAULT_MODE;
	2286	+
	2287	+ if (fwnode_property_read_u32(node, "reg", &pval)) {
	2288	+ dev_err(dev, "invalid reg on %pfw\n", node);
	2289	+ continue;
	2290	+ }
	2291	+
	2292	+ channel = pval;
	2293	+ if (channel >= MS1112_CHANNELS) {
	2294	+ dev_err(dev, "invalid channel index %d on %pfw\n",
	2295	+ channel, node);
	2296	+ continue;
	2297	+ }
	2298	+
	2299	+ if (!fwnode_property_read_u32(node, "ti,gain", &pval)) {
	2300	+ pga = pval;
	2301	+ if (pga > 3 ) {
	2302	+ dev_err(dev, "invalid gain on %pfw\n", node);
	2303	+ fwnode_handle_put(node);
	2304	+ return -EINVAL;
	2305	+ }
	2306	+ }
	2307	+
	2308	+ if (!fwnode_property_read_u32(node, "ti,datarate", &pval)) {
	2309	+ data_rate = pval;
	2310	+ if (data_rate > 3) {
	2311	+ dev_err(dev, "invalid data_rate on %pfw\n", node);
	2312	+ fwnode_handle_put(node);
	2313	+ return -EINVAL;
	2314	+ }
	2315	+ }
	2316	+
	2317	+ if (!fwnode_property_read_u32(node, "ti,mode", &pval)) {
	2318	+ mode = pval;
	2319	+ if (mode > 1) {
	2320	+ dev_err(dev, "invalid mode on %pfw\n", node);
	2321	+ fwnode_handle_put(node);
	2322	+ return -EINVAL;
	2323	+ }
	2324	+ }
	2325	+
	2326	+
	2327	+ data->channel_data[channel].pga = pga;
	2328	+ data->channel_data[channel].data_rate = data_rate;
	2329	+ data->channel_data[channel].mode = mode;
	2330	+ i++;
	2331	+ }
	2332	+
	2333	+ return i < 0 ? -EINVAL : 0;
	2334	+}
	2335	+
	2336	+static void ms1112_get_channels_config(struct i2c_client *client)
	2337	+{
	2338	+ unsigned int k;
	2339	+
	2340	+ struct iio_dev *indio_dev = i2c_get_clientdata(client);
	2341	+ struct ms1112_data *data = iio_priv(indio_dev);
	2342	+
	2343	+ if (!ms1112_client_get_channels_config(client))
	2344	+ return;
	2345	+
	2346	+ /* fallback on default configuration */
	2347	+ for (k = 0; k < MS1112_CHANNELS; ++k) {
	2348	+ data->channel_data[k].pga = MS1112_DEFAULT_PGA;
	2349	+ data->channel_data[k].data_rate = MS1112_DEFAULT_DATA_RATE;
	2350	+ data->channel_data[k].mode = MS1112_DEFAULT_MODE;
	2351	+ }
	2352	+}
	2353	+
	2354	+static int ms1112_probe(struct i2c_client client,const struct i2c_device_id id)
	2355	+{
	2356	+ struct iio_dev *indio_dev;
	2357	+ const struct ms1112_chip_data *chip;
	2358	+ struct ms1112_data *data;
	2359	+ int ret;
	2360	+ int i;
	2361	+
	2362	+ chip = device_get_match_data(&client->dev);
	2363	+ if (!chip)
	2364	+ chip = (const struct ms1112_chip_data *)id->driver_data;
	2365	+ if (!chip)
	2366	+ return dev_err_probe(&client->dev, -EINVAL, "Unknown chip\n");
	2367	+
	2368	+ indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*indio_dev));
	2369	+ if (!indio_dev)
	2370	+ return -ENOMEM;
	2371	+
	2372	+ data = iio_priv(indio_dev);
	2373	+ i2c_set_clientdata(client, indio_dev);
	2374	+
	2375	+ mutex_init(&data->lock);
	2376	+
	2377	+ indio_dev->name = MS1112_DRV_NAME;
	2378	+ indio_dev->info = chip->info;
	2379	+ indio_dev->modes = INDIO_DIRECT_MODE;
	2380	+ indio_dev->channels = chip->channels;
	2381	+ indio_dev->num_channels = chip->num_channels;
	2382	+ data->chip = chip;
	2383	+ data->client = client;
	2384	+
	2385	+ for (i = 0; i < MS1112_CHANNELS; i++) {
	2386	+ int realbits = indio_dev->channels[i].scan_type.realbits;
	2387	+
	2388	+ data->thresh_data[i].low_thresh = -1 << (realbits - 1);
	2389	+ data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1;
	2390	+ }
	2391	+
	2392	+ /* we need to keep this ABI the same as used by hwmon ADS1015 driver */
	2393	+ ms1112_get_channels_config(client);
	2394	+
	2395	+ ret = iio_device_register(indio_dev);
	2396	+ if (ret)
	2397	+ dev_err(&client->dev, "Failed to register IIO device\n");
	2398	+ return ret;
	2399	+}
	2400	+
	2401	+static void ms1112_remove(struct i2c_client *client)
	2402	+{
	2403	+ struct iio_dev *indio_dev = i2c_get_clientdata(client);
	2404	+
	2405	+ iio_device_unregister(indio_dev);
	2406	+
	2407	+}
	2408	+
	2409	+static const struct ms1112_chip_data ms1112_data = {
	2410	+ .channels = ms1112_channels,
	2411	+ .num_channels = ARRAY_SIZE(ms1112_channels),
	2412	+ .info = &ms1112_info,
	2413	+ .data_rate = ms1112_data_rate,
	2414	+ .data_rate_len = ARRAY_SIZE(ms1112_data_rate),
	2415	+ .scale = ms1112_scale,
	2416	+ .scale_len = ARRAY_SIZE(ms1112_scale),
	2417	+ .has_comparator = false,
	2418	+};
	2419	+
	2420	+static const struct i2c_device_id ms1112_id[] = {
	2421	+ { "ms1112", (kernel_ulong_t)&ms1112_data },
	2422	+ {}
	2423	+};
	2424	+MODULE_DEVICE_TABLE(i2c, ms1112_id);
	2425	+
	2426	+static const struct of_device_id ms1112_of_match[] = {
	2427	+ { .compatible = "ms,ms1112" },
	2428	+ { },
	2429	+};
	2430	+MODULE_DEVICE_TABLE(of, ms1112_of_match);
	2431	+
	2432	+static struct i2c_driver ms1112_driver = {
	2433	+ .driver = {
	2434	+ .owner = THIS_MODULE,
	2435	+ .name = "ms1112",
	2436	+ .of_match_table = ms1112_of_match,
	2437	+ },
	2438	+ .probe = ms1112_probe,
	2439	+ .remove = ms1112_remove,
	2440	+ .id_table = ms1112_id,
	2441	+};
	2442	+
	2443	+module_i2c_driver(ms1112_driver);
	2444	+
	2445	+MODULE_AUTHOR("Tang Junfeng");
	2446	+MODULE_DESCRIPTION("MS1112 IIO ADC Driver");
	2447	+MODULE_LICENSE("GPL");