guowenxue
2024-07-17 35deaefe2a198508903c5657a0fa7cb2ad60f56d
commit | author | age
7d0d56 1 diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
W 2 index 7b1a129e6..1d5c6e770 100644
3 --- a/arch/arm64/boot/dts/freescale/Makefile
4 +++ b/arch/arm64/boot/dts/freescale/Makefile
5 @@ -412,3 +412,5 @@ dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb \
6                s32v234-sbc.dtb
7  dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-sof-cs42888.dtb imx8qm-mek-sof-wm8960.dtb \
8                imx8qm-mek-revd-sof-wm8962.dtb imx8qm-mek-sof.dtb
9 +
10 +dtb-$(CONFIG_ARCH_MXC) += igkboard-imx8mp.dtb
11 diff --git a/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts b/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts
12 new file mode 100644
35deae 13 index 000000000..ce38a5b4a
7d0d56 14 --- /dev/null
W 15 +++ b/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts
35deae 16 @@ -0,0 +1,782 @@
7d0d56 17 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6f4428 18 +/* 
G 19 + * Device Tree Source for LingYun IGKBoard(IoT Gateway Kits Board) - imx8mp
7d0d56 20 + * Copyright 2023 LingYun IoT System Studio.
W 21 + */
22 +
23 +/dts-v1/;
24 +
25 +#include <dt-bindings/usb/pd.h>
26 +#include "imx8mp.dtsi"
27 +
28 +/*+------------------------+
29 +  |       root node        |
30 +  +------------------------+*/
31 +/ {
32 +    model = "LingYun IoT Gateway Kits Board based on i.MX8MP";
33 +    compatible = "lingyun,igkboard-imx8mp", "fsl,imx8mp";
34 +
6f4428 35 +    /* console */
7d0d56 36 +    chosen {
W 37 +        stdout-path = &uart2;
38 +    };
39 +
40 +    /* MT53D512M32D2DS-053 WT:D, 2GB LPDDR4 */
41 +    memory@80000000 {
42 +        device_type = "memory";
6f4428 43 +        reg = <0x0 0x80000000 0 0x40000000>;
7d0d56 44 +    };
W 45 +
46 +    leds {
47 +        compatible = "gpio-leds";
48 +        pinctrl-names = "default";
49 +        pinctrl-0 = <&pinctrl_leds>;
50 +        status = "okay";
51 +
52 +        sysled {
53 +            label = "sysled";
54 +            gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
7872ca 55 +            default-state = "on";
G 56 +            linux,default-trigger = "heartbeat";
57 +        };
58 +
59 +        ledred {
60 +            label = "redled";
61 +            gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
62 +            default-state = "off";
63 +        };
64 +
65 +        ledgreen {
66 +            label = "greenled";
67 +            gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
68 +            default-state = "off";
69 +        };
70 +
71 +        ledblue {
72 +            label = "blueled";
73 +            gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
74 +            default-state = "on";
f77a70 75 +            linux,default-trigger = "timer";
7872ca 76 +        };
G 77 +    };
78 +
79 +    keys {
80 +        compatible = "gpio-keys";
81 +        pinctrl-names = "default";
82 +        pinctrl-0 = <&pinctrl_keys>;
83 +        status = "okay";
84 +
85 +        key1 {
86 +            label = "K1";
87 +            gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
88 +            linux,code = <BTN_1>;
89 +        };
90 +
91 +        key2 {
92 +            label = "K2";
93 +            gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
94 +            linux,code = <BTN_2>;
95 +        };
96 +
97 +        key3 {
98 +            label = "K3";
99 +            gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
100 +            linux,code = <BTN_3>;
101 +        };
102 +
103 +        key4 {
104 +            label = "K4";
105 +            gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
106 +            linux,code = <BTN_4>;
7d0d56 107 +        };
35deae 108 +    };
G 109 +
110 +    sound-wm8960 {
111 +        compatible = "fsl,imx-audio-wm8960";
112 +        model = "wm8960-audio";
113 +        audio-cpu = <&sai3>;
114 +        audio-codec = <&codec>;
115 +        audio-asrc = <&easrc>;
116 +        //hp-det-gpio = <&gpio4 29 0>;
117 +        audio-routing =
118 +            "Headphone Jack", "HP_L",
119 +            "Headphone Jack", "HP_R",
120 +            "Ext Spk", "SPK_LP",
121 +            "Ext Spk", "SPK_LN",
122 +            "Ext Spk", "SPK_RP",
123 +            "Ext Spk", "SPK_RN",
124 +            "LINPUT1", "Mic Jack",
125 +            "LINPUT3", "Mic Jack",
126 +            "Mic Jack", "MICB";
7d0d56 127 +    };
W 128 +};
129 +
130 +/*+------------------------+
131 +  |   power key & reset    |
132 +  +------------------------+*/
133 +
134 +&snvs_pwrkey {
135 +    status = "okay";
136 +};
137 +
138 +&wdog1 {
139 +    pinctrl-names = "default";
140 +    pinctrl-0 = <&pinctrl_wdog>;
141 +    fsl,ext-reset-output;
142 +    status = "okay";
143 +};
144 +
145 +/*+------------------------+
146 +  |    console usart2      |
147 +  +------------------------+*/
148 +&uart2 {
149 +    pinctrl-names = "default";
150 +    pinctrl-0 = <&pinctrl_uart2>;
151 +    status = "okay";
152 +};
153 +
154 +/*+------------------------+
155 +  |    8GB eMMC on SD3     |
156 +  +------------------------+*/
157 +
158 +/* KLM8G1GETF-B041 8GB eMMC */
159 +&usdhc3 {
160 +    pinctrl-names = "default", "state_100mhz", "state_200mhz";
161 +    pinctrl-0 = <&pinctrl_usdhc3>;
162 +    pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
163 +    pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
164 +    bus-width = <8>;
165 +    non-removable;
166 +    status = "okay";
167 +};
168 +
169 +/*+------------------------+
170 +  |     TF Card on SD2     |
171 +  +------------------------+*/
172 +
173 +&usdhc2 {
174 +    pinctrl-names = "default", "state_100mhz", "state_200mhz";
175 +    pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
176 +    pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
177 +    pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
178 +    cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
179 +    bus-width = <4>;
180 +    no-1-8-v;
181 +    status = "okay";
182 +};
183 +
184 +/*+------------------------+
185 +  | Typec USB for download |
186 +  +------------------------+*/
187 +
188 +&usb3_phy0 {
189 +    fsl,phy-tx-vref-tune = <6>;
190 +    fsl,phy-tx-rise-tune = <0>;
191 +    fsl,phy-tx-preemp-amp-tune = <3>;
192 +    fsl,phy-comp-dis-tune = <7>;
193 +    fsl,pcs-tx-deemph-3p5db = <0x21>;
194 +    fsl,phy-pcs-tx-swing-full = <0x7f>;
195 +    status = "okay";
196 +};
197 +
198 +&usb3_0 {
199 +    status = "okay";
200 +};
201 +
202 +&usb_dwc3_0 {
203 +    dr_mode = "peripheral";
204 +    hnp-disable;
205 +    srp-disable;
206 +    adp-disable;
207 +    status = "okay";
208 +};
209 +
210 +/*+------------------------+
211 +  | 2xUSB Host on USB Hub  |
212 +  +------------------------+*/
213 +
214 +/* Renesas USB 3.0 Hub uPD720210 */
215 +&usb3_phy1 {
216 +    fsl,phy-tx-preemp-amp-tune = <2>;
217 +    status = "okay";
218 +};
219 +
220 +&usb3_1 {
221 +    status = "okay";
222 +};
223 +
224 +&usb_dwc3_1 {
225 +    dr_mode = "host";
226 +    status = "okay";
227 +};
228 +
229 +/*+------------------------+
230 +  |        Ethernet        |
231 +  +------------------------+*/
232 +
233 +/* First 1000Mbps Ethernet For TSN on ENET */
234 +&eqos {
235 +    pinctrl-names = "default";
236 +    pinctrl-0 = <&pinctrl_eqos>;
237 +    phy-mode = "rgmii-id";
238 +    phy-handle = <&ethphy0>;
239 +    status = "okay";
240 +
241 +    mdio {
242 +        compatible = "snps,dwmac-mdio";
243 +        #address-cells = <1>;
244 +        #size-cells = <0>;
6f4428 245 +        clock-frequency = <5000000>;
7d0d56 246 +
W 247 +        ethphy0: ethernet-phy@0 { /* YT8521SH-CA */
248 +            compatible = "ethernet-phy-ieee802.3-c22";
249 +            reg = <0>;
250 +            eee-broken-1000t;
251 +        };
252 +    };
253 +};
254 +
6f4428 255 +/* Second 1000Mbps Ethernet on ENET1, test okay */
7d0d56 256 +&fec {
W 257 +    pinctrl-names = "default";
258 +    pinctrl-0 = <&pinctrl_fec>;
259 +    phy-mode = "rgmii-id";
260 +    phy-handle = <&ethphy1>;
261 +    fsl,magic-packet;
262 +    status = "okay";
263 +
264 +    mdio {
265 +        #address-cells = <1>;
266 +        #size-cells = <0>;
6f4428 267 +        clock-frequency = <5000000>;
7d0d56 268 +
W 269 +        ethphy1: ethernet-phy@0 { /* YT8521SH-CA */
270 +            compatible = "ethernet-phy-ieee802.3-c22";
271 +            reg = <0>;
272 +            eee-broken-1000t;
273 +        };
274 +    };
275 +};
276 +
277 +/*+------------------------+
500850 278 +  |      Misc Devices      |
G 279 +  +------------------------+*/
280 +
281 +/* Buzzer */
282 +&pwm1 {
283 +    pinctrl-names = "default";
284 +    pinctrl-0 = <&pinctrl_pwm1>;
285 +    status = "okay";
286 +};
287 +
2b23f8 288 +&i2c2 {
G 289 +    clock-frequency = <100000>;
290 +    pinctrl-names = "default";
291 +    pinctrl-0 = <&pinctrl_i2c2>;
292 +    status = "okay";
293 +
35deae 294 +    codec: wm8960@1a {
G 295 +        compatible = "wlf,wm8960";
296 +        reg = <0x1a>;
297 +        clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>;
298 +        clock-names = "mclk";
299 +        wlf,shared-lrclk;
2f7a23 300 +    };
G 301 +
302 +    ms1112@4a {
303 +        compatible = "ms,ms1112";
304 +        reg = <0x4a>;
305 +        status = "okay";
306 +        #address-cells = <1>;
307 +        #size-cells = <0>;
308 +
309 +        channel@2 {
310 +                reg = <2>;
311 +                ti,gain = <0>;
312 +                ti,datarate = <3>;
313 +                ti,mode = <1>;
314 +        };
315 +
316 +        channel@3{
317 +                reg = <3>;
318 +                ti,gain = <0>;
319 +                ti,datarate = <3>;
320 +                ti,mode = <1>;
321 +        };
2b23f8 322 +    };
35deae 323 +
G 324 +    rtc1208@6f {
325 +        compatible = "isil,isl1208";
326 +        reg = <0x6f>;
327 +        status = "okay";
328 +    };
329 +};
330 +
331 +/*+------------------------+
332 +  |   WM8960 Audio Codec   |
333 +  +------------------------+*/
334 +
335 +&sai3 {
336 +    pinctrl-names = "default";
337 +    pinctrl-0 = <&pinctrl_sai3>;
338 +    assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
339 +    assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
340 +    assigned-clock-rates = <12288000>;
341 +    clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>,
342 +         <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
343 +         <&clk IMX8MP_CLK_DUMMY>;
344 +    clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
345 +    fsl,sai-mclk-direction-output;
346 +    status = "okay";
347 +};
348 +
349 +&easrc {
350 +    fsl,asrc-rate  = <48000>;
351 +    status = "okay";
352 +};
353 +
354 +&xcvr {
355 +    #sound-dai-cells = <0>;
356 +    status = "okay";
357 +};
358 +
359 +&sdma2 {
360 +    status = "okay";
2b23f8 361 +};
G 362 +
500850 363 +/*+------------------------+
ac4b9f 364 +  |  CAN/RS485 interface   |
G 365 +  +------------------------+*/
366 +/* RS485 */
367 +&uart3 {
368 +    pinctrl-names = "default";
369 +    pinctrl-0 = <&pinctrl_uart3>;
370 +    status = "okay";
371 +};
372 +
373 +/* CAN */
374 +&flexcan1 {
375 +    pinctrl-names = "default";
376 +    pinctrl-0 = <&pinctrl_flexcan1>;
377 +    status = "okay";
378 +};
379 +
380 +&flexcan2 {
381 +    pinctrl-names = "default";
382 +    pinctrl-0 = <&pinctrl_flexcan2>;
383 +    status = "okay";
384 +};
385 +
386 +/*+------------------------+
500850 387 +  |   MikroBUS interface   |
G 388 +  +------------------------+*/
389 +
390 +/* Same as RPi 40Pin extend interface: #32 */
391 +&pwm3 {
392 +    pinctrl-names = "default";
393 +    pinctrl-0 = <&pinctrl_pwm3>;
394 +    status = "okay";
395 +};
396 +
397 +/* Same as RPi 40Pin extend interface: #19, #21, #23, #24 */
398 +&uart1 {
399 +    pinctrl-names = "default";
400 +    pinctrl-0 = <&pinctrl_uart1>;
401 +    assigned-clocks = <&clk IMX8MP_CLK_UART1>;
402 +    assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
403 +    status = "okay";
404 +};
405 +
406 +/* Same as RPi 40Pin extend interface */
407 +&ecspi2 {
408 +    #address-cells = <1>;
409 +    #size-cells = <0>;
410 +    fsl,spi-num-chipselects = <1>;
411 +    pinctrl-names = "default";
412 +    pinctrl-0 = <&pinctrl_ecspi2>;
413 +    cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
414 +    status = "okay";
415 +
416 +    spidev@0 {
417 +        compatible = "fsl,spidev", "semtech,sx1301";
418 +        reg = <0>;
419 +        spi-max-frequency = <2000000>;
420 +    };
421 +};
422 +
423 +/* Same as RPi 40Pin extend interface: #3, #5 */
424 +&i2c5 {
425 +    clock-frequency = <100000>;
426 +    pinctrl-names = "default";
427 +    pinctrl-0 = <&pinctrl_i2c5>;
428 +    status = "okay";
2b23f8 429 +
G 430 +    hdc1080@40 {
431 +        compatible = "ti,hdc1080";
432 +        reg = <0x40>;
433 +        status = "okay";
434 +    };
435 +
436 +    eeprom@50 {
437 +        compatible = "microchip,24c32", "atmel,24c32";
438 +        reg = <0x50>;
439 +        pagesize = <32>;
440 +        num-addresses = <8>;
441 +    };
500850 442 +};
G 443 +
444 +/*+------------------------+
7d0d56 445 +  |    PCA9450CHN PMIC     |
W 446 +  +------------------------+*/
447 +
448 +&i2c1 {
449 +    clock-frequency = <400000>;
500850 450 +    pinctrl-names = "default";
7d0d56 451 +    pinctrl-0 = <&pinctrl_i2c1>;
W 452 +    status = "okay";
453 +
454 +    pmic@25 {
455 +        compatible = "nxp,pca9450c";
456 +        reg = <0x25>;
457 +        pinctrl-names = "default";
458 +        pinctrl-0 = <&pinctrl_pmic>;
459 +        interrupt-parent = <&gpio1>;
460 +        interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
461 +
462 +        regulators {
463 +            buck1: BUCK1 {
464 +                regulator-name = "BUCK1";
465 +                regulator-min-microvolt = <600000>;
466 +                regulator-max-microvolt = <2187500>;
467 +                regulator-boot-on;
468 +                regulator-always-on;
469 +                regulator-ramp-delay = <3125>;
470 +            };
471 +
472 +            buck2: BUCK2 {
473 +                regulator-name = "BUCK2";
474 +                regulator-min-microvolt = <600000>;
475 +                regulator-max-microvolt = <2187500>;
476 +                regulator-boot-on;
477 +                regulator-always-on;
478 +                regulator-ramp-delay = <3125>;
479 +                nxp,dvs-run-voltage = <950000>;
480 +                nxp,dvs-standby-voltage = <850000>;
481 +            };
482 +
483 +            buck4: BUCK4{
484 +                regulator-name = "BUCK4";
485 +                regulator-min-microvolt = <600000>;
486 +                regulator-max-microvolt = <3400000>;
487 +                regulator-boot-on;
488 +                regulator-always-on;
489 +            };
490 +
491 +            buck5: BUCK5{
492 +                regulator-name = "BUCK5";
493 +                regulator-min-microvolt = <600000>;
494 +                regulator-max-microvolt = <3400000>;
495 +                regulator-boot-on;
496 +                regulator-always-on;
497 +            };
498 +
499 +            buck6: BUCK6 {
500 +                regulator-name = "BUCK6";
501 +                regulator-min-microvolt = <600000>;
502 +                regulator-max-microvolt = <3400000>;
503 +                regulator-boot-on;
504 +                regulator-always-on;
505 +            };
506 +
507 +            ldo1: LDO1 {
508 +                regulator-name = "LDO1";
509 +                regulator-min-microvolt = <1600000>;
510 +                regulator-max-microvolt = <3300000>;
511 +                regulator-boot-on;
512 +                regulator-always-on;
513 +            };
514 +
515 +            ldo2: LDO2 {
516 +                regulator-name = "LDO2";
517 +                regulator-min-microvolt = <800000>;
518 +                regulator-max-microvolt = <1150000>;
519 +                regulator-boot-on;
520 +                regulator-always-on;
521 +            };
522 +
523 +            ldo3: LDO3 {
524 +                regulator-name = "LDO3";
525 +                regulator-min-microvolt = <800000>;
526 +                regulator-max-microvolt = <3300000>;
527 +                regulator-boot-on;
528 +                regulator-always-on;
529 +            };
530 +
531 +            ldo4: LDO4 {
532 +                regulator-name = "LDO4";
533 +                regulator-min-microvolt = <800000>;
534 +                regulator-max-microvolt = <3300000>;
535 +                regulator-boot-on;
536 +                regulator-always-on;
537 +            };
538 +
539 +            ldo5: LDO5 {
540 +                regulator-name = "LDO5";
541 +                regulator-min-microvolt = <1800000>;
542 +                regulator-max-microvolt = <3300000>;
543 +                regulator-boot-on;
544 +                regulator-always-on;
545 +            };
546 +        };
547 +    };
548 +};
549 +
550 +&iomuxc {
551 +    pinctrl-names = "default";
552 +
500850 553 +    pinctrl_wdog: wdoggrp {
G 554 +        fsl,pins = <
555 +            MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B                       0xc6
556 +        >;
557 +    };
558 +
7d0d56 559 +    pinctrl_leds: ledsgrp {
W 560 +        fsl,pins = <
561 +            MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16                       0x140
7872ca 562 +            MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14                         0x140
G 563 +            MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09                         0x140
564 +            MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21                          0x140
565 +        >;
566 +    };
567 +
568 +    pinctrl_keys: keysgrp {
569 +        fsl,pins = <
570 +            MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08                        0x140
571 +            MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09                         0x140
572 +            MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26                          0x140
573 +            MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27                          0x140
7d0d56 574 +        >;
W 575 +    };
576 +
500850 577 +    pinctrl_pwm1: pwm1grp {
7d0d56 578 +        fsl,pins = <
500850 579 +            MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT                           0x116
G 580 +        >;
581 +    };
582 +
583 +    pinctrl_pwm3: pwm3grp {
584 +        fsl,pins = <
585 +            MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT                             0x116
586 +        >;
587 +    };
588 +
589 +    pinctrl_uart1: uart1grp {
590 +        fsl,pins = <
591 +            MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX                        0x140
592 +            MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX                        0x140
7d0d56 593 +        >;
W 594 +    };
595 +
596 +    pinctrl_uart2: uart2grp {
597 +        fsl,pins = <
598 +            MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX                        0x49
599 +            MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX                        0x49
600 +        >;
601 +    };
602 +
ac4b9f 603 +    pinctrl_uart3: uart3grp {
G 604 +        fsl,pins = <
605 +            MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX                      0x82
606 +            MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX                      0x82
607 +        >;
608 +    };
609 +
610 +    pinctrl_flexcan1: flexcan1grp {
611 +        fsl,pins = <
612 +            MX8MP_IOMUXC_SPDIF_TX__CAN1_TX                              0x154
613 +            MX8MP_IOMUXC_SPDIF_RX__CAN1_RX                              0x154
614 +        >;
615 +    };
616 +
617 +    pinctrl_flexcan2: flexcan2grp {
618 +        fsl,pins = <
619 +            MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX                             0x154
620 +            MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX                             0x154
621 +        >;
622 +    };
623 +
500850 624 +    pinctrl_ecspi2: ecspi2grp {
G 625 +        fsl,pins = <
626 +            MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK                       0x82
627 +            MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI                       0x82
628 +            MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO                       0x82
629 +            MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13                         0x40000
630 +        >;
631 +    };
632 +
7d0d56 633 +    pinctrl_i2c1: i2c1grp {
W 634 +        fsl,pins = <
635 +            MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL                             0x400001c3
636 +            MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA                             0x400001c3
637 +        >;
638 +    };
639 +
2b23f8 640 +    pinctrl_i2c2: i2c2grp {
G 641 +        fsl,pins = <
642 +            MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL                             0x400001c2
643 +            MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA                             0x400001c2
644 +        >;
645 +    };
646 +
500850 647 +    pinctrl_i2c5: i2c5grp {
7d0d56 648 +        fsl,pins = <
500850 649 +            MX8MP_IOMUXC_SD1_CMD__I2C5_SDA                              0x400001c2
G 650 +            MX8MP_IOMUXC_SD1_CLK__I2C5_SCL                              0x400001c2
7d0d56 651 +        >;
W 652 +    };
653 +
35deae 654 +    pinctrl_sai3: sai3grp {
G 655 +        fsl,pins = <
656 +            MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC               0xd6
657 +            MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK                0xd6
658 +            MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00              0xd6
659 +            MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00              0xd6
660 +            MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK                  0xd6
661 +            MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29                           0xd6
662 +        >;
663 +    };
664 +
7d0d56 665 +    pinctrl_pmic: pmicirq {
W 666 +        fsl,pins = <
667 +            MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03                         0x41
668 +        >;
669 +    };
670 +
671 +    pinctrl_usdhc2_gpio: usdhc2grp-gpio {
672 +        fsl,pins = <
673 +            MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12                           0x1c4
674 +        >;
675 +    };
676 +
677 +    pinctrl_usdhc2: usdhc2grp {
678 +        fsl,pins = <
679 +            MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                            0x190
680 +            MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                            0x1d0
681 +            MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                        0x1d0
682 +            MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                        0x1d0
683 +            MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                        0x1d0
684 +            MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                        0x1d0
685 +            MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT                     0xc1
686 +        >;
687 +    };
688 +
689 +    pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
690 +        fsl,pins = <
691 +            MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                            0x194
692 +            MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                            0x1d4
693 +            MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                        0x1d4
694 +            MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                        0x1d4
695 +            MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                        0x1d4
696 +            MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                        0x1d4
697 +            MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT                     0xc1
698 +        >;
699 +    };
700 +
701 +    pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
702 +        fsl,pins = <
703 +            MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK                            0x196
704 +            MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD                            0x1d6
705 +            MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0                        0x1d6
706 +            MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1                        0x1d6
707 +            MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2                        0x1d6
708 +            MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3                        0x1d6
709 +            MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT                     0xc1
710 +        >;
711 +    };
712 +
713 +    pinctrl_usdhc3: usdhc3grp {
714 +        fsl,pins = <
715 +            MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK                          0x190
716 +            MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD                          0x1d0
717 +            MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0                      0x1d0
718 +            MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1                      0x1d0
719 +            MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2                      0x1d0
720 +            MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3                      0x1d0
721 +            MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4                        0x1d0
722 +            MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5                       0x1d0
723 +            MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6                       0x1d0
724 +            MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7                         0x1d0
725 +            MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE                      0x190
726 +        >;
727 +    };
728 +
729 +    pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
730 +        fsl,pins = <
731 +            MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK                          0x194
732 +            MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD                          0x1d4
733 +            MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0                      0x1d4
734 +            MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1                      0x1d4
735 +            MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2                      0x1d4
736 +            MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3                      0x1d4
737 +            MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4                        0x1d4
738 +            MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5                       0x1d4
739 +            MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6                       0x1d4
740 +            MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7                         0x1d4
741 +            MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE                      0x194
742 +        >;
743 +    };
744 +
745 +    pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
746 +        fsl,pins = <
747 +            MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK                          0x196
748 +            MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD                          0x1d6
749 +            MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0                      0x1d6
750 +            MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1                      0x1d6
751 +            MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2                      0x1d6
752 +            MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3                      0x1d6
753 +            MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4                        0x1d6
754 +            MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5                       0x1d6
755 +            MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6                       0x1d6
756 +            MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7                         0x1d6
757 +            MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE                      0x196
758 +        >;
759 +    };
760 +
761 +    pinctrl_eqos: eqosgrp {
762 +        fsl,pins = <
763 +            MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC                         0x2
764 +            MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO                       0x2
765 +            MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0                   0x90
766 +            MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1                   0x90
767 +            MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2                   0x90
768 +            MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3                   0x90
769 +            MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK   0x90
770 +            MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL             0x90
771 +            MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0                   0x16
772 +            MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1                   0x16
773 +            MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2                   0x16
774 +            MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3                   0x16
775 +            MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL             0x16
776 +            MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK   0x16
777 +        >;
778 +    };
779 +
780 +    pinctrl_fec: fecgrp {
781 +        fsl,pins = <
782 +            MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC                           0x2
783 +            MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO                          0x2
784 +            MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0                     0x90
785 +            MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1                     0x90
786 +            MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2                     0x90
787 +            MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3                     0x90
788 +            MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC                      0x90
789 +            MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL                  0x90
790 +            MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0                     0x16
791 +            MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1                     0x16
792 +            MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2                     0x16
793 +            MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3                     0x16
794 +            MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL                  0x16
795 +            MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC                     0x16
796 +        >;
797 +    };
798 +};
799 diff --git a/arch/arm64/configs/igkboard-imx8mp_defconfig b/arch/arm64/configs/igkboard-imx8mp_defconfig
800 new file mode 100644
2f7a23 801 index 000000000..b0f923742
7d0d56 802 --- /dev/null
W 803 +++ b/arch/arm64/configs/igkboard-imx8mp_defconfig
2f7a23 804 @@ -0,0 +1,1103 @@
7d0d56 805 +CONFIG_SYSVIPC=y
W 806 +CONFIG_POSIX_MQUEUE=y
807 +CONFIG_AUDIT=y
808 +CONFIG_NO_HZ_IDLE=y
809 +CONFIG_HIGH_RES_TIMERS=y
810 +CONFIG_BPF_SYSCALL=y
811 +CONFIG_BPF_JIT=y
812 +CONFIG_PREEMPT=y
813 +CONFIG_IRQ_TIME_ACCOUNTING=y
814 +CONFIG_BSD_PROCESS_ACCT=y
815 +CONFIG_BSD_PROCESS_ACCT_V3=y
816 +CONFIG_TASKSTATS=y
817 +CONFIG_TASK_XACCT=y
818 +CONFIG_TASK_IO_ACCOUNTING=y
819 +CONFIG_IKCONFIG=y
820 +CONFIG_IKCONFIG_PROC=y
821 +CONFIG_NUMA_BALANCING=y
822 +CONFIG_MEMCG=y
823 +CONFIG_BLK_CGROUP=y
824 +CONFIG_CGROUP_PIDS=y
825 +CONFIG_CGROUP_FREEZER=y
826 +CONFIG_CGROUP_HUGETLB=y
827 +CONFIG_CPUSETS=y
828 +CONFIG_CGROUP_DEVICE=y
829 +CONFIG_CGROUP_CPUACCT=y
830 +CONFIG_CGROUP_PERF=y
831 +CONFIG_CGROUP_BPF=y
f77a70 832 +CONFIG_NAMESPACES=y
7d0d56 833 +CONFIG_USER_NS=y
W 834 +CONFIG_SCHED_AUTOGROUP=y
835 +CONFIG_RELAY=y
836 +CONFIG_BLK_DEV_INITRD=y
f77a70 837 +CONFIG_EXPERT=y
7d0d56 838 +CONFIG_KALLSYMS_ALL=y
W 839 +CONFIG_PROFILING=y
840 +CONFIG_ARCH_KEEMBAY=y
841 +CONFIG_ARCH_NXP=y
842 +CONFIG_ARCH_LAYERSCAPE=y
843 +CONFIG_ARCH_MXC=y
844 +CONFIG_ARCH_S32=y
845 +CONFIG_SOC_S32V234=y
846 +CONFIG_ARM64_VA_BITS_48=y
847 +CONFIG_SCHED_MC=y
848 +CONFIG_SCHED_SMT=y
849 +CONFIG_NUMA=y
850 +CONFIG_KEXEC=y
851 +CONFIG_KEXEC_FILE=y
852 +CONFIG_CRASH_DUMP=y
853 +CONFIG_XEN=y
854 +CONFIG_ARCH_FORCE_MAX_ORDER=14
855 +CONFIG_COMPAT=y
856 +CONFIG_RANDOMIZE_BASE=y
857 +CONFIG_PM_DEBUG=y
858 +CONFIG_PM_TEST_SUSPEND=y
859 +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
860 +CONFIG_ENERGY_MODEL=y
861 +CONFIG_ARM_PSCI_CPUIDLE=y
862 +CONFIG_CPU_FREQ=y
863 +CONFIG_CPU_FREQ_STAT=y
864 +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
865 +CONFIG_CPU_FREQ_GOV_POWERSAVE=y
866 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
867 +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
868 +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
869 +CONFIG_CPUFREQ_DT=y
870 +CONFIG_ACPI_CPPC_CPUFREQ=m
871 +CONFIG_ARM_SCPI_CPUFREQ=y
872 +CONFIG_ARM_IMX_CPUFREQ_DT=y
873 +CONFIG_ARM_SCMI_CPUFREQ=y
874 +CONFIG_QORIQ_CPUFREQ=y
875 +CONFIG_ACPI=y
876 +CONFIG_ACPI_APEI=y
877 +CONFIG_ACPI_APEI_GHES=y
878 +CONFIG_ACPI_APEI_MEMORY_FAILURE=y
879 +CONFIG_ACPI_APEI_EINJ=y
880 +CONFIG_VIRTUALIZATION=y
881 +CONFIG_KVM=y
882 +CONFIG_JUMP_LABEL=y
883 +CONFIG_MODULES=y
884 +CONFIG_MODULE_UNLOAD=y
885 +CONFIG_MODVERSIONS=y
886 +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
887 +# CONFIG_COMPAT_BRK is not set
888 +CONFIG_KSM=y
889 +CONFIG_MEMORY_FAILURE=y
890 +CONFIG_TRANSPARENT_HUGEPAGE=y
891 +CONFIG_NET=y
892 +CONFIG_PACKET=y
893 +CONFIG_UNIX=y
894 +CONFIG_TLS=y
895 +CONFIG_TLS_DEVICE=y
896 +CONFIG_INET=y
897 +CONFIG_IP_MULTICAST=y
898 +CONFIG_IP_PNP=y
899 +CONFIG_IP_PNP_DHCP=y
900 +CONFIG_IP_PNP_BOOTP=y
901 +CONFIG_IPV6_SIT=m
902 +CONFIG_NETFILTER=y
903 +CONFIG_BRIDGE_NETFILTER=m
904 +CONFIG_NETFILTER_NETLINK_OSF=m
905 +CONFIG_NF_CONNTRACK=m
906 +CONFIG_NF_CONNTRACK_EVENTS=y
907 +CONFIG_NF_TABLES=y
908 +CONFIG_NF_TABLES_INET=y
909 +CONFIG_NF_TABLES_NETDEV=y
910 +CONFIG_NFT_CT=m
911 +CONFIG_NFT_MASQ=m
912 +CONFIG_NFT_NAT=m
913 +CONFIG_NFT_COMPAT=m
914 +CONFIG_NFT_DUP_NETDEV=m
915 +CONFIG_NFT_FWD_NETDEV=m
916 +CONFIG_NF_FLOW_TABLE=m
917 +CONFIG_NETFILTER_XT_MARK=m
918 +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
919 +CONFIG_NETFILTER_XT_TARGET_LOG=m
920 +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
921 +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
922 +CONFIG_NETFILTER_XT_MATCH_IPVS=m
923 +CONFIG_IP_VS=m
924 +CONFIG_NF_SOCKET_IPV4=m
925 +CONFIG_NF_TPROXY_IPV4=m
926 +CONFIG_IP_NF_IPTABLES=m
927 +CONFIG_IP_NF_FILTER=m
928 +CONFIG_IP_NF_TARGET_REJECT=m
929 +CONFIG_IP_NF_NAT=m
930 +CONFIG_IP_NF_TARGET_MASQUERADE=m
931 +CONFIG_IP_NF_MANGLE=m
932 +CONFIG_NF_SOCKET_IPV6=m
933 +CONFIG_NF_TPROXY_IPV6=m
934 +CONFIG_IP6_NF_IPTABLES=m
935 +CONFIG_IP6_NF_FILTER=m
936 +CONFIG_IP6_NF_TARGET_REJECT=m
937 +CONFIG_IP6_NF_MANGLE=m
938 +CONFIG_IP6_NF_NAT=m
939 +CONFIG_IP6_NF_TARGET_MASQUERADE=m
940 +CONFIG_NF_TABLES_BRIDGE=m
941 +CONFIG_BRIDGE_NF_EBTABLES=m
942 +CONFIG_BRIDGE=y
943 +CONFIG_BRIDGE_VLAN_FILTERING=y
944 +CONFIG_NET_DSA=m
945 +CONFIG_VLAN_8021Q_GVRP=y
946 +CONFIG_VLAN_8021Q_MVRP=y
947 +CONFIG_LLC2=y
948 +CONFIG_NET_SCHED=y
949 +CONFIG_NET_SCH_MULTIQ=m
950 +CONFIG_NET_SCH_CBS=m
951 +CONFIG_NET_SCH_ETF=m
952 +CONFIG_NET_SCH_TAPRIO=m
953 +CONFIG_NET_SCH_MQPRIO=m
954 +CONFIG_NET_SCH_INGRESS=m
955 +CONFIG_NET_CLS_BASIC=m
956 +CONFIG_NET_CLS_U32=m
957 +CONFIG_NET_CLS_FLOWER=m
958 +CONFIG_NET_CLS_ACT=y
959 +CONFIG_NET_ACT_GACT=m
960 +CONFIG_NET_ACT_MIRRED=m
961 +CONFIG_NET_ACT_SKBEDIT=m
962 +CONFIG_NET_ACT_GATE=m
963 +CONFIG_TSN=y
964 +CONFIG_QRTR=m
965 +CONFIG_QRTR_SMD=m
966 +CONFIG_QRTR_TUN=m
967 +CONFIG_NET_PKTGEN=m
ac4b9f 968 +CONFIG_CAN=y
G 969 +CONFIG_CAN_ISOTP=y
7d0d56 970 +CONFIG_BT=y
W 971 +CONFIG_BT_RFCOMM=y
972 +CONFIG_BT_RFCOMM_TTY=y
973 +CONFIG_BT_BNEP=y
974 +CONFIG_BT_BNEP_MC_FILTER=y
975 +CONFIG_BT_BNEP_PROTO_FILTER=y
976 +CONFIG_BT_HIDP=y
977 +CONFIG_BT_LEDS=y
978 +# CONFIG_BT_DEBUGFS is not set
979 +CONFIG_BT_HCIBTUSB=m
980 +CONFIG_BT_HCIUART=y
981 +CONFIG_BT_HCIUART_BCSP=y
982 +CONFIG_BT_HCIUART_ATH3K=y
983 +CONFIG_BT_HCIUART_LL=y
984 +CONFIG_BT_HCIUART_3WIRE=y
985 +CONFIG_BT_HCIUART_BCM=y
986 +CONFIG_BT_HCIUART_QCA=y
987 +CONFIG_BT_HCIVHCI=y
988 +CONFIG_BT_NXPUART=m
989 +CONFIG_CFG80211=y
990 +CONFIG_NL80211_TESTMODE=y
991 +CONFIG_CFG80211_WEXT=y
992 +CONFIG_MAC80211=y
993 +CONFIG_MAC80211_LEDS=y
994 +CONFIG_NFC=m
995 +CONFIG_NFC_NCI=m
996 +CONFIG_NFC_S3FWRN5_I2C=m
997 +CONFIG_PCI=y
998 +CONFIG_PCIEPORTBUS=y
999 +CONFIG_PCI_IOV=y
1000 +CONFIG_PCI_PASID=y
1001 +CONFIG_HOTPLUG_PCI=y
1002 +CONFIG_HOTPLUG_PCI_ACPI=y
1003 +CONFIG_PCI_HOST_GENERIC=y
1004 +CONFIG_PCI_XGENE=y
1005 +CONFIG_PCIE_ALTERA=y
1006 +CONFIG_PCIE_ALTERA_MSI=y
1007 +CONFIG_PCI_HOST_THUNDER_PEM=y
1008 +CONFIG_PCI_HOST_THUNDER_ECAM=y
1009 +CONFIG_PCI_IMX6_HOST=y
1010 +CONFIG_PCI_IMX6_EP=y
1011 +CONFIG_PCI_LAYERSCAPE=y
1012 +CONFIG_PCI_HISI=y
1013 +CONFIG_PCIE_KIRIN=y
1014 +CONFIG_PCI_MESON=m
1015 +CONFIG_PCIE_LAYERSCAPE_GEN4=y
1016 +CONFIG_PCI_ENDPOINT=y
1017 +CONFIG_PCI_ENDPOINT_CONFIGFS=y
1018 +CONFIG_PCI_EPF_TEST=y
1019 +CONFIG_DEVTMPFS=y
1020 +CONFIG_DEVTMPFS_MOUNT=y
1021 +CONFIG_FW_LOADER_USER_HELPER=y
1022 +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
1023 +CONFIG_BRCMSTB_GISB_ARB=y
1024 +CONFIG_VEXPRESS_CONFIG=y
1025 +CONFIG_FSL_MC_UAPI_SUPPORT=y
1026 +CONFIG_ARM_SCMI_PROTOCOL=y
1027 +CONFIG_ARM_SCPI_PROTOCOL=y
1028 +CONFIG_EFI_CAPSULE_LOADER=y
1029 +CONFIG_IMX_DSP=y
1030 +CONFIG_IMX_SCU=y
1031 +CONFIG_IMX_SCU_PD=y
1032 +CONFIG_IMX_EL_ENCLAVE=y
1033 +CONFIG_GNSS=m
1034 +CONFIG_GNSS_MTK_SERIAL=m
1035 +CONFIG_MTD=y
1036 +CONFIG_MTD_CMDLINE_PARTS=y
1037 +CONFIG_MTD_BLOCK=y
1038 +CONFIG_MTD_CFI=y
1039 +CONFIG_MTD_CFI_ADV_OPTIONS=y
1040 +CONFIG_MTD_CFI_INTELEXT=y
1041 +CONFIG_MTD_CFI_AMDSTD=y
1042 +CONFIG_MTD_CFI_STAA=y
1043 +CONFIG_MTD_PHYSMAP=y
1044 +CONFIG_MTD_PHYSMAP_OF=y
1045 +CONFIG_MTD_DATAFLASH=y
1046 +CONFIG_MTD_SST25L=y
1047 +CONFIG_MTD_RAW_NAND=y
1048 +CONFIG_MTD_NAND_DENALI_DT=y
1049 +CONFIG_MTD_NAND_GPMI_NAND=y
1050 +CONFIG_MTD_NAND_FSL_IFC=y
1051 +CONFIG_MTD_SPI_NAND=y
1052 +CONFIG_MTD_SPI_NOR=y
1053 +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
1054 +CONFIG_MTD_UBI=y
1055 +CONFIG_BLK_DEV_LOOP=y
1056 +CONFIG_BLK_DEV_NBD=m
1057 +CONFIG_XEN_BLKDEV_BACKEND=m
1058 +CONFIG_VIRTIO_BLK=y
1059 +CONFIG_BLK_DEV_NVME=y
1060 +CONFIG_SRAM=y
1061 +CONFIG_PCI_ENDPOINT_TEST=y
2b23f8 1062 +CONFIG_EEPROM_AT24=y
7d0d56 1063 +CONFIG_UACCE=m
W 1064 +# CONFIG_SCSI_PROC_FS is not set
1065 +CONFIG_BLK_DEV_SD=y
1066 +CONFIG_SCSI_SAS_ATA=y
1067 +CONFIG_SCSI_HISI_SAS=y
1068 +CONFIG_SCSI_HISI_SAS_PCI=y
1069 +CONFIG_MEGARAID_SAS=y
1070 +CONFIG_SCSI_MPT3SAS=m
1071 +CONFIG_ATA=y
1072 +CONFIG_SATA_AHCI=y
1073 +CONFIG_SATA_AHCI_PLATFORM=y
1074 +CONFIG_AHCI_IMX=y
1075 +CONFIG_AHCI_CEVA=y
1076 +CONFIG_AHCI_XGENE=y
1077 +CONFIG_AHCI_QORIQ=y
1078 +CONFIG_SATA_SIL24=y
1079 +CONFIG_PATA_OF_PLATFORM=y
1080 +CONFIG_MD=y
1081 +CONFIG_BLK_DEV_MD=m
1082 +CONFIG_BLK_DEV_DM=m
1083 +CONFIG_DM_CRYPT=m
1084 +CONFIG_DM_MIRROR=m
1085 +CONFIG_DM_ZERO=m
1086 +CONFIG_NETDEVICES=y
1087 +CONFIG_MACVLAN=m
1088 +CONFIG_MACVTAP=m
1089 +CONFIG_TUN=y
1090 +CONFIG_VETH=m
1091 +CONFIG_VIRTIO_NET=y
1092 +CONFIG_NET_DSA_MSCC_FELIX=m
1093 +CONFIG_NET_DSA_SJA1105=m
1094 +CONFIG_NET_DSA_SJA1105_PTP=y
1095 +CONFIG_NET_DSA_SJA1105_TAS=y
1096 +CONFIG_NET_DSA_SJA1105_VL=y
1097 +CONFIG_AMD_XGBE=y
1098 +CONFIG_ATL1C=m
1099 +CONFIG_BCMGENET=m
1100 +CONFIG_BNX2X=m
1101 +CONFIG_SYSTEMPORT=m
1102 +CONFIG_MACB=y
1103 +CONFIG_THUNDER_NIC_PF=y
1104 +CONFIG_FEC=y
1105 +CONFIG_FEC_UIO=y
1106 +CONFIG_FSL_FMAN=y
1107 +CONFIG_FSL_DPAA_ETH=y
1108 +CONFIG_FSL_DPAA2_ETH=y
1109 +CONFIG_FSL_DPAA2_MAC=y
1110 +CONFIG_FSL_DPAA2_SWITCH=y
1111 +CONFIG_FSL_ENETC=y
1112 +CONFIG_FSL_ENETC_VF=y
1113 +CONFIG_FSL_ENETC_QOS=y
1114 +CONFIG_ENETC_TSN=y
1115 +CONFIG_HIX5HD2_GMAC=y
1116 +CONFIG_HNS_DSAF=y
1117 +CONFIG_HNS_ENET=y
1118 +CONFIG_HNS3=y
1119 +CONFIG_HNS3_HCLGE=y
1120 +CONFIG_HNS3_ENET=y
1121 +CONFIG_E1000=y
1122 +CONFIG_E1000E=y
1123 +CONFIG_IGB=y
1124 +CONFIG_IGBVF=y
1125 +CONFIG_MVMDIO=y
1126 +CONFIG_SKY2=y
1127 +CONFIG_MLX4_EN=m
1128 +CONFIG_MLX5_CORE=m
1129 +CONFIG_MLX5_CORE_EN=y
1130 +CONFIG_MSCC_OCELOT_SWITCH=y
1131 +CONFIG_QCOM_EMAC=m
1132 +CONFIG_RMNET=m
1133 +CONFIG_SMC91X=y
1134 +CONFIG_SMSC911X=y
1135 +CONFIG_STMMAC_ETH=y
1136 +CONFIG_DWMAC_GENERIC=m
1137 +CONFIG_AQUANTIA_PHY=y
1138 +CONFIG_BROADCOM_PHY=m
1139 +CONFIG_BCM54140_PHY=m
1140 +CONFIG_MARVELL_PHY=m
1141 +CONFIG_MARVELL_10G_PHY=m
1142 +CONFIG_MICREL_PHY=y
1143 +CONFIG_MICROSEMI_PHY=y
1144 +CONFIG_NXP_C45_TJA11XX_PHY=y
1145 +CONFIG_NXP_TJA11XX_PHY=y
1146 +CONFIG_AT803X_PHY=y
1147 +CONFIG_REALTEK_PHY=y
1148 +CONFIG_ROCKCHIP_PHY=y
1149 +CONFIG_VITESSE_PHY=y
ac4b9f 1150 +CONFIG_CAN_FLEXCAN=y
7d0d56 1151 +CONFIG_MDIO_BITBANG=y
W 1152 +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
1153 +CONFIG_MDIO_BUS_MUX_MMIOREG=y
1154 +CONFIG_USB_PEGASUS=m
1155 +CONFIG_USB_RTL8150=m
1156 +CONFIG_USB_RTL8152=y
1157 +CONFIG_USB_LAN78XX=m
1158 +CONFIG_USB_USBNET=y
1159 +CONFIG_USB_NET_AX8817X=m
1160 +CONFIG_USB_NET_AX88179_178A=m
1161 +CONFIG_USB_NET_CDCETHER=m
1162 +CONFIG_USB_NET_CDC_NCM=m
1163 +CONFIG_USB_NET_DM9601=m
1164 +CONFIG_USB_NET_SR9800=m
1165 +CONFIG_USB_NET_SMSC75XX=m
1166 +CONFIG_USB_NET_SMSC95XX=m
1167 +CONFIG_USB_NET_NET1080=m
1168 +CONFIG_USB_NET_PLUSB=m
1169 +CONFIG_USB_NET_MCS7830=m
1170 +CONFIG_USB_NET_CDC_SUBSET=m
1171 +CONFIG_USB_NET_ZAURUS=m
1172 +CONFIG_HOSTAP=y
1173 +CONFIG_WL18XX=m
1174 +CONFIG_WLCORE_SDIO=m
1175 +CONFIG_XEN_NETDEV_BACKEND=m
1176 +CONFIG_IVSHMEM_NET=y
1177 +CONFIG_INPUT_EVDEV=y
1178 +CONFIG_KEYBOARD_ADC=m
1179 +CONFIG_KEYBOARD_GPIO=y
1180 +CONFIG_KEYBOARD_RPMSG=y
1181 +CONFIG_KEYBOARD_SNVS_PWRKEY=y
1182 +CONFIG_KEYBOARD_BBNSM_PWRKEY=y
1183 +CONFIG_KEYBOARD_IMX_SC_KEY=y
1184 +CONFIG_KEYBOARD_CROS_EC=y
1185 +CONFIG_INPUT_TOUCHSCREEN=y
1186 +CONFIG_TOUCHSCREEN_ATMEL_MXT=m
1187 +CONFIG_TOUCHSCREEN_EXC3000=m
1188 +CONFIG_TOUCHSCREEN_GOODIX=m
1189 +CONFIG_TOUCHSCREEN_EDT_FT5X06=m
1190 +CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=m
1191 +CONFIG_INPUT_MISC=y
1192 +CONFIG_INPUT_PWM_BEEPER=m
1193 +CONFIG_INPUT_PWM_VIBRA=m
1194 +# CONFIG_SERIO_SERPORT is not set
1195 +CONFIG_SERIO_AMBAKMI=y
1196 +CONFIG_LEGACY_PTY_COUNT=16
1197 +CONFIG_SERIAL_8250=y
1198 +CONFIG_SERIAL_8250_CONSOLE=y
1199 +CONFIG_SERIAL_8250_EXTENDED=y
1200 +CONFIG_SERIAL_8250_SHARE_IRQ=y
1201 +CONFIG_SERIAL_8250_DW=y
1202 +CONFIG_SERIAL_OF_PLATFORM=y
1203 +CONFIG_SERIAL_AMBA_PL011=y
1204 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1205 +CONFIG_SERIAL_IMX=y
1206 +CONFIG_SERIAL_IMX_CONSOLE=y
1207 +CONFIG_SERIAL_XILINX_PS_UART=y
1208 +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
1209 +CONFIG_SERIAL_FSL_LPUART=y
1210 +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
1211 +CONFIG_SERIAL_FSL_LINFLEXUART=y
1212 +CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
1213 +CONFIG_SERIAL_DEV_BUS=y
1214 +CONFIG_VIRTIO_CONSOLE=y
1215 +CONFIG_IPMI_HANDLER=m
1216 +CONFIG_IPMI_DEVICE_INTERFACE=m
1217 +CONFIG_IPMI_SI=m
1218 +CONFIG_TCG_TPM=y
1219 +CONFIG_TCG_TIS_I2C_INFINEON=y
1220 +CONFIG_I2C_CHARDEV=y
1221 +CONFIG_I2C_MUX=y
1222 +CONFIG_I2C_MUX_GPIO=y
1223 +CONFIG_I2C_MUX_PCA954x=y
1224 +CONFIG_I2C_DESIGNWARE_PLATFORM=y
1225 +CONFIG_I2C_GPIO=m
1226 +CONFIG_I2C_IMX=y
1227 +CONFIG_I2C_IMX_LPI2C=y
1228 +CONFIG_I2C_RK3X=y
1229 +CONFIG_I2C_RPBUS=y
1230 +CONFIG_I2C_CROS_EC_TUNNEL=y
1231 +CONFIG_I2C_SLAVE_EEPROM=y
1232 +CONFIG_I3C=y
1233 +CONFIG_SVC_I3C_MASTER=y
1234 +CONFIG_SPI=y
1235 +CONFIG_SPI_CADENCE_QUADSPI=y
1236 +CONFIG_SPI_DESIGNWARE=m
1237 +CONFIG_SPI_DW_DMA=y
1238 +CONFIG_SPI_DW_MMIO=m
1239 +CONFIG_SPI_FSL_LPSPI=y
1240 +CONFIG_SPI_FSL_QUADSPI=y
1241 +CONFIG_SPI_NXP_FLEXSPI=y
1242 +CONFIG_SPI_IMX=y
1243 +CONFIG_SPI_FSL_DSPI=y
1244 +CONFIG_SPI_PL022=y
1245 +CONFIG_SPI_ROCKCHIP=y
1246 +CONFIG_SPI_SPIDEV=y
1247 +CONFIG_SPI_SLAVE=y
1248 +CONFIG_SPI_SLAVE_TIME=y
1249 +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y
1250 +CONFIG_SPMI=y
1251 +CONFIG_PPS_CLIENT_GPIO=y
1252 +CONFIG_PINCTRL_MAX77620=y
1253 +CONFIG_PINCTRL_SINGLE=y
1254 +CONFIG_PINCTRL_IMX8MM=y
1255 +CONFIG_PINCTRL_IMX8MN=y
1256 +CONFIG_PINCTRL_IMX8MP=y
1257 +CONFIG_PINCTRL_IMX8MQ=y
1258 +CONFIG_PINCTRL_IMX8QM=y
1259 +CONFIG_PINCTRL_IMX8QXP=y
1260 +CONFIG_PINCTRL_IMX8DXL=y
1261 +CONFIG_PINCTRL_IMX8ULP=y
1262 +CONFIG_PINCTRL_IMX93=y
1263 +CONFIG_PINCTRL_S32V234=y
f77a70 1264 +CONFIG_GPIO_SYSFS=y
7d0d56 1265 +CONFIG_GPIO_MXC=y
W 1266 +CONFIG_POWER_RESET_BRCMSTB=y
1267 +CONFIG_POWER_RESET_XGENE=y
1268 +CONFIG_POWER_RESET_SYSCON=y
1269 +CONFIG_SYSCON_REBOOT_MODE=y
1270 +CONFIG_BATTERY_SBS=m
1271 +CONFIG_BATTERY_BQ27XXX=y
1272 +CONFIG_BATTERY_MAX17042=m
1273 +CONFIG_CHARGER_BQ25890=m
1274 +CONFIG_CHARGER_BQ25980=m
1275 +CONFIG_SENSORS_ARM_SCMI=y
1276 +CONFIG_SENSORS_ARM_SCPI=y
1277 +CONFIG_SENSORS_FP9931=y
1278 +CONFIG_SENSORS_LM90=m
1279 +CONFIG_SENSORS_PWM_FAN=m
1280 +CONFIG_SENSORS_SL28CPLD=m
1281 +CONFIG_SENSORS_INA2XX=m
1282 +CONFIG_SENSORS_INA3221=m
1283 +CONFIG_THERMAL_WRITABLE_TRIPS=y
1284 +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
1285 +CONFIG_CPU_THERMAL=y
1286 +CONFIG_THERMAL_EMULATION=y
1287 +CONFIG_IMX_SC_THERMAL=y
1288 +CONFIG_IMX8MM_THERMAL=y
1289 +CONFIG_DEVICE_THERMAL=y
1290 +CONFIG_QORIQ_THERMAL=y
1291 +CONFIG_WATCHDOG=y
1292 +CONFIG_SL28CPLD_WATCHDOG=m
1293 +CONFIG_ARM_SP805_WATCHDOG=y
1294 +CONFIG_ARM_SBSA_WATCHDOG=y
1295 +CONFIG_DW_WATCHDOG=y
1296 +CONFIG_IMX2_WDT=y
1297 +CONFIG_IMX_SC_WDT=y
1298 +CONFIG_IMX7ULP_WDT=y
1299 +CONFIG_ARM_SMC_WATCHDOG=y
1300 +CONFIG_XEN_WDT=y
1301 +CONFIG_MFD_ADP5585=y
1302 +CONFIG_MFD_BD9571MWV=y
1303 +CONFIG_MFD_AXP20X_I2C=y
1304 +CONFIG_MFD_IMX_FLEXIO=y
1305 +CONFIG_MFD_HI6421_PMIC=y
1306 +CONFIG_MFD_FP9931=y
1307 +CONFIG_MFD_MAX77620=y
1308 +CONFIG_MFD_MT6397=y
1309 +CONFIG_MFD_RK808=y
1310 +CONFIG_MFD_SEC_CORE=y
1311 +CONFIG_MFD_SL28CPLD=y
1312 +CONFIG_MFD_ROHM_BD718XX=y
1313 +CONFIG_MFD_WCD934X=m
1314 +CONFIG_REGULATOR_FIXED_VOLTAGE=y
1315 +CONFIG_REGULATOR_AXP20X=y
1316 +CONFIG_REGULATOR_BD718XX=y
1317 +CONFIG_REGULATOR_BD9571MWV=y
1318 +CONFIG_REGULATOR_FAN53555=y
1319 +CONFIG_REGULATOR_GPIO=y
1320 +CONFIG_REGULATOR_HI6421V530=y
1321 +CONFIG_REGULATOR_MAX77620=y
1322 +CONFIG_REGULATOR_MAX8973=y
1323 +CONFIG_REGULATOR_FP9931=y
1324 +CONFIG_REGULATOR_MP8859=y
1325 +CONFIG_REGULATOR_MT6358=y
1326 +CONFIG_REGULATOR_MT6397=y
1327 +CONFIG_REGULATOR_PCA9450=y
1328 +CONFIG_REGULATOR_PF8X00=y
1329 +CONFIG_REGULATOR_PFUZE100=y
1330 +CONFIG_REGULATOR_PWM=y
1331 +CONFIG_REGULATOR_QCOM_SPMI=y
1332 +CONFIG_REGULATOR_RK808=y
1333 +CONFIG_REGULATOR_S2MPS11=y
1334 +CONFIG_REGULATOR_TPS65132=m
1335 +CONFIG_REGULATOR_VCTRL=m
1336 +CONFIG_RC_CORE=m
1337 +CONFIG_RC_DECODERS=y
1338 +CONFIG_IR_IMON_DECODER=m
1339 +CONFIG_IR_JVC_DECODER=m
1340 +CONFIG_IR_MCE_KBD_DECODER=m
1341 +CONFIG_IR_NEC_DECODER=m
1342 +CONFIG_IR_RC5_DECODER=m
1343 +CONFIG_IR_RC6_DECODER=m
1344 +CONFIG_IR_RCMM_DECODER=m
1345 +CONFIG_IR_SANYO_DECODER=m
1346 +CONFIG_IR_SHARP_DECODER=m
1347 +CONFIG_IR_SONY_DECODER=m
1348 +CONFIG_IR_XMP_DECODER=m
1349 +CONFIG_RC_DEVICES=y
1350 +CONFIG_IR_GPIO_CIR=m
1351 +CONFIG_MEDIA_SUPPORT=y
f77a70 1352 +CONFIG_MEDIA_SUPPORT_FILTER=y
7d0d56 1353 +CONFIG_MEDIA_CAMERA_SUPPORT=y
W 1354 +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
1355 +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
1356 +CONFIG_MEDIA_SDR_SUPPORT=y
1357 +CONFIG_MEDIA_PLATFORM_SUPPORT=y
1358 +# CONFIG_DVB_NET is not set
1359 +CONFIG_MEDIA_USB_SUPPORT=y
1360 +CONFIG_USB_VIDEO_CLASS=m
1361 +CONFIG_V4L_PLATFORM_DRIVERS=y
1362 +CONFIG_SDR_PLATFORM_DRIVERS=y
1363 +CONFIG_V4L_MEM2MEM_DRIVERS=y
1364 +CONFIG_VIDEO_MX8_CAPTURE=y
1365 +CONFIG_VIDEO_MXC_CAPTURE=y
1366 +CONFIG_VIDEO_MXC_CSI_CAMERA=y
1367 +CONFIG_MXC_MIPI_CSI=y
1368 +CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y
1369 +CONFIG_VIDEO_AMPHION_VPU=y
1370 +CONFIG_VIDEO_IMX8_JPEG=m
1371 +CONFIG_VIDEO_HANTRO=m
1372 +CONFIG_VIDEO_IMX219=m
1373 +CONFIG_VIDEO_OV5640=y
1374 +CONFIG_VIDEO_OV5645=m
1375 +CONFIG_VIDEO_AP1302=y
1376 +CONFIG_VIDEO_MT9M114=y
1377 +CONFIG_IMX_DPU_CORE=y
1378 +CONFIG_IMX8MM_LCDIF_CORE=y
1379 +CONFIG_IMX_LCDIFV3_CORE=y
1380 +CONFIG_DRM=y
1381 +CONFIG_DRM_I2C_NXP_TDA998X=m
1382 +CONFIG_DRM_MALI_DISPLAY=m
1383 +CONFIG_DRM_NOUVEAU=m
1384 +CONFIG_DRM_RCAR_DW_HDMI=m
1385 +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
1386 +CONFIG_DRM_PANEL_LVDS=m
1387 +CONFIG_DRM_PANEL_SIMPLE=y
1388 +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
1389 +CONFIG_DRM_PANEL_RAYDIUM_RM67191=y
1390 +CONFIG_DRM_PANEL_RAYDIUM_RM68200=y
1391 +CONFIG_DRM_PANEL_ROCKTECK_HIMAX8394F=y
1392 +CONFIG_DRM_PANEL_SEIKO_43WVF1G=y
1393 +CONFIG_DRM_PANEL_SITRONIX_ST7703=m
1394 +CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
1395 +CONFIG_DRM_PANEL_WKS_101WX001=y
1396 +CONFIG_DRM_DISPLAY_CONNECTOR=m
1397 +CONFIG_DRM_LONTIUM_LT8912B=m
1398 +CONFIG_DRM_LONTIUM_LT9611=m
1399 +CONFIG_DRM_LONTIUM_LT9611UXC=m
1400 +CONFIG_DRM_FSL_IMX_LVDS_BRIDGE=y
1401 +CONFIG_DRM_NWL_MIPI_DSI=y
1402 +CONFIG_DRM_NXP_SEIKO_43WVFIG=y
1403 +CONFIG_DRM_PARADE_PS8640=m
1404 +CONFIG_DRM_SII902X=m
1405 +CONFIG_DRM_SIMPLE_BRIDGE=m
1406 +CONFIG_DRM_THINE_THC63LVD1024=m
1407 +CONFIG_DRM_TI_SN65DSI86=m
1408 +CONFIG_DRM_I2C_ADV7511=y
1409 +CONFIG_DRM_I2C_ADV7511_AUDIO=y
1410 +CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
1411 +CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
1412 +CONFIG_DRM_DW_HDMI_GP_AUDIO=y
1413 +CONFIG_DRM_DW_HDMI_CEC=m
1414 +CONFIG_DRM_ITE_IT6263=y
1415 +CONFIG_DRM_ITE_IT6161=y
1416 +CONFIG_DRM_IMX=y
1417 +CONFIG_DRM_IMX_LCDIF_MUX_DISPLAY=y
1418 +CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
1419 +CONFIG_DRM_IMX_TVE=y
1420 +CONFIG_DRM_IMX_LDB=y
1421 +CONFIG_DRM_IMX8QM_LDB=y
1422 +CONFIG_DRM_IMX8QXP_LDB=y
1423 +CONFIG_DRM_IMX8MP_LDB=y
1424 +CONFIG_DRM_IMX93_LDB=y
1425 +CONFIG_DRM_IMX_DW_MIPI_DSI=y
1426 +CONFIG_DRM_IMX93_PARALLEL_DISPLAY_FORMAT=y
1427 +CONFIG_DRM_IMX_HDMI=y
1428 +CONFIG_DRM_IMX_SEC_DSIM=y
1429 +CONFIG_DRM_IMX_DCNANO=y
1430 +CONFIG_DRM_IMX_DCSS=y
1431 +CONFIG_DRM_IMX_CDNS_MHDP=y
1432 +CONFIG_DRM_ETNAVIV=m
1433 +CONFIG_DRM_HISI_HIBMC=m
1434 +CONFIG_DRM_HISI_KIRIN=m
1435 +CONFIG_DRM_MXSFB=y
1436 +CONFIG_DRM_PL111=m
1437 +CONFIG_DRM_LIMA=m
1438 +CONFIG_DRM_PANFROST=m
1439 +CONFIG_FB=y
1440 +CONFIG_FB_ARMCLCD=y
1441 +CONFIG_FB_EFI=y
1442 +CONFIG_FB_MXC_EINK_V2_PANEL=y
1443 +CONFIG_BACKLIGHT_PWM=y
1444 +CONFIG_BACKLIGHT_LP855X=m
1445 +CONFIG_BACKLIGHT_GPIO=y
f77a70 1446 +CONFIG_FRAMEBUFFER_CONSOLE=y
7d0d56 1447 +CONFIG_LOGO=y
W 1448 +# CONFIG_LOGO_LINUX_MONO is not set
1449 +# CONFIG_LOGO_LINUX_VGA16 is not set
1450 +CONFIG_SOUND=y
1451 +CONFIG_SND=y
1452 +CONFIG_SND_ALOOP=m
1453 +CONFIG_SND_USB_AUDIO=m
1454 +CONFIG_SND_SOC=y
1455 +CONFIG_SND_SOC_FSL_ASRC=m
1456 +CONFIG_SND_SOC_FSL_MQS=m
1457 +CONFIG_SND_SOC_FSL_MICFIL=m
1458 +CONFIG_SND_SOC_FSL_EASRC=m
1459 +CONFIG_SND_SOC_FSL_XCVR=m
1460 +CONFIG_SND_SOC_FSL_ESAI_CLIENT=y
1461 +CONFIG_SND_SOC_FSL_RPMSG=m
1462 +CONFIG_SND_IMX_SOC=m
1463 +CONFIG_SND_SOC_IMX_SGTL5000=m
1464 +CONFIG_SND_SOC_IMX_SPDIF=m
1465 +CONFIG_SND_SOC_FSL_ASOC_CARD=m
1466 +CONFIG_SND_SOC_IMX_AUDMIX=m
1467 +CONFIG_SND_SOC_IMX_HDMI=m
1468 +CONFIG_SND_SOC_IMX_CARD=m
1469 +CONFIG_SND_SOC_IMX_PCM512X=m
1470 +CONFIG_SND_SOC_SOF_TOPLEVEL=y
1471 +CONFIG_SND_SOC_SOF_OF=m
1472 +CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y
1473 +CONFIG_SND_SOC_SOF_IMX8=m
1474 +CONFIG_SND_SOC_SOF_IMX8M=m
1475 +CONFIG_SND_SOC_SOF_IMX8ULP=m
1476 +CONFIG_SND_SOC_AK4613=m
1477 +CONFIG_SND_SOC_BT_SCO=y
1478 +CONFIG_SND_SOC_CROS_EC_CODEC=m
1479 +CONFIG_SND_SOC_CS42XX8_I2C=y
1480 +CONFIG_SND_SOC_DMIC=m
1481 +CONFIG_SND_SOC_ES7134=m
1482 +CONFIG_SND_SOC_ES7241=m
1483 +CONFIG_SND_SOC_GTM601=m
1484 +CONFIG_SND_SOC_MAX98357A=m
1485 +CONFIG_SND_SOC_MAX98927=m
1486 +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
1487 +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
1488 +CONFIG_SND_SOC_PCM3168A_I2C=m
1489 +CONFIG_SND_SOC_RT5659=m
1490 +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
1491 +CONFIG_SND_SOC_SIMPLE_MUX=m
1492 +CONFIG_SND_SOC_SPDIF=m
1493 +CONFIG_SND_SOC_TAS571X=m
1494 +CONFIG_SND_SOC_WCD934X=m
1495 +CONFIG_SND_SOC_WM8524=y
1496 +CONFIG_SND_SOC_WM8904=m
1497 +CONFIG_SND_SOC_WM8960=m
1498 +CONFIG_SND_SOC_WM8962=m
1499 +CONFIG_SND_SOC_WSA881X=m
1500 +CONFIG_SND_SOC_RPMSG_WM8960=m
1501 +CONFIG_SND_SOC_RPMSG_AK4497=m
1502 +CONFIG_SND_SOC_LPASS_WSA_MACRO=m
1503 +CONFIG_SND_SOC_LPASS_VA_MACRO=m
1504 +CONFIG_SND_SIMPLE_CARD=y
1505 +CONFIG_SND_AUDIO_GRAPH_CARD=y
f77a70 1506 +CONFIG_HID_A4TECH=y
G 1507 +CONFIG_HID_APPLE=y
1508 +CONFIG_HID_BELKIN=y
1509 +CONFIG_HID_CHERRY=y
1510 +CONFIG_HID_CHICONY=y
1511 +CONFIG_HID_CYPRESS=y
1512 +CONFIG_HID_EZKEY=y
1513 +CONFIG_HID_ITE=y
1514 +CONFIG_HID_KENSINGTON=y
1515 +CONFIG_HID_LOGITECH=y
1516 +CONFIG_HID_REDRAGON=y
1517 +CONFIG_HID_MICROSOFT=y
1518 +CONFIG_HID_MONTEREY=y
7d0d56 1519 +CONFIG_HID_MULTITOUCH=m
W 1520 +CONFIG_I2C_HID_ACPI=m
1521 +CONFIG_I2C_HID_OF=m
1522 +CONFIG_USB_CONN_GPIO=y
1523 +CONFIG_USB=y
1524 +CONFIG_USB_OTG=y
1525 +CONFIG_USB_XHCI_HCD=y
1526 +CONFIG_USB_XHCI_PCI_RENESAS=m
1527 +CONFIG_USB_EHCI_HCD=y
1528 +CONFIG_USB_EHCI_HCD_PLATFORM=y
1529 +CONFIG_USB_OHCI_HCD=y
1530 +CONFIG_USB_OHCI_HCD_PLATFORM=y
1531 +CONFIG_USB_HCD_TEST_MODE=y
1532 +CONFIG_USB_ACM=m
1533 +CONFIG_USB_STORAGE=y
1534 +CONFIG_USB_UAS=y
1535 +CONFIG_USB_CDNS_SUPPORT=y
1536 +CONFIG_USB_CDNS3=y
1537 +CONFIG_USB_CDNS3_GADGET=y
1538 +CONFIG_USB_CDNS3_HOST=y
1539 +CONFIG_USB_MUSB_HDRC=y
1540 +CONFIG_USB_DWC3=y
1541 +CONFIG_USB_DWC2=y
1542 +CONFIG_USB_CHIPIDEA=y
1543 +CONFIG_USB_CHIPIDEA_UDC=y
1544 +CONFIG_USB_CHIPIDEA_HOST=y
1545 +CONFIG_USB_ISP1760=y
1546 +CONFIG_USB_SERIAL=y
1547 +CONFIG_USB_SERIAL_CONSOLE=y
1548 +CONFIG_USB_SERIAL_GENERIC=y
1549 +CONFIG_USB_SERIAL_SIMPLE=y
1550 +CONFIG_USB_SERIAL_CP210X=m
1551 +CONFIG_USB_SERIAL_FTDI_SIO=y
1552 +CONFIG_USB_SERIAL_OPTION=m
1553 +CONFIG_USB_TEST=m
1554 +CONFIG_USB_EHSET_TEST_FIXTURE=y
1555 +CONFIG_USB_HSIC_USB3503=y
1556 +CONFIG_NOP_USB_XCEIV=y
1557 +CONFIG_USB_MXS_PHY=y
1558 +CONFIG_USB_ULPI=y
1559 +CONFIG_USB_GADGET=y
1560 +CONFIG_USB_SNP_UDC_PLAT=y
1561 +CONFIG_USB_BDC_UDC=y
1562 +CONFIG_USB_CONFIGFS=y
1563 +CONFIG_USB_CONFIGFS_SERIAL=y
1564 +CONFIG_USB_CONFIGFS_ACM=y
1565 +CONFIG_USB_CONFIGFS_OBEX=y
1566 +CONFIG_USB_CONFIGFS_NCM=y
1567 +CONFIG_USB_CONFIGFS_ECM=y
1568 +CONFIG_USB_CONFIGFS_ECM_SUBSET=y
1569 +CONFIG_USB_CONFIGFS_RNDIS=y
1570 +CONFIG_USB_CONFIGFS_EEM=y
1571 +CONFIG_USB_CONFIGFS_MASS_STORAGE=y
1572 +CONFIG_USB_CONFIGFS_F_LB_SS=y
1573 +CONFIG_USB_CONFIGFS_F_FS=y
1574 +CONFIG_USB_CONFIGFS_F_UAC1=y
1575 +CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
1576 +CONFIG_USB_CONFIGFS_F_UAC2=y
1577 +CONFIG_USB_CONFIGFS_F_MIDI=y
1578 +CONFIG_USB_CONFIGFS_F_HID=y
1579 +CONFIG_USB_CONFIGFS_F_UVC=y
1580 +CONFIG_USB_ZERO=m
1581 +CONFIG_USB_AUDIO=m
1582 +CONFIG_USB_ETH=m
1583 +CONFIG_USB_MASS_STORAGE=m
1584 +CONFIG_USB_G_SERIAL=m
1585 +CONFIG_TYPEC=y
1586 +CONFIG_TYPEC_TCPM=y
1587 +CONFIG_TYPEC_TCPCI=y
1588 +CONFIG_TYPEC_FUSB302=m
1589 +CONFIG_TYPEC_TPS6598X=m
1590 +CONFIG_TYPEC_HD3SS3220=m
1591 +CONFIG_TYPEC_SWITCH_GPIO=y
1592 +CONFIG_MMC=y
1593 +CONFIG_MMC_BLOCK_MINORS=32
1594 +CONFIG_MMC_ARMMMCI=y
1595 +CONFIG_MMC_SDHCI=y
1596 +CONFIG_MMC_SDHCI_ACPI=y
1597 +CONFIG_MMC_SDHCI_PLTFM=y
1598 +CONFIG_MMC_SDHCI_OF_ARASAN=y
1599 +CONFIG_MMC_SDHCI_OF_ESDHC=y
1600 +CONFIG_MMC_SDHCI_CADENCE=y
1601 +CONFIG_MMC_SDHCI_ESDHC_IMX=y
1602 +CONFIG_MMC_SDHCI_F_SDH30=y
1603 +CONFIG_MMC_SPI=y
1604 +CONFIG_MMC_DW=y
1605 +CONFIG_MMC_DW_EXYNOS=y
1606 +CONFIG_MMC_DW_HI3798CV200=y
1607 +CONFIG_MMC_DW_K3=y
1608 +CONFIG_MMC_MTK=y
1609 +CONFIG_MMC_SDHCI_XENON=y
1610 +CONFIG_MMC_SDHCI_AM654=y
1611 +CONFIG_SCSI_UFSHCD=y
1612 +CONFIG_SCSI_UFSHCD_PLATFORM=y
1613 +CONFIG_NEW_LEDS=y
1614 +CONFIG_LEDS_CLASS=y
1615 +CONFIG_LEDS_CLASS_MULTICOLOR=m
1616 +CONFIG_LEDS_LM3692X=m
1617 +CONFIG_LEDS_PCA9532=m
1618 +CONFIG_LEDS_GPIO=y
1619 +CONFIG_LEDS_PCA995X=m
1620 +CONFIG_LEDS_PWM=y
1621 +CONFIG_LEDS_SYSCON=y
1622 +CONFIG_LEDS_TRIGGER_TIMER=y
1623 +CONFIG_LEDS_TRIGGER_DISK=y
1624 +CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1625 +CONFIG_LEDS_TRIGGER_CPU=y
1626 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
1627 +CONFIG_LEDS_TRIGGER_PANIC=y
1628 +CONFIG_EDAC=y
1629 +CONFIG_EDAC_GHES=y
1630 +CONFIG_EDAC_LAYERSCAPE=m
1631 +CONFIG_EDAC_SYNOPSYS=y
1632 +CONFIG_RTC_CLASS=y
2b23f8 1633 +CONFIG_RTC_DRV_ISL1208=y
7d0d56 1634 +CONFIG_DMADEVICES=y
W 1635 +CONFIG_FSL_EDMA=y
1636 +CONFIG_FSL_QDMA=m
1637 +CONFIG_FSL_EDMA_V3=y
1638 +CONFIG_IMX_SDMA=y
1639 +CONFIG_MV_XOR_V2=y
1640 +CONFIG_MXS_DMA=y
1641 +CONFIG_MXC_PXP_V3=y
1642 +CONFIG_PL330_DMA=y
1643 +CONFIG_QCOM_HIDMA_MGMT=y
1644 +CONFIG_QCOM_HIDMA=y
1645 +CONFIG_DW_EDMA=y
1646 +CONFIG_DW_EDMA_PCIE=y
1647 +CONFIG_FSL_DPAA2_QDMA=m
1648 +CONFIG_DMATEST=y
1649 +CONFIG_DMABUF_HEAPS=y
1650 +CONFIG_DMABUF_HEAPS_SYSTEM=y
1651 +CONFIG_DMABUF_HEAPS_CMA=y
1652 +CONFIG_DMABUF_HEAPS_DSP=y
1653 +CONFIG_UIO_PCI_GENERIC=y
1654 +CONFIG_UIO_IVSHMEM=y
1655 +CONFIG_VFIO=y
1656 +CONFIG_VFIO_PCI=y
1657 +CONFIG_VFIO_FSL_MC=y
1658 +CONFIG_VIRTIO_PCI=y
1659 +CONFIG_VIRTIO_BALLOON=y
1660 +CONFIG_VIRTIO_MMIO=y
1661 +CONFIG_VIRTIO_IVSHMEM=y
1662 +CONFIG_XEN_GNTDEV=y
1663 +CONFIG_XEN_GRANT_DEV_ALLOC=y
1664 +CONFIG_STAGING=y
1665 +CONFIG_STAGING_MEDIA=y
1666 +CONFIG_VIDEO_IMX_CAPTURE=y
1667 +CONFIG_IMX8_MEDIA_DEVICE=m
1668 +CONFIG_MHDP_HDMIRX=y
1669 +CONFIG_MHDP_HDMIRX_CEC=y
1670 +CONFIG_FSL_DPAA2=y
1671 +CONFIG_FSL_PPFE=y
1672 +CONFIG_FSL_PPFE_UTIL_DISABLED=y
1673 +CONFIG_ETHOSU=y
1674 +CONFIG_CHROME_PLATFORMS=y
1675 +CONFIG_CROS_EC=y
1676 +CONFIG_CROS_EC_I2C=y
1677 +CONFIG_CROS_EC_SPI=y
1678 +CONFIG_CROS_EC_CHARDEV=m
1679 +CONFIG_CLK_VEXPRESS_OSC=y
1680 +CONFIG_COMMON_CLK_RK808=y
1681 +CONFIG_COMMON_CLK_SCMI=y
1682 +CONFIG_COMMON_CLK_SCPI=y
1683 +CONFIG_COMMON_CLK_CS2000_CP=y
1684 +CONFIG_COMMON_CLK_FSL_SAI=y
1685 +CONFIG_COMMON_CLK_S2MPS11=y
1686 +CONFIG_COMMON_CLK_XGENE=y
1687 +CONFIG_COMMON_CLK_PWM=y
1688 +CONFIG_COMMON_CLK_VC5=y
1689 +CONFIG_CLK_IMX8MM=y
1690 +CONFIG_CLK_IMX8MN=y
1691 +CONFIG_CLK_IMX8MP=y
1692 +CONFIG_CLK_IMX8MQ=y
1693 +CONFIG_CLK_IMX8QXP=y
1694 +CONFIG_CLK_IMX8ULP=y
1695 +CONFIG_CLK_IMX93=y
1696 +CONFIG_HWSPINLOCK=y
1697 +CONFIG_ARM_MHU=y
1698 +CONFIG_IMX_MBOX=y
1699 +CONFIG_PLATFORM_MHU=y
1700 +CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
1701 +CONFIG_ARM_SMMU=y
1702 +CONFIG_ARM_SMMU_V3=y
1703 +CONFIG_REMOTEPROC=y
1704 +CONFIG_IMX_REMOTEPROC=y
1705 +CONFIG_IMX_DSP_REMOTEPROC=m
1706 +CONFIG_RPMSG_CHAR=m
1707 +CONFIG_RPMSG_CTRL=m
1708 +CONFIG_RPMSG_QCOM_GLINK_RPM=y
1709 +CONFIG_SOUNDWIRE=m
1710 +CONFIG_SOUNDWIRE_QCOM=m
1711 +CONFIG_SOC_BRCMSTB=y
1712 +CONFIG_FSL_DPAA=y
1713 +CONFIG_FSL_MC_DPIO=y
1714 +CONFIG_FSL_RCPM=y
1715 +CONFIG_FSL_QIXIS=y
1716 +CONFIG_SOC_TI=y
1717 +CONFIG_EXTCON_PTN5150=m
1718 +CONFIG_EXTCON_USB_GPIO=y
1719 +CONFIG_EXTCON_USBC_CROS_EC=y
1720 +CONFIG_IIO=y
1721 +CONFIG_FXLS8962AF_I2C=m
1722 +CONFIG_IIO_ST_ACCEL_3AXIS=m
1723 +CONFIG_IMX8QXP_ADC=y
1724 +CONFIG_IMX93_ADC=y
2f7a23 1725 +CONFIG_MS1112=y
2b23f8 1726 +CONFIG_BMG160=m
7d0d56 1727 +CONFIG_IIO_ST_GYRO_3AXIS=m
2b23f8 1728 +CONFIG_MAX30100=m
G 1729 +CONFIG_MAX30102=m
1730 +CONFIG_DHT11=y
1731 +CONFIG_HDC100X=y
1732 +CONFIG_HTS221=y
7d0d56 1733 +CONFIG_FXOS8700_I2C=y
W 1734 +CONFIG_RPMSG_IIO_PEDOMETER=m
1735 +CONFIG_INV_MPU6050_I2C=m
1736 +CONFIG_IIO_ST_LSM6DSX=y
1737 +CONFIG_SENSORS_ISL29018=y
1738 +CONFIG_IIO_ST_MAGN_3AXIS=m
1739 +CONFIG_MPL3115=y
1740 +CONFIG_MS5611=m
1741 +CONFIG_MS5611_I2C=m
1742 +CONFIG_PWM=y
1743 +CONFIG_PWM_ADP5585=y
1744 +CONFIG_PWM_CROS_EC=m
1745 +CONFIG_PWM_FSL_FTM=m
1746 +CONFIG_PWM_IMX27=y
1747 +CONFIG_PWM_RPCHIP=y
1748 +CONFIG_PWM_SL28CPLD=m
1749 +CONFIG_SL28CPLD_INTC=y
1750 +CONFIG_RESET_IMX7=y
1751 +CONFIG_RESET_IMX8ULP_SIM=y
1752 +CONFIG_PHY_XGENE=y
1753 +CONFIG_PHY_MIXEL_LVDS=y
1754 +CONFIG_PHY_MIXEL_LVDS_COMBO=y
1755 +CONFIG_PHY_CADENCE_SALVO=y
1756 +CONFIG_PHY_FSL_IMX8MP_LVDS=y
1757 +CONFIG_PHY_FSL_IMX93_MIPI_DPHY=y
1758 +CONFIG_PHY_MIXEL_MIPI_DPHY=y
1759 +CONFIG_PHY_FSL_IMX8M_PCIE=y
1760 +CONFIG_PHY_FSL_IMX8Q_PCIE=y
1761 +CONFIG_PHY_SAMSUNG_HDMI_PHY=y
1762 +CONFIG_PHY_QCOM_USB_HS=y
1763 +CONFIG_PHY_SAMSUNG_USB2=y
1764 +CONFIG_ARM_CCI_PMU=m
1765 +CONFIG_ARM_CCN=m
1766 +CONFIG_ARM_CMN=m
1767 +CONFIG_ARM_SMMU_V3_PMU=m
1768 +CONFIG_ARM_DSU_PMU=m
1769 +CONFIG_FSL_IMX8_DDR_PMU=y
1770 +CONFIG_FSL_IMX9_DDR_PMU=y
1771 +CONFIG_ARM_SPE_PMU=m
1772 +CONFIG_ARM_DMC620_PMU=m
1773 +CONFIG_HISI_PMU=y
1774 +CONFIG_NVMEM_IMX_OCOTP=y
1775 +CONFIG_NVMEM_IMX_OCOTP_SCU=y
1776 +CONFIG_NVMEM_RMEM=m
1777 +CONFIG_FPGA=y
1778 +CONFIG_FPGA_BRIDGE=m
1779 +CONFIG_ALTERA_FREEZE_BRIDGE=m
1780 +CONFIG_FPGA_REGION=m
1781 +CONFIG_OF_FPGA_REGION=m
1782 +CONFIG_TEE=y
1783 +CONFIG_OPTEE=y
1784 +CONFIG_MUX_MMIO=y
1785 +CONFIG_SLIM_QCOM_CTRL=m
1786 +CONFIG_MXC_SIM=y
1787 +CONFIG_MXC_GPU_VIV=y
1788 +CONFIG_MXC_EMVSIM=y
1789 +CONFIG_EXT2_FS=y
1790 +CONFIG_EXT3_FS=y
1791 +CONFIG_EXT4_FS_POSIX_ACL=y
1792 +CONFIG_FANOTIFY=y
1793 +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
1794 +CONFIG_QUOTA=y
1795 +CONFIG_AUTOFS4_FS=y
1796 +CONFIG_FUSE_FS=m
1797 +CONFIG_CUSE=m
1798 +CONFIG_OVERLAY_FS=m
1799 +CONFIG_VFAT_FS=y
f77a70 1800 +CONFIG_EXFAT_FS=y
G 1801 +CONFIG_NTFS_FS=y
1802 +CONFIG_NTFS_RW=y
1803 +CONFIG_NTFS3_FS=y
1804 +CONFIG_NTFS3_64BIT_CLUSTER=y
1805 +CONFIG_NTFS3_LZX_XPRESS=y
1806 +CONFIG_NTFS3_FS_POSIX_ACL=y
7d0d56 1807 +CONFIG_TMPFS_POSIX_ACL=y
W 1808 +CONFIG_HUGETLBFS=y
1809 +CONFIG_EFIVAR_FS=y
1810 +CONFIG_JFFS2_FS=y
1811 +CONFIG_NFS_FS=y
1812 +CONFIG_NFS_V4=y
1813 +CONFIG_NFS_V4_1=y
1814 +CONFIG_NFS_V4_2=y
1815 +CONFIG_ROOT_NFS=y
1816 +CONFIG_NLS_CODEPAGE_437=y
f77a70 1817 +CONFIG_NLS_CODEPAGE_936=y
G 1818 +CONFIG_NLS_CODEPAGE_950=y
1819 +CONFIG_NLS_CODEPAGE_874=y
7d0d56 1820 +CONFIG_NLS_ISO8859_1=y
f77a70 1821 +CONFIG_NLS_UTF8=y
7d0d56 1822 +CONFIG_TRUSTED_KEYS=m
W 1823 +# CONFIG_TRUSTED_KEYS_TPM is not set
1824 +# CONFIG_TRUSTED_KEYS_TEE is not set
1825 +CONFIG_SECURITY=y
1826 +CONFIG_CRYPTO_USER=y
1827 +CONFIG_CRYPTO_TEST=m
1828 +CONFIG_CRYPTO_ANUBIS=m
1829 +CONFIG_CRYPTO_ARIA=m
1830 +CONFIG_CRYPTO_BLOWFISH=m
1831 +CONFIG_CRYPTO_CAMELLIA=m
1832 +CONFIG_CRYPTO_CAST5=m
1833 +CONFIG_CRYPTO_CAST6=m
1834 +CONFIG_CRYPTO_FCRYPT=m
1835 +CONFIG_CRYPTO_KHAZAD=m
1836 +CONFIG_CRYPTO_SEED=m
1837 +CONFIG_CRYPTO_SERPENT=m
1838 +CONFIG_CRYPTO_TEA=m
1839 +CONFIG_CRYPTO_TWOFISH=m
1840 +CONFIG_CRYPTO_ARC4=m
1841 +CONFIG_CRYPTO_CFB=m
1842 +CONFIG_CRYPTO_CTS=m
1843 +CONFIG_CRYPTO_LRW=m
1844 +CONFIG_CRYPTO_OFB=m
1845 +CONFIG_CRYPTO_PCBC=m
1846 +CONFIG_CRYPTO_CHACHA20POLY1305=m
1847 +CONFIG_CRYPTO_ECHAINIV=y
1848 +CONFIG_CRYPTO_TLS=m
f77a70 1849 +CONFIG_CRYPTO_BLAKE2B=m
7d0d56 1850 +CONFIG_CRYPTO_MD4=m
W 1851 +CONFIG_CRYPTO_RMD160=m
1852 +CONFIG_CRYPTO_STREEBOG=m
1853 +CONFIG_CRYPTO_VMAC=m
1854 +CONFIG_CRYPTO_WP512=m
1855 +CONFIG_CRYPTO_XCBC=m
f77a70 1856 +CONFIG_CRYPTO_XXHASH=m
G 1857 +CONFIG_CRYPTO_LZO=y
1858 +CONFIG_CRYPTO_ZSTD=y
7d0d56 1859 +CONFIG_CRYPTO_ANSI_CPRNG=y
W 1860 +CONFIG_CRYPTO_USER_API_HASH=m
1861 +CONFIG_CRYPTO_USER_API_SKCIPHER=m
1862 +CONFIG_CRYPTO_USER_API_RNG=m
1863 +CONFIG_CRYPTO_USER_API_AEAD=m
1864 +CONFIG_CRYPTO_CHACHA20_NEON=m
1865 +CONFIG_CRYPTO_GHASH_ARM64_CE=y
1866 +CONFIG_CRYPTO_SHA1_ARM64_CE=y
1867 +CONFIG_CRYPTO_SHA2_ARM64_CE=y
1868 +CONFIG_CRYPTO_SHA512_ARM64_CE=m
1869 +CONFIG_CRYPTO_SHA3_ARM64=m
1870 +CONFIG_CRYPTO_SM3_ARM64_CE=m
1871 +CONFIG_CRYPTO_POLYVAL_ARM64_CE=m
1872 +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
1873 +CONFIG_CRYPTO_AES_ARM64_BS=m
1874 +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
1875 +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
1876 +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=m
1877 +CONFIG_CRYPTO_DEV_FSL_CAAM=m
1878 +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m
1879 +CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m
1880 +CONFIG_CRYPTO_DEV_CCREE=m
1881 +CONFIG_CRYPTO_DEV_HISI_SEC2=m
1882 +CONFIG_CRYPTO_DEV_HISI_ZIP=m
1883 +CONFIG_CRYPTO_DEV_HISI_HPRE=m
1884 +CONFIG_CRYPTO_DEV_HISI_TRNG=m
1885 +CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
1886 +CONFIG_INDIRECT_PIO=y
1887 +CONFIG_CRC_CCITT=m
1888 +CONFIG_CRC8=y
1889 +CONFIG_CMA_SIZE_MBYTES=32
1890 +CONFIG_PRINTK_TIME=y
1891 +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
1892 +CONFIG_DEBUG_INFO_REDUCED=y
1893 +CONFIG_MAGIC_SYSRQ=y
1894 +CONFIG_DEBUG_FS=y
1895 +# CONFIG_SCHED_DEBUG is not set
1896 +# CONFIG_DEBUG_PREEMPT is not set
1897 +# CONFIG_FTRACE is not set
1898 +CONFIG_CORESIGHT=y
1899 +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
1900 +CONFIG_CORESIGHT_CATU=m
1901 +CONFIG_CORESIGHT_SINK_TPIU=m
1902 +CONFIG_CORESIGHT_SINK_ETBV10=m
1903 +CONFIG_CORESIGHT_SOURCE_ETM4X=y
1904 +CONFIG_CORESIGHT_STM=m
1905 +CONFIG_CORESIGHT_CPU_DEBUG=m
1906 +CONFIG_CORESIGHT_CTI=m
1907 +CONFIG_MEMTEST=y
2f7a23 1908 diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
G 1909 index 3946eb595..15278c13c 100644
1910 --- a/drivers/iio/adc/Kconfig
1911 +++ b/drivers/iio/adc/Kconfig
1912 @@ -1164,6 +1164,18 @@ config TI_ADC161S626
1913        This driver can also be built as a module. If so, the module will be
1914        called ti-adc161s626.
1915  
1916 +config MS1112
1917 +    tristate "Ruimeng Technology MS1112 ADC"
1918 +    depends on I2C
1919 +    select IIO_BUFFER
1920 +    select IIO_TRIGGERED_BUFFER
1921 +    help
1922 +      If you say yes here you get support for Ruimeng Technology ADS1015
1923 +      ADC chip.
1924 +
1925 +      This driver can also be built as a module. If so, the module will be
1926 +      called ms1112.
1927 +
1928  config TI_ADS1015
1929      tristate "Texas Instruments ADS1015 ADC"
1930      depends on I2C
1931 diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
1932 index 83233c38c..f403164cf 100644
1933 --- a/drivers/iio/adc/Makefile
1934 +++ b/drivers/iio/adc/Makefile
1935 @@ -104,6 +104,7 @@ obj-$(CONFIG_TI_ADC12138) += ti-adc12138.o
1936  obj-$(CONFIG_TI_ADC108S102) += ti-adc108s102.o
1937  obj-$(CONFIG_TI_ADC128S052) += ti-adc128s052.o
1938  obj-$(CONFIG_TI_ADC161S626) += ti-adc161s626.o
1939 +obj-$(CONFIG_MS1112) += ms1112.o
1940  obj-$(CONFIG_TI_ADS1015) += ti-ads1015.o
1941  obj-$(CONFIG_TI_ADS7950) += ti-ads7950.o
1942  obj-$(CONFIG_TI_ADS8344) += ti-ads8344.o
1943 diff --git a/drivers/iio/adc/ms1112.c b/drivers/iio/adc/ms1112.c
1944 new file mode 100644
1945 index 000000000..cf8ea5c66
1946 --- /dev/null
1947 +++ b/drivers/iio/adc/ms1112.c
1948 @@ -0,0 +1,569 @@
1949 +// SPDX-License-Identifier: GPL-2.0-only
1950 +/*
1951 + * MS1112 - Ruimeng Technology Analog-to-Digital Converter
1952 + *
1953 + * Copyright (c) 2024, LingYun IoT System Studio.
1954 + *
1955 + * IIO driver for MS1112 ADC 7-bit I2C slave address: 0x4A
1956 + */
1957 +
1958 +#include <linux/init.h>
1959 +#include <linux/module.h>
1960 +#include <linux/errno.h>
1961 +#include <linux/gpio.h>
1962 +#include <linux/cdev.h>
1963 +#include <linux/device.h>
1964 +#include <linux/of_gpio.h>
1965 +#include <linux/semaphore.h>
1966 +#include <linux/timer.h>
1967 +#include <linux/i2c.h>
1968 +#include <asm/uaccess.h>
1969 +#include <asm/io.h>
1970 +#include <linux/iio/iio.h>
1971 +#include <linux/iio/driver.h>
1972 +
1973 +#define MS1112_DRV_NAME                "ms1112"
1974 +
1975 +#define MS1112_CONV_REG                0x00
1976 +#define MS1112_CFG_REG                0x01
1977 +#define MS1112_DEFAULT_CONFIG        0xFC
1978 +
1979 +#define MS1112_CHANNELS                4
1980 +#define MS1112_CFG_DR_SHIFT            2
1981 +#define MS1112_CFG_MOD_SHIFT        4
1982 +#define MS1112_CFG_PGA_SHIFT        0
1983 +#define MS1112_CFG_MUX_SHIFT        5
1984 +
1985 +#define MS1112_CFG_DR_MASK            GENMASK(3, 2)
1986 +#define MS1112_CFG_MOD_MASK            BIT(4)
1987 +#define MS1112_CFG_PGA_MASK            GENMASK(1, 0)
1988 +#define MS1112_CFG_MUX_MASK            GENMASK(6, 5)
1989 +
1990 +#define MS1112_DEFAULT_PGA            0
1991 +#define MS1112_DEFAULT_DATA_RATE    3
1992 +#define MS1112_DEFAULT_CHAN            2
1993 +#define MS1112_DEFAULT_MODE            1
1994 +
1995 +#define MS1112_CONTINUOUS            0
1996 +#define MS1112_SINGLESHOT            1
1997 +
1998 +struct ms1112_chip_data {
1999 +    struct iio_chan_spec const    *channels;
2000 +    int                            num_channels;
2001 +    const struct iio_info        *info;
2002 +    const int                    *data_rate;
2003 +    const int                    data_rate_len;
2004 +    const int                    *scale;
2005 +    const int                    scale_len;
2006 +    bool                        has_comparator;
2007 +};
2008 +
2009 +enum ms1112_channels {
2010 +    MS1112_AIN0_AIN1 = 0,
2011 +    MS1112_AIN2,
2012 +    MS1112_AIN0,
2013 +    MS1112_AIN1,
2014 +    MS1112_TIMESTAMP,
2015 +};
2016 +
2017 +static const int ms1112_data_rate[] = {
2018 +    240,60,30,15
2019 +};
2020 +
2021 +static const int ms1112_fullscale_range[] = {
2022 +    2048
2023 +};
2024 +
2025 +static const int ms1112_scale[] = { /* 12bit ADC */
2026 +    2048,11,
2027 +    2048,13,
2028 +    2048,14,
2029 +    2048,15
2030 +};
2031 +
2032 +#define FIT_CHECK(_testbits, _fitbits)                \
2033 +    (                                                \
2034 +        (_fitbits) *                                \
2035 +        !!sizeof(struct {                            \
2036 +        static_assert((_testbits) <= (_fitbits));    \
2037 +        int pad;                                    \
2038 +        })                                            \
2039 +    )
2040 +
2041 +#define MS1112_V_CHAN(_chan, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \
2042 +    .type = IIO_VOLTAGE,                \
2043 +    .indexed = 1,                        \
2044 +    .address = _addr,                    \
2045 +    .channel = _chan,                    \
2046 +    .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |    \
2047 +    BIT(IIO_CHAN_INFO_SCALE) |                        \
2048 +    BIT(IIO_CHAN_INFO_SAMP_FREQ),                    \
2049 +    .info_mask_shared_by_all_available =            \
2050 +    BIT(IIO_CHAN_INFO_SCALE) |                        \
2051 +    BIT(IIO_CHAN_INFO_SAMP_FREQ),                    \
2052 +    .scan_index = _addr,                            \
2053 +    .scan_type = {                                    \
2054 +        .sign = 's',                                \
2055 +        .realbits = (_realbits),                    \
2056 +        .storagebits = FIT_CHECK((_realbits) + (_shift), 16),    \
2057 +        .shift = (_shift),                            \
2058 +        .endianness = IIO_CPU,                        \
2059 +    },                                                \
2060 +    .event_spec = (_event_spec),                    \
2061 +    .num_event_specs = (_num_event_specs),            \
2062 +    .datasheet_name = "AIN"#_chan,                    \
2063 +}
2064 +
2065 +#define MS1112_V_DIFF_CHAN(_chan, _chan2, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \
2066 +    .type = IIO_VOLTAGE,                            \
2067 +    .differential = 1,                                \
2068 +    .indexed = 1,                                    \
2069 +    .address = _addr,                                \
2070 +    .channel = _chan,                                \
2071 +    .channel2 = _chan2,                                \
2072 +    .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |    \
2073 +    BIT(IIO_CHAN_INFO_SCALE) |                        \
2074 +    BIT(IIO_CHAN_INFO_SAMP_FREQ),                    \
2075 +    .info_mask_shared_by_all_available =            \
2076 +    BIT(IIO_CHAN_INFO_SCALE) |                        \
2077 +    BIT(IIO_CHAN_INFO_SAMP_FREQ),                    \
2078 +    .scan_index = _addr,                            \
2079 +    .scan_type = {                                    \
2080 +        .sign = 's',                                \
2081 +        .realbits = (_realbits),                    \
2082 +        .storagebits = FIT_CHECK((_realbits) + (_shift), 16),    \
2083 +        .shift = (_shift),                            \
2084 +        .endianness = IIO_CPU,                        \
2085 +    },                                                \
2086 +    .event_spec = (_event_spec),                    \
2087 +    .num_event_specs = (_num_event_specs),            \
2088 +    .datasheet_name = "AIN"#_chan"-AIN"#_chan2,        \
2089 +}
2090 +
2091 +struct ms1112_channel_data {
2092 +    bool enabled;
2093 +    unsigned int pga;
2094 +    unsigned int data_rate;
2095 +    unsigned int mode;
2096 +};
2097 +
2098 +struct ms1112_thresh_data {
2099 +    int high_thresh;
2100 +    int low_thresh;
2101 +};
2102 +
2103 +struct ms1112_data {
2104 +    struct ms1112_channel_data channel_data[MS1112_CHANNELS];
2105 +    struct ms1112_thresh_data thresh_data[MS1112_CHANNELS];
2106 +    const struct ms1112_chip_data *chip;
2107 +    struct mutex lock;
2108 +    void *private_data;
2109 +    struct i2c_client *client;
2110 +};
2111 +
2112 +/* MS1112 don't use the register address */
2113 +static int ms1112_read_regs(struct ms1112_data *dev, uint8_t reg, void *buf, uint8_t size)
2114 +{
2115 +    int                    ret = 0;
2116 +    struct i2c_msg        msg[1];
2117 +    struct i2c_client    *client = dev->client;
2118 +
2119 +    msg[0].addr  = client->addr;
2120 +    msg[0].flags = I2C_M_RD;
2121 +    msg[0].buf     = buf;
2122 +    msg[0].len     = size;
2123 +
2124 +    ret = i2c_transfer(client->adapter, msg, 1);
2125 +    if(ret != 1) {
2126 +        dev_err(&dev->client->dev, "%s() i2c_transfer error, ret=%d\n", __func__, ret);
2127 +        ret = -EREMOTEIO;
2128 +    }
2129 +
2130 +    return ret;
2131 +}
2132 +
2133 +/* MS1112 don't use the register address */
2134 +static s32 ms1112_write_regs(struct ms1112_data *dev, uint8_t reg, uint8_t *data, uint8_t bytes)
2135 +{
2136 +    int                    ret = 0;
2137 +    struct i2c_msg        msg;
2138 +    struct i2c_client    *client = dev->client;
2139 +
2140 +    msg.addr  = client->addr;
2141 +    msg.flags = 0;
2142 +    msg.buf   = data;
2143 +    msg.len   = bytes;
2144 +
2145 +    ret = i2c_transfer(client->adapter, &msg, 1);
2146 +    if(ret != 1) {
2147 +        dev_err(&dev->client->dev, "%s() i2c_transfer error, ret=%d\n", __func__, ret);
2148 +        ret = -EREMOTEIO;
2149 +    }
2150 +
2151 +    return ret;
2152 +}
2153 +
2154 +static int ms1112_readdata(struct ms1112_data *dev,unsigned int *val)
2155 +{
2156 +    unsigned char    buf[3];
2157 +    unsigned char    rx_data[3];
2158 +    int                rv = 0;
2159 +
2160 +    rv = ms1112_read_regs(dev, MS1112_CONV_REG, rx_data, 3);
2161 +    if(rv<0) {
2162 +        return rv;
2163 +    }
2164 +
2165 +    buf[0] = rx_data[0];
2166 +    buf[1] = rx_data[1];
2167 +    buf[2] = rx_data[2];
2168 +
2169 +    *val = (buf[0]<<8) | buf[1];
2170 +    return rv;
2171 +}
2172 +
2173 +static int ms1112_get_adc_result(struct ms1112_data *data, int chan, int *val)
2174 +{
2175 +    int            ret = 0;
2176 +    int            pga, dr , mode;
2177 +    uint8_t        mask, cfg;
2178 +
2179 +    if (chan < 0 || chan >= MS1112_CHANNELS)
2180 +        return -EINVAL;
2181 +
2182 +    mode = data->channel_data[chan].mode;
2183 +    pga = data->channel_data[chan].pga;
2184 +    dr = data->channel_data[chan].data_rate;
2185 +
2186 +    mask = MS1112_CFG_MUX_MASK | MS1112_CFG_PGA_MASK |
2187 +        MS1112_CFG_DR_MASK | MS1112_CFG_MOD_MASK | MS1112_SINGLESHOT << 7;
2188 +
2189 +    cfg = chan << MS1112_CFG_MUX_SHIFT | pga << MS1112_CFG_PGA_SHIFT |
2190 +        dr << MS1112_CFG_DR_SHIFT | mode << MS1112_CFG_MOD_SHIFT | MS1112_SINGLESHOT << 7;
2191 +
2192 +    cfg = (cfg & mask);
2193 +
2194 +    ms1112_write_regs(data, MS1112_CFG_REG, &cfg, 1);
2195 +
2196 +    ret = ms1112_readdata(data,val);
2197 +    return ret;
2198 +}
2199 +
2200 +static int ms1112_set_scale(struct ms1112_data *data, struct iio_chan_spec const *chan,
2201 +        int scale, int uscale)
2202 +{
2203 +    int i;
2204 +    int fullscale = div_s64((scale * 1000000LL + uscale) <<
2205 +            (chan->scan_type.realbits - 1), 1000000);
2206 +
2207 +    for (i = 0; i < ARRAY_SIZE(ms1112_fullscale_range); i++) {
2208 +        if (ms1112_fullscale_range[i] == fullscale) {
2209 +            data->channel_data[chan->address].pga = i;
2210 +            return 0;
2211 +        }
2212 +    }
2213 +
2214 +    return -EINVAL;
2215 +}
2216 +
2217 +static int ms1112_set_data_rate(struct ms1112_data *data, int chan, int rate)
2218 +{
2219 +    int i;
2220 +
2221 +    for (i = 0; i < data->chip->data_rate_len; i++) {
2222 +        if (data->chip->data_rate[i] == rate) {
2223 +            data->channel_data[chan].data_rate = i;
2224 +            return 0;
2225 +        }
2226 +    }
2227 +
2228 +    return -EINVAL;
2229 +}
2230 +
2231 +static int ms1112_read_avail(struct iio_dev *indio_dev,
2232 +        struct iio_chan_spec const *chan,
2233 +        const int **vals, int *type, int *length,
2234 +        long mask)
2235 +{
2236 +    struct ms1112_data *data = iio_priv(indio_dev);
2237 +
2238 +    if (chan->type != IIO_VOLTAGE)
2239 +        return -EINVAL;
2240 +
2241 +    switch (mask) {
2242 +        case IIO_CHAN_INFO_SCALE:
2243 +            *type = IIO_VAL_FRACTIONAL_LOG2;
2244 +            *vals =  data->chip->scale;
2245 +            *length = data->chip->scale_len;
2246 +            return IIO_AVAIL_LIST;
2247 +        case IIO_CHAN_INFO_SAMP_FREQ:
2248 +            *type = IIO_VAL_INT;
2249 +            *vals = data->chip->data_rate;
2250 +            *length = data->chip->data_rate_len;
2251 +            return IIO_AVAIL_LIST;
2252 +        default:
2253 +            return -EINVAL;
2254 +    }
2255 +}
2256 +
2257 +static int ms1112_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask)
2258 +{
2259 +    int ret, idx;
2260 +    struct ms1112_data *data = iio_priv(indio_dev);
2261 +
2262 +    mutex_lock(&data->lock);
2263 +    switch (mask) {
2264 +        case IIO_CHAN_INFO_RAW:
2265 +
2266 +            ret = iio_device_claim_direct_mode(indio_dev);
2267 +            if (ret)
2268 +                break;
2269 +
2270 +            ret = ms1112_get_adc_result(data, chan->address, val);
2271 +            if (ret < 0) {
2272 +                goto release_direct;
2273 +            }
2274 +
2275 +            *val = sign_extend32(*val >> chan->scan_type.shift,
2276 +                    chan->scan_type.realbits - 1);
2277 +
2278 +            ret = IIO_VAL_INT;
2279 +release_direct:
2280 +            iio_device_release_direct_mode(indio_dev);
2281 +            break;
2282 +
2283 +        case IIO_CHAN_INFO_SCALE:
2284 +            idx = data->channel_data[chan->address].pga;
2285 +            *val = ms1112_fullscale_range[idx];
2286 +            *val2 = chan->scan_type.realbits - 1;
2287 +            ret = IIO_VAL_FRACTIONAL_LOG2;
2288 +            break;
2289 +        case IIO_CHAN_INFO_SAMP_FREQ:
2290 +            idx = data->channel_data[chan->address].data_rate;
2291 +            *val = data->chip->data_rate[idx];
2292 +            ret = IIO_VAL_INT;
2293 +            break;
2294 +        default:
2295 +            ret = -EINVAL;
2296 +            break;
2297 +    }
2298 +    mutex_unlock(&data->lock);
2299 +
2300 +    return ret;
2301 +}
2302 +
2303 +static int ms1112_write_raw(struct iio_dev *indio_dev,
2304 +        struct iio_chan_spec const *chan, int val,
2305 +        int val2, long mask)
2306 +{
2307 +    struct ms1112_data *data = iio_priv(indio_dev);
2308 +    int ret;
2309 +
2310 +    mutex_lock(&data->lock);
2311 +    switch (mask) {
2312 +        case IIO_CHAN_INFO_SCALE:
2313 +            ret = ms1112_set_scale(data, chan, val, val2);
2314 +            break;
2315 +        case IIO_CHAN_INFO_SAMP_FREQ:
2316 +            ret = ms1112_set_data_rate(data, chan->address, val);
2317 +            break;
2318 +        default:
2319 +            ret = -EINVAL;
2320 +            break;
2321 +    }
2322 +    mutex_unlock(&data->lock);
2323 +
2324 +    return ret;
2325 +}
2326 +
2327 +static const struct iio_info ms1112_info = {
2328 +    .read_raw = ms1112_read_raw,
2329 +    .write_raw = ms1112_write_raw,
2330 +    .read_avail = ms1112_read_avail,
2331 +};
2332 +
2333 +
2334 +static const struct iio_chan_spec ms1112_channels[] = {
2335 +    MS1112_V_DIFF_CHAN(0, 1, MS1112_AIN0_AIN1, 16, 0, NULL, 0),
2336 +    MS1112_V_CHAN(2, MS1112_AIN2, 16, 0, NULL, 0),
2337 +    MS1112_V_CHAN(0, MS1112_AIN0, 16, 0, NULL, 0),
2338 +    MS1112_V_CHAN(1, MS1112_AIN1, 16, 0, NULL, 0),
2339 +    IIO_CHAN_SOFT_TIMESTAMP(MS1112_TIMESTAMP),
2340 +};
2341 +
2342 +static int ms1112_client_get_channels_config(struct i2c_client *client)
2343 +{
2344 +    struct iio_dev *indio_dev = i2c_get_clientdata(client);
2345 +    struct ms1112_data *data = iio_priv(indio_dev);
2346 +    struct device *dev = &client->dev;
2347 +    struct fwnode_handle *node;
2348 +    int i = -1;
2349 +
2350 +    device_for_each_child_node(dev, node) {
2351 +        u32 pval;
2352 +        unsigned int channel;
2353 +        unsigned int pga = MS1112_DEFAULT_PGA;
2354 +        unsigned int data_rate = MS1112_DEFAULT_DATA_RATE;
2355 +        unsigned int mode = MS1112_DEFAULT_MODE;
2356 +
2357 +        if (fwnode_property_read_u32(node, "reg", &pval)) {
2358 +            dev_err(dev, "invalid reg on %pfw\n", node);
2359 +            continue;
2360 +        }
2361 +
2362 +        channel = pval;
2363 +        if (channel >= MS1112_CHANNELS) {
2364 +            dev_err(dev, "invalid channel index %d on %pfw\n",
2365 +                    channel, node);
2366 +            continue;
2367 +        }
2368 +
2369 +        if (!fwnode_property_read_u32(node, "ti,gain", &pval)) {
2370 +            pga = pval;
2371 +            if (pga > 3 ) {
2372 +                dev_err(dev, "invalid gain on %pfw\n", node);
2373 +                fwnode_handle_put(node);
2374 +                return -EINVAL;
2375 +            }
2376 +        }
2377 +
2378 +        if (!fwnode_property_read_u32(node, "ti,datarate", &pval)) {
2379 +            data_rate = pval;
2380 +            if (data_rate > 3) {
2381 +                dev_err(dev, "invalid data_rate on %pfw\n", node);
2382 +                fwnode_handle_put(node);
2383 +                return -EINVAL;
2384 +            }
2385 +        }
2386 +
2387 +        if (!fwnode_property_read_u32(node, "ti,mode", &pval)) {
2388 +            mode = pval;
2389 +            if (mode > 1) {
2390 +                dev_err(dev, "invalid mode on %pfw\n", node);
2391 +                fwnode_handle_put(node);
2392 +                return -EINVAL;
2393 +            }
2394 +        }
2395 +
2396 +
2397 +        data->channel_data[channel].pga = pga;
2398 +        data->channel_data[channel].data_rate = data_rate;
2399 +        data->channel_data[channel].mode = mode;
2400 +        i++;
2401 +    }
2402 +
2403 +    return i < 0 ? -EINVAL : 0;
2404 +}
2405 +
2406 +static void ms1112_get_channels_config(struct i2c_client *client)
2407 +{
2408 +    unsigned int k;
2409 +
2410 +    struct iio_dev *indio_dev = i2c_get_clientdata(client);
2411 +    struct ms1112_data *data = iio_priv(indio_dev);
2412 +
2413 +    if (!ms1112_client_get_channels_config(client))
2414 +        return;
2415 +
2416 +    /* fallback on default configuration */
2417 +    for (k = 0; k < MS1112_CHANNELS; ++k) {
2418 +        data->channel_data[k].pga = MS1112_DEFAULT_PGA;
2419 +        data->channel_data[k].data_rate = MS1112_DEFAULT_DATA_RATE;
2420 +        data->channel_data[k].mode = MS1112_DEFAULT_MODE;
2421 +    }
2422 +}
2423 +
2424 +static int ms1112_probe(struct i2c_client *client,const struct i2c_device_id *id)
2425 +{
2426 +    struct iio_dev *indio_dev;
2427 +    const struct ms1112_chip_data *chip;
2428 +    struct ms1112_data *data;
2429 +    int ret;
2430 +    int i;
2431 +
2432 +    chip = device_get_match_data(&client->dev);
2433 +    if (!chip)
2434 +        chip = (const struct ms1112_chip_data *)id->driver_data;
2435 +    if (!chip)
2436 +        return dev_err_probe(&client->dev, -EINVAL, "Unknown chip\n");
2437 +
2438 +    indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*indio_dev));
2439 +    if (!indio_dev)
2440 +        return -ENOMEM;
2441 +
2442 +    data = iio_priv(indio_dev);
2443 +    i2c_set_clientdata(client, indio_dev);
2444 +
2445 +    mutex_init(&data->lock);
2446 +
2447 +    indio_dev->name = MS1112_DRV_NAME;
2448 +    indio_dev->info = chip->info;
2449 +    indio_dev->modes = INDIO_DIRECT_MODE;
2450 +    indio_dev->channels = chip->channels;
2451 +    indio_dev->num_channels = chip->num_channels;
2452 +    data->chip = chip;
2453 +    data->client = client;
2454 +
2455 +    for (i = 0; i < MS1112_CHANNELS; i++) {
2456 +        int realbits = indio_dev->channels[i].scan_type.realbits;
2457 +
2458 +        data->thresh_data[i].low_thresh = -1 << (realbits - 1);
2459 +        data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1;
2460 +    }
2461 +
2462 +    /* we need to keep this ABI the same as used by hwmon ADS1015 driver */
2463 +    ms1112_get_channels_config(client);
2464 +
2465 +    ret = iio_device_register(indio_dev);
2466 +    if (ret)
2467 +        dev_err(&client->dev, "Failed to register IIO device\n");
2468 +    return ret;
2469 +}
2470 +
2471 +static void ms1112_remove(struct i2c_client *client)
2472 +{
2473 +    struct iio_dev *indio_dev = i2c_get_clientdata(client);
2474 +
2475 +    iio_device_unregister(indio_dev);
2476 +
2477 +}
2478 +
2479 +static const struct ms1112_chip_data ms1112_data = {
2480 +    .channels    = ms1112_channels,
2481 +    .num_channels    = ARRAY_SIZE(ms1112_channels),
2482 +    .info        = &ms1112_info,
2483 +    .data_rate    = ms1112_data_rate,
2484 +    .data_rate_len    = ARRAY_SIZE(ms1112_data_rate),
2485 +    .scale        = ms1112_scale,
2486 +    .scale_len    = ARRAY_SIZE(ms1112_scale),
2487 +    .has_comparator = false,
2488 +};
2489 +
2490 +static const struct i2c_device_id ms1112_id[] = {
2491 +    { "ms1112", (kernel_ulong_t)&ms1112_data },
2492 +    {}
2493 +};
2494 +MODULE_DEVICE_TABLE(i2c, ms1112_id);
2495 +
2496 +static const struct of_device_id ms1112_of_match[] = {
2497 +    { .compatible = "ms,ms1112" },
2498 +    { },
2499 +};
2500 +MODULE_DEVICE_TABLE(of, ms1112_of_match);
2501 +
2502 +static struct i2c_driver ms1112_driver = {
2503 +    .driver = {
2504 +        .owner = THIS_MODULE,
2505 +        .name = "ms1112",
2506 +        .of_match_table = ms1112_of_match,
2507 +    },
2508 +    .probe = ms1112_probe,
2509 +    .remove = ms1112_remove,
2510 +    .id_table    = ms1112_id,
2511 +};
2512 +
2513 +module_i2c_driver(ms1112_driver);
2514 +
2515 +MODULE_AUTHOR("Tang Junfeng");
2516 +MODULE_DESCRIPTION("MS1112 IIO ADC Driver");
2517 +MODULE_LICENSE("GPL");