| commit | author | age | ||
| 89ed87 | 1 | diff --git a/.gitignore b/.gitignore |
| G | 2 | index 3a4d056e..1893a337 100644 |
| 3 | --- a/.gitignore | |
| 4 | +++ b/.gitignore | |
| 5 | @@ -30,6 +30,7 @@ | |
| 6 | *.order | |
| 7 | *.patch | |
| 8 | *.s | |
| 9 | +*.S | |
| 10 | *.su | |
| 11 | *.swp | |
| 12 | *.tab.[ch] | |
| 64217c | 13 | diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile |
| 89ed87 | 14 | index 8b65ac0b..5a613cbc 100644 |
| 64217c | 15 | --- a/arch/arm/dts/Makefile |
| L | 16 | +++ b/arch/arm/dts/Makefile |
| 89ed87 | 17 | @@ -942,6 +942,8 @@ dtb-$(CONFIG_MX6ULL) += \ |
| 64217c | 18 | imx6ull-14x14-ddr3-val-gpmi-weim.dtb \ |
| L | 19 | imx6ull-14x14-ddr3-val-tsc.dtb \ |
| 20 | imx6ull-14x14-evk.dtb \ | |
| 21 | + alientek-imx6ull-v20.dtb \ | |
| 89ed87 | 22 | + alientek-imx6ull-v24.dtb \ |
| 64217c | 23 | imx6ull-14x14-evk-emmc.dtb \ |
| L | 24 | imx6ull-14x14-evk-gpmi-weim.dtb \ |
| 25 | imx6ull-9x9-evk.dtb \ | |
| 26 | diff --git a/arch/arm/dts/alientek-imx6ull-v20.dts b/arch/arm/dts/alientek-imx6ull-v20.dts | |
| 27 | new file mode 100644 | |
| 28 | index 00000000..3dee0233 | |
| 29 | --- /dev/null | |
| 30 | +++ b/arch/arm/dts/alientek-imx6ull-v20.dts | |
| 31 | @@ -0,0 +1,41 @@ | |
| 32 | +// SPDX-License-Identifier: (GPL-2.0 OR MIT) | |
| 33 | +// | |
| 34 | +// Copyright (C) 2022 LingYun IoT System Studio. | |
| 35 | + | |
| 36 | +/dts-v1/; | |
| 37 | + | |
| 38 | +#include "alientek-imx6ull.dts" | |
| 39 | + | |
| 40 | +&fec2 { | |
| 41 | + pinctrl-names = "default"; | |
| 42 | + pinctrl-0 = <&pinctrl_enet2>; | |
| 43 | + phy-mode = "rmii"; | |
| 44 | + phy-handle = <ðphy1>; | |
| 45 | + phy-supply = <®_peri_3v3>; | |
| 46 | + phy-reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; | |
| 47 | + phy-reset-duration = <100>; | |
| 48 | + phy-reset-post-delay = <100>; | |
| 49 | + status = "okay"; | |
| 50 | + | |
| 51 | + mdio { | |
| 52 | + #address-cells = <1>; | |
| 53 | + #size-cells = <0>; | |
| 54 | + | |
| 55 | + ethphy0: ethernet-phy@2 { | |
| 56 | + compatible = "ethernet-phy-id0022.1560"; | |
| 57 | + reg = <0>; | |
| 58 | + micrel,led-mode = <1>; | |
| 59 | + clocks = <&clks IMX6UL_CLK_ENET_REF>; | |
| 60 | + clock-names = "rmii-ref"; | |
| 61 | + }; | |
| 62 | + | |
| 63 | + ethphy1: ethernet-phy@1 { | |
| 64 | + compatible = "ethernet-phy-id0022.1560"; | |
| 65 | + reg = <1>; | |
| 66 | + micrel,led-mode = <1>; | |
| 67 | + clocks = <&clks IMX6UL_CLK_ENET2_REF>; | |
| 68 | + clock-names = "rmii-ref"; | |
| 69 | + }; | |
| 70 | + }; | |
| 71 | +}; | |
| 72 | + | |
| 73 | diff --git a/arch/arm/dts/alientek-imx6ull-v24.dts b/arch/arm/dts/alientek-imx6ull-v24.dts | |
| 74 | new file mode 100644 | |
| 75 | index 00000000..e78bf08d | |
| 76 | --- /dev/null | |
| 77 | +++ b/arch/arm/dts/alientek-imx6ull-v24.dts | |
| 78 | @@ -0,0 +1,47 @@ | |
| 79 | +// SPDX-License-Identifier: (GPL-2.0 OR MIT) | |
| 80 | +// | |
| 81 | +// Copyright (C) 2022 LingYun IoT System Studio. | |
| 82 | + | |
| 83 | +/dts-v1/; | |
| 84 | + | |
| 85 | +#include "alientek-imx6ull.dts" | |
| 86 | + | |
| 87 | +&fec1 { | |
| 88 | + pinctrl-names = "default"; | |
| 89 | + pinctrl-0 = <&pinctrl_enet1>; | |
| 90 | + phy-mode = "rmii"; | |
| 91 | + phy-handle = <ðphy0>; | |
| 92 | + phy-supply = <®_peri_3v3>; | |
| 93 | + status = "okay"; | |
| 94 | +}; | |
| 95 | + | |
| 96 | +&fec2 { | |
| 97 | + pinctrl-names = "default"; | |
| 98 | + pinctrl-0 = <&pinctrl_enet2>; | |
| 99 | + phy-mode = "rmii"; | |
| 100 | + phy-handle = <ðphy1>; | |
| 101 | + phy-supply = <®_peri_3v3>; | |
| 102 | + status = "okay"; | |
| 103 | + | |
| 104 | + mdio { | |
| 105 | + #address-cells = <1>; | |
| 106 | + #size-cells = <0>; | |
| 107 | + | |
| 108 | + ethphy0: ethernet-phy@2 { | |
| 109 | + compatible = "ethernet-phy-id001c.c800"; | |
| 110 | + reg = <2>; | |
| 111 | + micrel,led-mode = <1>; | |
| 112 | + clocks = <&clks IMX6UL_CLK_ENET_REF>; | |
| 113 | + clock-names = "rmii-ref"; | |
| 114 | + }; | |
| 115 | + | |
| 116 | + ethphy1: ethernet-phy@1 { | |
| 117 | + compatible = "ethernet-phy-id001c.c800"; | |
| 118 | + reg = <1>; | |
| 119 | + micrel,led-mode = <1>; | |
| 120 | + clocks = <&clks IMX6UL_CLK_ENET2_REF>; | |
| 121 | + clock-names = "rmii-ref"; | |
| 122 | + }; | |
| 123 | + }; | |
| 124 | +}; | |
| 125 | + | |
| 126 | diff --git a/arch/arm/dts/alientek-imx6ull.dts b/arch/arm/dts/alientek-imx6ull.dts | |
| 127 | new file mode 100644 | |
| 89ed87 | 128 | index 00000000..f63335db |
| 64217c | 129 | --- /dev/null |
| L | 130 | +++ b/arch/arm/dts/alientek-imx6ull.dts |
| 89ed87 | 131 | @@ -0,0 +1,259 @@ |
| 64217c | 132 | +// SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| L | 133 | +// |
| 134 | +// Copyright (C) 2022 LingYun IoT System Studio. | |
| 135 | + | |
| 136 | +/dts-v1/; | |
| 137 | + | |
| 138 | +#include "imx6ull.dtsi" | |
| 139 | + | |
| 140 | +/{ | |
| 141 | + model = "Freescale i.MX6 ULL 14x14 EVK Board"; | |
| 142 | + compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; | |
| 143 | + | |
| 144 | + chosen { | |
| 145 | + stdout-path = &uart1; | |
| 146 | + }; | |
| 147 | + | |
| 148 | + memory@80000000 { | |
| 149 | + device_type = "memory"; | |
| 150 | + reg = <0x80000000 0x20000000>; | |
| 151 | + }; | |
| 152 | + | |
| 153 | + reserved-memory { | |
| 154 | + #address-cells = <1>; | |
| 155 | + #size-cells = <1>; | |
| 156 | + ranges; | |
| 157 | + | |
| 158 | + linux,cma { | |
| 159 | + compatible = "shared-dma-pool"; | |
| 160 | + reusable; | |
| 161 | + size = <0xa000000>; | |
| 162 | + linux,cma-default; | |
| 163 | + }; | |
| 164 | + }; | |
| 165 | + | |
| 166 | + reg_sd1_vmmc: regulator-sd1-vmmc { | |
| 167 | + compatible = "regulator-fixed"; | |
| 168 | + regulator-name = "VSD_3V3"; | |
| 169 | + regulator-min-microvolt = <3300000>; | |
| 170 | + regulator-max-microvolt = <3300000>; | |
| 171 | + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; | |
| 172 | + off-on-delay-us = <20000>; | |
| 173 | + enable-active-high; | |
| 174 | + }; | |
| 175 | + | |
| 176 | + reg_peri_3v3: regulator-peri-3v3 { | |
| 177 | + compatible = "regulator-fixed"; | |
| 178 | + pinctrl-names = "default"; | |
| 179 | + pinctrl-0 = <&pinctrl_peri_3v3>; | |
| 180 | + regulator-name = "VPERI_3V3"; | |
| 181 | + regulator-min-microvolt = <3300000>; | |
| 182 | + regulator-max-microvolt = <3300000>; | |
| 183 | + gpio = <&gpio5 2 GPIO_ACTIVE_LOW>; | |
| 184 | + regulator-always-on; | |
| 185 | + }; | |
| 186 | + | |
| 187 | + leds { | |
| 188 | + compatible = "gpio-leds"; | |
| 189 | + status = "okay"; | |
| 190 | + led0 { | |
| 191 | + label = "red"; | |
| 192 | + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; | |
| 193 | + linux,default-trigger = "heartbeat"; | |
| 194 | + default-state = "on"; | |
| 195 | + }; | |
| 196 | + }; | |
| 197 | +}; | |
| 198 | + | |
| 199 | + | |
| 200 | +&clks { | |
| 201 | + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; | |
| 202 | + assigned-clock-rates = <786432000>; | |
| 203 | +}; | |
| 204 | + | |
| 205 | +&uart1 { | |
| 206 | + pinctrl-names = "default"; | |
| 207 | + pinctrl-0 = <&pinctrl_uart1>; | |
| 208 | + status = "okay"; | |
| 209 | +}; | |
| 210 | + | |
| 89ed87 | 211 | +&usbotg1 { |
| G | 212 | + dr_mode = "otg"; |
| 213 | + srp-disable; | |
| 214 | + hnp-disable; | |
| 215 | + adp-disable; | |
| 216 | + status = "okay"; | |
| 217 | +}; | |
| 218 | + | |
| 219 | +&usbotg2 { | |
| 220 | + dr_mode = "host"; | |
| 221 | + disable-over-current; | |
| 222 | + status = "okay"; | |
| 223 | +}; | |
| 224 | + | |
| 225 | +&usbphy1 { | |
| 226 | + tx-d-cal = <0x5>; | |
| 227 | +}; | |
| 228 | + | |
| 229 | +&usbphy2 { | |
| 230 | + tx-d-cal = <0x5>; | |
| 231 | +}; | |
| 232 | + | |
| 64217c | 233 | +&usdhc1 { |
| L | 234 | + pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| 235 | + pinctrl-0 = <&pinctrl_usdhc1>; | |
| 236 | + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; | |
| 237 | + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; | |
| 238 | + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; | |
| 239 | + keep-power-in-suspend; | |
| 240 | + wakeup-source; | |
| 241 | + vmmc-supply = <®_sd1_vmmc>; | |
| 242 | + status = "okay"; | |
| 243 | +}; | |
| 244 | + | |
| 245 | +&usdhc2 { | |
| 246 | + pinctrl-names = "default", "state_100mhz", "state_200mhz"; | |
| 247 | + pinctrl-0 = <&pinctrl_usdhc2_8bit>; | |
| 248 | + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; | |
| 249 | + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; | |
| 250 | + bus-width = <8>; | |
| 251 | + non-removable; | |
| 252 | + status = "okay"; | |
| 253 | +}; | |
| 254 | + | |
| 255 | +&iomuxc { | |
| 256 | + pinctrl-names = "default"; | |
| 257 | + pinctrl_enet1: enet1grp { | |
| 258 | + fsl,pins = < | |
| 259 | + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 | |
| 260 | + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 | |
| 261 | + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 | |
| 262 | + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 | |
| 263 | + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 | |
| 264 | + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 | |
| 265 | + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 | |
| 266 | + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 | |
| 267 | + >; | |
| 268 | + }; | |
| 269 | + | |
| 270 | + pinctrl_enet2: enet2grp { | |
| 271 | + fsl,pins = < | |
| 272 | + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 | |
| 273 | + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 | |
| 274 | + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 | |
| 275 | + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 | |
| 276 | + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 | |
| 277 | + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 | |
| 278 | + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 | |
| 279 | + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 | |
| 280 | + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 | |
| 281 | + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 | |
| 282 | + >; | |
| 283 | + }; | |
| 284 | + | |
| 285 | + pinctrl_peri_3v3: peri3v3grp { | |
| 286 | + fsl,pins = < | |
| 287 | + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 | |
| 288 | + >; | |
| 289 | + }; | |
| 290 | + | |
| 291 | + pinctrl_uart1: uart1grp { | |
| 292 | + fsl,pins = < | |
| 89ed87 | 293 | + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 |
| G | 294 | + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 |
| 64217c | 295 | + >; |
| L | 296 | + }; |
| 297 | + | |
| 298 | + pinctrl_usdhc1: usdhc1grp { | |
| 299 | + fsl,pins = < | |
| 300 | + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 | |
| 301 | + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 | |
| 302 | + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 | |
| 303 | + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 | |
| 304 | + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 | |
| 305 | + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 | |
| 306 | + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ | |
| 307 | + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ | |
| 308 | + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ | |
| 309 | + >; | |
| 310 | + }; | |
| 311 | + | |
| 312 | + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { | |
| 313 | + fsl,pins = < | |
| 89ed87 | 314 | + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 |
| G | 315 | + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 |
| 316 | + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 | |
| 317 | + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 | |
| 318 | + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 | |
| 319 | + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 | |
| 64217c | 320 | + >; |
| L | 321 | + }; |
| 322 | + | |
| 323 | + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { | |
| 324 | + fsl,pins = < | |
| 89ed87 | 325 | + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 |
| G | 326 | + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 |
| 327 | + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 | |
| 328 | + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 | |
| 329 | + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 | |
| 330 | + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 | |
| 64217c | 331 | + >; |
| L | 332 | + }; |
| 333 | + | |
| 334 | + pinctrl_usdhc2: usdhc2grp { | |
| 335 | + fsl,pins = < | |
| 336 | + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 | |
| 337 | + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 | |
| 89ed87 | 338 | + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 |
| G | 339 | + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 |
| 340 | + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 | |
| 341 | + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 | |
| 64217c | 342 | + >; |
| L | 343 | + }; |
| 344 | + | |
| 345 | + pinctrl_usdhc2_8bit: usdhc2grp_8bit { | |
| 346 | + fsl,pins = < | |
| 347 | + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 | |
| 348 | + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 | |
| 89ed87 | 349 | + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 |
| G | 350 | + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 |
| 351 | + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 | |
| 352 | + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 | |
| 353 | + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 | |
| 354 | + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 | |
| 355 | + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 | |
| 356 | + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 | |
| 64217c | 357 | + >; |
| L | 358 | + }; |
| 359 | + | |
| 360 | + pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { | |
| 361 | + fsl,pins = < | |
| 362 | + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 | |
| 363 | + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 | |
| 89ed87 | 364 | + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 |
| G | 365 | + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 |
| 366 | + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 | |
| 367 | + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 | |
| 368 | + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 | |
| 369 | + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 | |
| 370 | + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 | |
| 371 | + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 | |
| 64217c | 372 | + >; |
| L | 373 | + }; |
| 374 | + | |
| 375 | + pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { | |
| 376 | + fsl,pins = < | |
| 377 | + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 | |
| 378 | + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 | |
| 89ed87 | 379 | + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 |
| G | 380 | + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 |
| 381 | + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 | |
| 382 | + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 | |
| 383 | + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 | |
| 384 | + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 | |
| 385 | + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 | |
| 386 | + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 | |
| 64217c | 387 | + >; |
| L | 388 | + }; |
| 389 | +}; | |
| 390 | + | |
| 391 | diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig | |
| 392 | index a7a04350..6616b8f9 100644 | |
| 393 | --- a/arch/arm/mach-imx/mx6/Kconfig | |
| 394 | +++ b/arch/arm/mach-imx/mx6/Kconfig | |
| 395 | @@ -624,15 +624,12 @@ config TARGET_MX6ULL_9X9_EVK | |
| 396 | select OF_SYSTEM_SETUP | |
| 397 | imply CMD_DM | |
| 398 | ||
| 399 | -config TARGET_MX6ULL_14X14_EVK | |
| 400 | - bool "Support mx6ull_14x14_evk" | |
| 401 | +config TARGET_ALIENTEK_IMX6ULL | |
| 402 | + bool "Support Alientek iMX6ULL Board v20/v24" | |
| 403 | depends on MX6ULL | |
| 404 | select BOARD_LATE_INIT | |
| 405 | select DM | |
| 406 | select DM_THERMAL | |
| 407 | - select IOMUX_LPSR | |
| 408 | - select IMX_MODULE_FUSE | |
| 409 | - select OF_SYSTEM_SETUP | |
| 410 | imply CMD_DM | |
| 411 | ||
| 412 | config TARGET_MX6ULZ_SMM_M2 | |
| 413 | @@ -875,6 +872,7 @@ source "board/freescale/mx6ul_14x14_ddr3_val/Kconfig" | |
| 414 | source "board/freescale/mx6ul_14x14_lpddr2_val/Kconfig" | |
| 415 | source "board/freescale/mx6ullevk/Kconfig" | |
| 416 | source "board/freescale/mx6ull_ddr3_val/Kconfig" | |
| 417 | +source "board/freescale/alientek-imx6ull/Kconfig" | |
| 418 | source "board/bosch/acc/Kconfig" | |
| 419 | source "board/grinn/liteboard/Kconfig" | |
| 420 | source "board/phytec/pcm058/Kconfig" | |
| 421 | diff --git a/board/freescale/alientek-imx6ull/Kconfig b/board/freescale/alientek-imx6ull/Kconfig | |
| 422 | new file mode 100644 | |
| 423 | index 00000000..c0d67681 | |
| 424 | --- /dev/null | |
| 425 | +++ b/board/freescale/alientek-imx6ull/Kconfig | |
| 426 | @@ -0,0 +1,17 @@ | |
| 427 | +if TARGET_ALIENTEK_IMX6ULL | |
| 428 | + | |
| 429 | +config SYS_BOARD | |
| 430 | + default "alientek-imx6ull" | |
| 431 | + | |
| 432 | +config SYS_VENDOR | |
| 433 | + default "freescale" | |
| 434 | + | |
| 435 | +config SYS_CONFIG_NAME | |
| 436 | + default "alientek-imx6ull" | |
| 437 | + | |
| 438 | +config IMX_CONFIG | |
| 439 | + default "board/freescale/alientek-imx6ull/imximage.cfg" | |
| 440 | + | |
| 441 | +config TEXT_BASE | |
| 442 | + default 0x87800000 | |
| 443 | +endif | |
| 444 | diff --git a/board/freescale/alientek-imx6ull/MAINTAINERS b/board/freescale/alientek-imx6ull/MAINTAINERS | |
| 445 | new file mode 100644 | |
| 446 | index 00000000..1b97ad3f | |
| 447 | --- /dev/null | |
| 448 | +++ b/board/freescale/alientek-imx6ull/MAINTAINERS | |
| 449 | @@ -0,0 +1,6 @@ | |
| 450 | +MX6ULLEVK BOARD | |
| 451 | +M: Peng Fan <peng.fan@nxp.com> | |
| 452 | +S: Maintained | |
| 453 | +F: board/freescale/mx6ullevk/ | |
| 454 | +F: include/configs/mx6ullevk.h | |
| 455 | +F: configs/alientek-imx6ull-v20_defconfig | |
| 456 | diff --git a/board/freescale/alientek-imx6ull/Makefile b/board/freescale/alientek-imx6ull/Makefile | |
| 457 | new file mode 100644 | |
| 458 | index 00000000..86ce97fd | |
| 459 | --- /dev/null | |
| 460 | +++ b/board/freescale/alientek-imx6ull/Makefile | |
| 461 | @@ -0,0 +1,4 @@ | |
| 462 | +# SPDX-License-Identifier: GPL-2.0+ | |
| 463 | +# (C) Copyright 2016 Freescale Semiconductor, Inc. | |
| 464 | + | |
| 465 | +obj-y := alientek-imx6ull.o | |
| 466 | diff --git a/board/freescale/alientek-imx6ull/alientek-imx6ull.c b/board/freescale/alientek-imx6ull/alientek-imx6ull.c | |
| 467 | new file mode 100644 | |
| 468 | index 00000000..598eb7df | |
| 469 | --- /dev/null | |
| 470 | +++ b/board/freescale/alientek-imx6ull/alientek-imx6ull.c | |
| 471 | @@ -0,0 +1,365 @@ | |
| 472 | +// SPDX-License-Identifier: GPL-2.0+ | |
| 473 | +/* | |
| 474 | + * Copyright (C) 2016 Freescale Semiconductor, Inc. | |
| 475 | + * Copyright 2017 NXP | |
| 476 | + */ | |
| 477 | + | |
| 478 | +#include <init.h> | |
| 479 | +#include <asm/arch/clock.h> | |
| 480 | +#include <asm/arch/iomux.h> | |
| 481 | +#include <asm/arch/imx-regs.h> | |
| 482 | +#include <asm/arch/crm_regs.h> | |
| 483 | +#include <asm/arch/mx6-pins.h> | |
| 484 | +#include <asm/arch/sys_proto.h> | |
| 485 | +#include <asm/global_data.h> | |
| 486 | +#include <asm/gpio.h> | |
| 487 | +#include <asm/mach-imx/iomux-v3.h> | |
| 488 | +#include <asm/mach-imx/boot_mode.h> | |
| 489 | +#include <asm/mach-imx/mxc_i2c.h> | |
| 490 | +#include <asm/io.h> | |
| 491 | +#include <common.h> | |
| 492 | +#include <env.h> | |
| 493 | +#include <fsl_esdhc_imx.h> | |
| 494 | +#include <i2c.h> | |
| 495 | +#include <miiphy.h> | |
| 496 | +#include <linux/sizes.h> | |
| 497 | +#include <linux/delay.h> | |
| 498 | +#include <mmc.h> | |
| 499 | +#include <miiphy.h> | |
| 500 | +#include <power/pmic.h> | |
| 501 | +#include <power/pfuze3000_pmic.h> | |
| 502 | +#include "../common/pfuze.h" | |
| 503 | + | |
| 504 | +DECLARE_GLOBAL_DATA_PTR; | |
| 505 | + | |
| 506 | +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | |
| 507 | + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ | |
| 508 | + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ | |
| 509 | + PAD_CTL_ODE) | |
| 510 | + | |
| 511 | +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ | |
| 512 | + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) | |
| 513 | + | |
| 514 | +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) | |
| 515 | +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ | |
| 516 | + PAD_CTL_SRE_FAST) | |
| 517 | +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) | |
| 518 | + | |
| 519 | + | |
| 520 | +#ifdef CONFIG_DM_PMIC | |
| 521 | +int power_init_board(void) | |
| 522 | +{ | |
| 523 | + struct udevice *dev; | |
| 524 | + int ret, dev_id, rev_id; | |
| 525 | + unsigned int reg; | |
| 526 | + | |
| 527 | + ret = pmic_get("pfuze3000@8", &dev); | |
| 528 | + if (ret == -ENODEV) | |
| 529 | + return 0; | |
| 530 | + if (ret != 0) | |
| 531 | + return ret; | |
| 532 | + | |
| 533 | + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); | |
| 534 | + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); | |
| 535 | + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); | |
| 536 | + | |
| 537 | + /* disable Low Power Mode during standby mode */ | |
| 538 | + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); | |
| 539 | + reg |= 0x1; | |
| 540 | + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); | |
| 541 | + | |
| 542 | + /* SW1B step ramp up time from 2us to 4us/25mV */ | |
| 543 | + pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40); | |
| 544 | + | |
| 545 | + /* SW1B mode to APS/PFM */ | |
| 546 | + pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc); | |
| 547 | + | |
| 548 | + /* SW1B standby voltage set to 0.975V */ | |
| 549 | + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb); | |
| 550 | + | |
| 551 | + return 0; | |
| 552 | +} | |
| 553 | + | |
| 554 | +#ifdef CONFIG_LDO_BYPASS_CHECK | |
| 555 | +void ldo_mode_set(int ldo_bypass) | |
| 556 | +{ | |
| 557 | + unsigned int value; | |
| 558 | + u32 vddarm; | |
| 559 | + struct udevice *dev; | |
| 560 | + int ret; | |
| 561 | + | |
| 562 | + ret = pmic_get("pfuze3000@8", &dev); | |
| 563 | + if (ret == -ENODEV) { | |
| 564 | + printf("No PMIC found!\n"); | |
| 565 | + return; | |
| 566 | + } | |
| 567 | + | |
| 568 | + /* switch to ldo_bypass mode */ | |
| 569 | + if (ldo_bypass) { | |
| 570 | + prep_anatop_bypass(); | |
| 571 | + /* decrease VDDARM to 1.275V */ | |
| 572 | + value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); | |
| 573 | + value &= ~0x1f; | |
| 574 | + value |= PFUZE3000_SW1AB_SETP(12750); | |
| 575 | + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value); | |
| 576 | + | |
| 577 | + set_anatop_bypass(1); | |
| 578 | + vddarm = PFUZE3000_SW1AB_SETP(11750); | |
| 579 | + | |
| 580 | + value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); | |
| 581 | + value &= ~0x1f; | |
| 582 | + value |= vddarm; | |
| 583 | + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value); | |
| 584 | + | |
| 585 | + finish_anatop_bypass(); | |
| 586 | + | |
| 587 | + printf("switch to ldo_bypass mode!\n"); | |
| 588 | + } | |
| 589 | +} | |
| 590 | +#endif | |
| 591 | +#endif | |
| 592 | + | |
| 593 | +int dram_init(void) | |
| 594 | +{ | |
| 595 | + gd->ram_size = imx_ddr_size(); | |
| 596 | + | |
| 597 | + return 0; | |
| 598 | +} | |
| 599 | + | |
| 600 | +int board_mmc_get_env_dev(int devno) | |
| 601 | +{ | |
| 602 | + return devno; | |
| 603 | +} | |
| 604 | + | |
| 605 | +#ifdef CONFIG_FSL_QSPI | |
| 606 | + | |
| 607 | +#ifndef CONFIG_DM_SPI | |
| 608 | +#define QSPI_PAD_CTRL1 \ | |
| 609 | + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ | |
| 610 | + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) | |
| 611 | + | |
| 612 | +static iomux_v3_cfg_t const quadspi_pads[] = { | |
| 613 | + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
| 614 | + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
| 615 | + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
| 616 | + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
| 617 | + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
| 618 | + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
| 619 | +}; | |
| 620 | +#endif | |
| 621 | + | |
| 622 | +static int board_qspi_init(void) | |
| 623 | +{ | |
| 624 | +#ifndef CONFIG_DM_SPI | |
| 625 | + /* Set the iomux */ | |
| 626 | + imx_iomux_v3_setup_multiple_pads(quadspi_pads, | |
| 627 | + ARRAY_SIZE(quadspi_pads)); | |
| 628 | +#endif | |
| 629 | + /* Set the clock */ | |
| 630 | + enable_qspi_clk(0); | |
| 631 | + | |
| 632 | + return 0; | |
| 633 | +} | |
| 634 | +#endif | |
| 635 | + | |
| 636 | +#ifdef CONFIG_NAND_MXS | |
| 637 | +static iomux_v3_cfg_t const nand_pads[] = { | |
| 638 | + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 639 | + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 640 | + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 641 | + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 642 | + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 643 | + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 644 | + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 645 | + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 646 | + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 647 | + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 648 | + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 649 | + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 650 | + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 651 | + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 652 | + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 653 | + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 654 | + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 655 | +}; | |
| 656 | + | |
| 657 | +static void setup_gpmi_nand(void) | |
| 658 | +{ | |
| 659 | + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
| 660 | + | |
| 661 | + /* config gpmi nand iomux */ | |
| 662 | + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); | |
| 663 | + | |
| 664 | + setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | | |
| 665 | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | | |
| 666 | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); | |
| 667 | + | |
| 668 | + /* enable apbh clock gating */ | |
| 669 | + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); | |
| 670 | +} | |
| 671 | +#endif | |
| 672 | + | |
| 673 | +#ifdef CONFIG_FEC_MXC | |
| 674 | +static int setup_fec(void) | |
| 675 | +{ | |
| 676 | + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
| 677 | + int ret; | |
| 678 | + | |
| 679 | + /* | |
| 680 | + * Use 50M anatop loopback REF_CLK1 for ENET1, | |
| 681 | + * clear gpr1[13], set gpr1[17]. | |
| 682 | + */ | |
| 683 | + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, | |
| 684 | + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); | |
| 685 | + /* | |
| 686 | + * Use 50M anatop loopback REF_CLK2 for ENET2, | |
| 687 | + * clear gpr1[14], set gpr1[18]. | |
| 688 | + */ | |
| 689 | + if (!check_module_fused(MODULE_ENET2)) { | |
| 690 | + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, | |
| 691 | + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); | |
| 692 | + } | |
| 693 | + | |
| 694 | + ret = enable_fec_anatop_clock(0, ENET_50MHZ); | |
| 695 | + if (ret) | |
| 696 | + return ret; | |
| 697 | + | |
| 698 | + if (!check_module_fused(MODULE_ENET2)) { | |
| 699 | + ret = enable_fec_anatop_clock(1, ENET_50MHZ); | |
| 700 | + if (ret) | |
| 701 | + return ret; | |
| 702 | + } | |
| 703 | + | |
| 704 | + enable_enet_clk(1); | |
| 705 | + | |
| 706 | + return 0; | |
| 707 | +} | |
| 708 | + | |
| 709 | +int board_phy_config(struct phy_device *phydev) | |
| 710 | +{ | |
| 711 | + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); | |
| 712 | + | |
| 713 | + if (phydev->drv->config) | |
| 714 | + phydev->drv->config(phydev); | |
| 715 | + | |
| 716 | + return 0; | |
| 717 | +} | |
| 718 | +#endif | |
| 719 | + | |
| 720 | +#ifdef CONFIG_VIDEO | |
| 721 | +static iomux_v3_cfg_t const lcd_pads[] = { | |
| 722 | + /* Use GPIO for Brightness adjustment, duty cycle = period. */ | |
| 723 | + MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
| 724 | +}; | |
| 725 | + | |
| 726 | +static int setup_lcd(void) | |
| 727 | +{ | |
| 728 | + enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); | |
| 729 | + | |
| 730 | + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); | |
| 731 | + | |
| 732 | + /* Reset the LCD */ | |
| 733 | + gpio_request(IMX_GPIO_NR(5, 9), "lcd reset"); | |
| 734 | + gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); | |
| 735 | + udelay(500); | |
| 736 | + gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); | |
| 737 | + | |
| 738 | + /* Set Brightness to high */ | |
| 739 | + gpio_request(IMX_GPIO_NR(1, 8), "backlight"); | |
| 740 | + gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); | |
| 741 | + | |
| 742 | + return 0; | |
| 743 | +} | |
| 744 | +#else | |
| 745 | +static inline int setup_lcd(void) { return 0; } | |
| 746 | +#endif | |
| 747 | + | |
| 748 | +int board_early_init_f(void) | |
| 749 | +{ | |
| 750 | + return 0; | |
| 751 | +} | |
| 752 | + | |
| 753 | +int board_init(void) | |
| 754 | +{ | |
| 755 | + /* Address of boot parameters */ | |
| 756 | + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; | |
| 757 | + | |
| 758 | +#ifdef CONFIG_FEC_MXC | |
| 759 | + setup_fec(); | |
| 760 | +#endif | |
| 761 | + | |
| 762 | +#ifdef CONFIG_FSL_QSPI | |
| 763 | + board_qspi_init(); | |
| 764 | +#endif | |
| 765 | + | |
| 766 | +#ifdef CONFIG_NAND_MXS | |
| 767 | + setup_gpmi_nand(); | |
| 768 | +#endif | |
| 769 | + | |
| 770 | + return 0; | |
| 771 | +} | |
| 772 | + | |
| 773 | +#ifdef CONFIG_CMD_BMODE | |
| 774 | +static const struct boot_mode board_boot_modes[] = { | |
| 775 | + /* 4 bit bus width */ | |
| 776 | + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, | |
| 777 | + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, | |
| 778 | + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, | |
| 779 | + {NULL, 0}, | |
| 780 | +}; | |
| 781 | +#endif | |
| 782 | + | |
| 783 | +int board_late_init(void) | |
| 784 | +{ | |
| 785 | +#ifdef CONFIG_CMD_BMODE | |
| 786 | + add_board_boot_modes(board_boot_modes); | |
| 787 | +#endif | |
| 788 | + | |
| 789 | + env_set("tee", "no"); | |
| 790 | +#ifdef CONFIG_IMX_OPTEE | |
| 791 | + env_set("tee", "yes"); | |
| 792 | +#endif | |
| 793 | + | |
| 794 | +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG | |
| 795 | + env_set("board_name", "EVK"); | |
| 796 | + | |
| 797 | + if (is_mx6ull_9x9_evk()) | |
| 798 | + env_set("board_rev", "9X9"); | |
| 799 | + else | |
| 800 | + env_set("board_rev", "14X14"); | |
| 801 | + | |
| 802 | + if (is_cpu_type(MXC_CPU_MX6ULZ)) { | |
| 803 | + env_set("board_name", "ULZ-EVK"); | |
| 804 | + env_set("usb_net_cmd", "usb start"); | |
| 805 | + } | |
| 806 | +#endif | |
| 807 | + | |
| 808 | + setup_lcd(); | |
| 809 | + | |
| 810 | +#ifdef CONFIG_ENV_IS_IN_MMC | |
| 811 | + board_late_mmc_env_init(); | |
| 812 | +#endif | |
| 813 | + | |
| 814 | + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); | |
| 815 | + | |
| 816 | + return 0; | |
| 817 | +} | |
| 818 | + | |
| 819 | +int checkboard(void) | |
| 820 | +{ | |
| 821 | + if (is_mx6ull_9x9_evk()) | |
| 822 | + puts("Board: MX6ULL 9x9 EVK\n"); | |
| 823 | + else if (is_cpu_type(MXC_CPU_MX6ULZ)) | |
| 824 | + puts("Board: MX6ULZ 14x14 EVK\n"); | |
| 825 | + else | |
| 826 | + puts("Board: MX6ULL 14x14 EVK\n"); | |
| 827 | + | |
| 828 | + return 0; | |
| 829 | +} | |
| 830 | + | |
| 831 | +void board_quiesce_devices(void) | |
| 832 | +{ | |
| 833 | +#if defined(CONFIG_VIDEO_MXS) | |
| 834 | + enable_lcdif_clock(LCDIF1_BASE_ADDR, 0); | |
| 835 | +#endif | |
| 836 | +} | |
| 837 | diff --git a/board/freescale/alientek-imx6ull/imximage.cfg b/board/freescale/alientek-imx6ull/imximage.cfg | |
| 838 | new file mode 100644 | |
| 839 | index 00000000..451ff602 | |
| 840 | --- /dev/null | |
| 841 | +++ b/board/freescale/alientek-imx6ull/imximage.cfg | |
| 842 | @@ -0,0 +1,120 @@ | |
| 843 | +/* SPDX-License-Identifier: GPL-2.0+ */ | |
| 844 | +/* | |
| 845 | + * Copyright (C) 2016 Freescale Semiconductor, Inc. | |
| 846 | + * Copyright 2017 NXP | |
| 847 | + * | |
| 848 | + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure | |
| 849 | + * and create imximage boot image | |
| 850 | + * | |
| 851 | + * The syntax is taken as close as possible with the kwbimage | |
| 852 | + */ | |
| 853 | + | |
| 854 | +#include <config.h> | |
| 855 | + | |
| 856 | +/* image version */ | |
| 857 | + | |
| 858 | +IMAGE_VERSION 2 | |
| 859 | + | |
| 860 | +/* | |
| 861 | + * Boot Device : one of | |
| 862 | + * spi/sd/nand/onenand, qspi/nor | |
| 863 | + */ | |
| 864 | + | |
| 865 | +#ifdef CONFIG_QSPI_BOOT | |
| 866 | +BOOT_FROM qspi | |
| 867 | +#elif defined(CONFIG_NOR_BOOT) | |
| 868 | +BOOT_FROM nor | |
| 869 | +#else | |
| 870 | +BOOT_FROM sd | |
| 871 | +#endif | |
| 872 | + | |
| 873 | +#ifdef CONFIG_USE_IMXIMG_PLUGIN | |
| 874 | +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ | |
| 875 | +PLUGIN board/freescale/alientek-imx6ull/plugin.bin 0x00907000 | |
| 876 | +#else | |
| 877 | + | |
| 878 | +#ifdef CONFIG_IMX_HAB | |
| 879 | +CSF CONFIG_CSF_SIZE | |
| 880 | +#endif | |
| 881 | + | |
| 882 | +/* | |
| 883 | + * Device Configuration Data (DCD) | |
| 884 | + * | |
| 885 | + * Each entry must have the format: | |
| 886 | + * Addr-type Address Value | |
| 887 | + * | |
| 888 | + * where: | |
| 889 | + * Addr-type register length (1,2 or 4 bytes) | |
| 890 | + * Address absolute address of the register | |
| 891 | + * value value to be stored in the register | |
| 892 | + */ | |
| 893 | + | |
| 894 | +/* Enable all clocks */ | |
| 895 | +DATA 4 0x020c4068 0xffffffff | |
| 896 | +DATA 4 0x020c406c 0xffffffff | |
| 897 | +DATA 4 0x020c4070 0xffffffff | |
| 898 | +DATA 4 0x020c4074 0xffffffff | |
| 899 | +DATA 4 0x020c4078 0xffffffff | |
| 900 | +DATA 4 0x020c407c 0xffffffff | |
| 901 | +DATA 4 0x020c4080 0xffffffff | |
| 902 | + | |
| 903 | +#ifdef CONFIG_IMX_OPTEE | |
| 904 | +DATA 4 0x20e4024 0x00000001 | |
| 905 | +CHECK_BITS_SET 4 0x20e4024 0x1 | |
| 906 | +#endif | |
| 907 | + | |
| 908 | +DATA 4 0x020E04B4 0x000C0000 | |
| 909 | +DATA 4 0x020E04AC 0x00000000 | |
| 910 | +DATA 4 0x020E027C 0x00000030 | |
| 911 | +DATA 4 0x020E0250 0x00000030 | |
| 912 | +DATA 4 0x020E024C 0x00000030 | |
| 913 | +DATA 4 0x020E0490 0x00000030 | |
| 914 | +DATA 4 0x020E0288 0x000C0030 | |
| 915 | +DATA 4 0x020E0270 0x00000000 | |
| 916 | +DATA 4 0x020E0260 0x00000030 | |
| 917 | +DATA 4 0x020E0264 0x00000030 | |
| 918 | +DATA 4 0x020E04A0 0x00000030 | |
| 919 | +DATA 4 0x020E0494 0x00020000 | |
| 920 | +DATA 4 0x020E0280 0x00000030 | |
| 921 | +DATA 4 0x020E0284 0x00000030 | |
| 922 | +DATA 4 0x020E04B0 0x00020000 | |
| 923 | +DATA 4 0x020E0498 0x00000030 | |
| 924 | +DATA 4 0x020E04A4 0x00000030 | |
| 925 | +DATA 4 0x020E0244 0x00000030 | |
| 926 | +DATA 4 0x020E0248 0x00000030 | |
| 927 | +DATA 4 0x021B001C 0x00008000 | |
| 928 | +DATA 4 0x021B0800 0xA1390003 | |
| 929 | +DATA 4 0x021B080C 0x00000004 | |
| 930 | +DATA 4 0x021B083C 0x41640158 | |
| 931 | +DATA 4 0x021B0848 0x40403237 | |
| 932 | +DATA 4 0x021B0850 0x40403C33 | |
| 933 | +DATA 4 0x021B081C 0x33333333 | |
| 934 | +DATA 4 0x021B0820 0x33333333 | |
| 935 | +DATA 4 0x021B082C 0xf3333333 | |
| 936 | +DATA 4 0x021B0830 0xf3333333 | |
| 937 | +DATA 4 0x021B08C0 0x00944009 | |
| 938 | +DATA 4 0x021B08b8 0x00000800 | |
| 939 | +DATA 4 0x021B0004 0x0002002D | |
| 940 | +DATA 4 0x021B0008 0x1B333030 | |
| 941 | +DATA 4 0x021B000C 0x676B52F3 | |
| 942 | +DATA 4 0x021B0010 0xB66D0B63 | |
| 943 | +DATA 4 0x021B0014 0x01FF00DB | |
| 944 | +DATA 4 0x021B0018 0x00201740 | |
| 945 | +DATA 4 0x021B001C 0x00008000 | |
| 946 | +DATA 4 0x021B002C 0x000026D2 | |
| 947 | +DATA 4 0x021B0030 0x006B1023 | |
| 948 | +DATA 4 0x021B0040 0x0000004F | |
| 949 | +DATA 4 0x021B0000 0x84180000 | |
| 950 | +DATA 4 0x021B0890 0x00400000 | |
| 951 | +DATA 4 0x021B001C 0x02008032 | |
| 952 | +DATA 4 0x021B001C 0x00008033 | |
| 953 | +DATA 4 0x021B001C 0x00048031 | |
| 954 | +DATA 4 0x021B001C 0x15208030 | |
| 955 | +DATA 4 0x021B001C 0x04008040 | |
| 956 | +DATA 4 0x021B0020 0x00000800 | |
| 957 | +DATA 4 0x021B0818 0x00000227 | |
| 958 | +DATA 4 0x021B0004 0x0002552D | |
| 959 | +DATA 4 0x021B0404 0x00011006 | |
| 960 | +DATA 4 0x021B001C 0x00000000 | |
| 961 | + | |
| 962 | +#endif | |
| 963 | diff --git a/board/freescale/alientek-imx6ull/imximage_lpddr2.cfg b/board/freescale/alientek-imx6ull/imximage_lpddr2.cfg | |
| 964 | new file mode 100644 | |
| 965 | index 00000000..23d770eb | |
| 966 | --- /dev/null | |
| 967 | +++ b/board/freescale/alientek-imx6ull/imximage_lpddr2.cfg | |
| 968 | @@ -0,0 +1,125 @@ | |
| 969 | +/* | |
| 970 | + * Copyright (C) 2016 Freescale Semiconductor, Inc. | |
| 971 | + * Copyright 2017 NXP | |
| 972 | + * | |
| 973 | + * SPDX-License-Identifier: GPL-2.0+ | |
| 974 | + * | |
| 975 | + * Refer docs/README.imxmage for more details about how-to configure | |
| 976 | + * and create imximage boot image | |
| 977 | + * | |
| 978 | + * The syntax is taken as close as possible with the kwbimage | |
| 979 | + */ | |
| 980 | + | |
| 981 | +#include <config.h> | |
| 982 | + | |
| 983 | +/* image version */ | |
| 984 | + | |
| 985 | +IMAGE_VERSION 2 | |
| 986 | + | |
| 987 | +/* | |
| 988 | + * Boot Device : one of | |
| 989 | + * spi/sd/nand/onenand, qspi/nor | |
| 990 | + */ | |
| 991 | + | |
| 992 | +#ifdef CONFIG_QSPI_BOOT | |
| 993 | +BOOT_FROM qspi | |
| 994 | +#elif defined(CONFIG_NOR_BOOT) | |
| 995 | +BOOT_FROM nor | |
| 996 | +#else | |
| 997 | +BOOT_FROM sd | |
| 998 | +#endif | |
| 999 | + | |
| 1000 | +#ifdef CONFIG_USE_IMXIMG_PLUGIN | |
| 1001 | +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ | |
| 1002 | +PLUGIN board/freescale/mx6ullevk/plugin.bin 0x00907000 | |
| 1003 | +#else | |
| 1004 | + | |
| 1005 | +#ifdef CONFIG_IMX_HAB | |
| 1006 | +CSF CONFIG_CSF_SIZE | |
| 1007 | +#endif | |
| 1008 | + | |
| 1009 | +/* | |
| 1010 | + * Device Configuration Data (DCD) | |
| 1011 | + * | |
| 1012 | + * Each entry must have the format: | |
| 1013 | + * Addr-type Address Value | |
| 1014 | + * | |
| 1015 | + * where: | |
| 1016 | + * Addr-type register length (1,2 or 4 bytes) | |
| 1017 | + * Address absolute address of the register | |
| 1018 | + * value value to be stored in the register | |
| 1019 | + */ | |
| 1020 | + | |
| 1021 | +DATA 4 0x020c4068 0xffffffff | |
| 1022 | +DATA 4 0x020c406c 0xffffffff | |
| 1023 | +DATA 4 0x020c4070 0xffffffff | |
| 1024 | +DATA 4 0x020c4074 0xffffffff | |
| 1025 | +DATA 4 0x020c4078 0xffffffff | |
| 1026 | +DATA 4 0x020c407c 0xffffffff | |
| 1027 | +DATA 4 0x020c4080 0xffffffff | |
| 1028 | + | |
| 1029 | +#ifdef CONFIG_IMX_OPTEE | |
| 1030 | +DATA 4 0x20e4024 0x00000001 | |
| 1031 | +CHECK_BITS_SET 4 0x20e4024 0x1 | |
| 1032 | +#endif | |
| 1033 | + | |
| 1034 | +DATA 4 0x020E04B4 0x00080000 | |
| 1035 | +DATA 4 0x020E04AC 0x00000000 | |
| 1036 | +DATA 4 0x020E027C 0x00000030 | |
| 1037 | +DATA 4 0x020E0250 0x00000030 | |
| 1038 | +DATA 4 0x020E024C 0x00000030 | |
| 1039 | +DATA 4 0x020E0490 0x00000030 | |
| 1040 | +DATA 4 0x020E0288 0x00000030 | |
| 1041 | +DATA 4 0x020E0270 0x00000000 | |
| 1042 | +DATA 4 0x020E0260 0x00000000 | |
| 1043 | +DATA 4 0x020E0264 0x00000000 | |
| 1044 | +DATA 4 0x020E04A0 0x00000030 | |
| 1045 | +DATA 4 0x020E0494 0x00020000 | |
| 1046 | +DATA 4 0x020E0280 0x00003030 | |
| 1047 | +DATA 4 0x020E0284 0x00003030 | |
| 1048 | +DATA 4 0x020E04B0 0x00020000 | |
| 1049 | +DATA 4 0x020E0498 0x00000030 | |
| 1050 | +DATA 4 0x020E04A4 0x00000030 | |
| 1051 | +DATA 4 0x020E0244 0x00000030 | |
| 1052 | +DATA 4 0x020E0248 0x00000030 | |
| 1053 | + | |
| 1054 | +DATA 4 0x021B001C 0x00008000 | |
| 1055 | +DATA 4 0x021B085C 0x1b4700c7 | |
| 1056 | +DATA 4 0x021B0800 0xA1390003 | |
| 1057 | +DATA 4 0x021B0890 0x23400A38 | |
| 1058 | +DATA 4 0x021B08b8 0x00000800 | |
| 1059 | + | |
| 1060 | +DATA 4 0x021B081C 0x33333333 | |
| 1061 | +DATA 4 0x021B0820 0x33333333 | |
| 1062 | +DATA 4 0x021B082C 0xf3333333 | |
| 1063 | +DATA 4 0x021B0830 0xf3333333 | |
| 1064 | +DATA 4 0x021B083C 0x20000000 | |
| 1065 | +DATA 4 0x021B0848 0x40403439 | |
| 1066 | +DATA 4 0x021B0850 0x4040342D | |
| 1067 | +DATA 4 0x021B08C0 0x00921012 | |
| 1068 | +DATA 4 0x021B08b8 0x00000800 | |
| 1069 | + | |
| 1070 | +DATA 4 0x021B0004 0x00020052 | |
| 1071 | +DATA 4 0x021B0008 0x00000000 | |
| 1072 | +DATA 4 0x021B000C 0x33374133 | |
| 1073 | +DATA 4 0x021B0010 0x00100A82 | |
| 1074 | +DATA 4 0x021B0038 0x00170557 | |
| 1075 | +DATA 4 0x021B0014 0x00000093 | |
| 1076 | +DATA 4 0x021B0018 0x00201748 | |
| 1077 | +DATA 4 0x021B002C 0x0F9F26D2 | |
| 1078 | +DATA 4 0x021B0030 0x009F0010 | |
| 1079 | +DATA 4 0x021B0040 0x00000047 | |
| 1080 | +DATA 4 0x021B0000 0x83100000 | |
| 1081 | +DATA 4 0x021B001C 0x00008010 | |
| 1082 | +DATA 4 0x021B001C 0x003F8030 | |
| 1083 | +DATA 4 0x021B001C 0xFF0A8030 | |
| 1084 | +DATA 4 0x021B001C 0x82018030 | |
| 1085 | +DATA 4 0x021B001C 0x04028030 | |
| 1086 | +DATA 4 0x021B001C 0x01038030 | |
| 1087 | +DATA 4 0x021B0020 0x00001800 | |
| 1088 | +DATA 4 0x021B0818 0x00000000 | |
| 1089 | +DATA 4 0x021B0800 0xA1310003 | |
| 1090 | +DATA 4 0x021B0004 0x00025552 | |
| 1091 | +DATA 4 0x021B0404 0x00011006 | |
| 1092 | +DATA 4 0x021B001C 0x00000000 | |
| 1093 | +#endif | |
| 1094 | diff --git a/board/freescale/alientek-imx6ull/plugin.S b/board/freescale/alientek-imx6ull/plugin.S | |
| 1095 | new file mode 100644 | |
| 1096 | index 00000000..812088d1 | |
| 1097 | --- /dev/null | |
| 1098 | +++ b/board/freescale/alientek-imx6ull/plugin.S | |
| 1099 | @@ -0,0 +1,263 @@ | |
| 1100 | +/* SPDX-License-Identifier: GPL-2.0+ */ | |
| 1101 | +/* | |
| 1102 | + * Copyright (C) 2016 Freescale Semiconductor, Inc. | |
| 1103 | + * Copyright 2017 NXP | |
| 1104 | + */ | |
| 1105 | + | |
| 1106 | +#include <config.h> | |
| 1107 | + | |
| 1108 | +/* DDR script */ | |
| 1109 | +.macro imx6ull_ddr3_evk_setting | |
| 1110 | + ldr r0, =IOMUXC_BASE_ADDR | |
| 1111 | + ldr r1, =0x000C0000 | |
| 1112 | + str r1, [r0, #0x4B4] | |
| 1113 | + ldr r1, =0x00000000 | |
| 1114 | + str r1, [r0, #0x4AC] | |
| 1115 | + ldr r1, =0x00000030 | |
| 1116 | + str r1, [r0, #0x27C] | |
| 1117 | + ldr r1, =0x00000030 | |
| 1118 | + str r1, [r0, #0x250] | |
| 1119 | + str r1, [r0, #0x24C] | |
| 1120 | + str r1, [r0, #0x490] | |
| 1121 | + ldr r1, =0x000C0030 | |
| 1122 | + str r1, [r0, #0x288] | |
| 1123 | + | |
| 1124 | + ldr r1, =0x00000000 | |
| 1125 | + str r1, [r0, #0x270] | |
| 1126 | + | |
| 1127 | + ldr r1, =0x00000030 | |
| 1128 | + str r1, [r0, #0x260] | |
| 1129 | + str r1, [r0, #0x264] | |
| 1130 | + str r1, [r0, #0x4A0] | |
| 1131 | + | |
| 1132 | + ldr r1, =0x00020000 | |
| 1133 | + str r1, [r0, #0x494] | |
| 1134 | + | |
| 1135 | + ldr r1, =0x00000030 | |
| 1136 | + str r1, [r0, #0x280] | |
| 1137 | + ldr r1, =0x00000030 | |
| 1138 | + str r1, [r0, #0x284] | |
| 1139 | + | |
| 1140 | + ldr r1, =0x00020000 | |
| 1141 | + str r1, [r0, #0x4B0] | |
| 1142 | + | |
| 1143 | + ldr r1, =0x00000030 | |
| 1144 | + str r1, [r0, #0x498] | |
| 1145 | + str r1, [r0, #0x4A4] | |
| 1146 | + str r1, [r0, #0x244] | |
| 1147 | + str r1, [r0, #0x248] | |
| 1148 | + | |
| 1149 | + ldr r0, =MMDC_P0_BASE_ADDR | |
| 1150 | + ldr r1, =0x00008000 | |
| 1151 | + str r1, [r0, #0x1C] | |
| 1152 | + ldr r1, =0xA1390003 | |
| 1153 | + str r1, [r0, #0x800] | |
| 1154 | + ldr r1, =0x00000004 | |
| 1155 | + str r1, [r0, #0x80C] | |
| 1156 | + ldr r1, =0x41640158 | |
| 1157 | + str r1, [r0, #0x83C] | |
| 1158 | + ldr r1, =0x40403237 | |
| 1159 | + str r1, [r0, #0x848] | |
| 1160 | + ldr r1, =0x40403C33 | |
| 1161 | + str r1, [r0, #0x850] | |
| 1162 | + ldr r1, =0x33333333 | |
| 1163 | + str r1, [r0, #0x81C] | |
| 1164 | + str r1, [r0, #0x820] | |
| 1165 | + ldr r1, =0xF3333333 | |
| 1166 | + str r1, [r0, #0x82C] | |
| 1167 | + str r1, [r0, #0x830] | |
| 1168 | + ldr r1, =0x00944009 | |
| 1169 | + str r1, [r0, #0x8C0] | |
| 1170 | + ldr r1, =0x00000800 | |
| 1171 | + str r1, [r0, #0x8B8] | |
| 1172 | + ldr r1, =0x0002002D | |
| 1173 | + str r1, [r0, #0x004] | |
| 1174 | + ldr r1, =0x1B333030 | |
| 1175 | + str r1, [r0, #0x008] | |
| 1176 | + ldr r1, =0x676B52F3 | |
| 1177 | + str r1, [r0, #0x00C] | |
| 1178 | + ldr r1, =0xB66D0B63 | |
| 1179 | + str r1, [r0, #0x010] | |
| 1180 | + ldr r1, =0x01FF00DB | |
| 1181 | + str r1, [r0, #0x014] | |
| 1182 | + ldr r1, =0x00201740 | |
| 1183 | + str r1, [r0, #0x018] | |
| 1184 | + ldr r1, =0x00008000 | |
| 1185 | + str r1, [r0, #0x01C] | |
| 1186 | + ldr r1, =0x000026D2 | |
| 1187 | + str r1, [r0, #0x02C] | |
| 1188 | + ldr r1, =0x006B1023 | |
| 1189 | + str r1, [r0, #0x030] | |
| 1190 | + ldr r1, =0x0000004F | |
| 1191 | + str r1, [r0, #0x040] | |
| 1192 | + ldr r1, =0x84180000 | |
| 1193 | + str r1, [r0, #0x000] | |
| 1194 | + ldr r1, =0x00400000 | |
| 1195 | + str r1, [r0, #0x890] | |
| 1196 | + ldr r1, =0x02008032 | |
| 1197 | + str r1, [r0, #0x01C] | |
| 1198 | + ldr r1, =0x00008033 | |
| 1199 | + str r1, [r0, #0x01C] | |
| 1200 | + ldr r1, =0x00048031 | |
| 1201 | + str r1, [r0, #0x01C] | |
| 1202 | + ldr r1, =0x15208030 | |
| 1203 | + str r1, [r0, #0x01C] | |
| 1204 | + ldr r1, =0x04008040 | |
| 1205 | + str r1, [r0, #0x01C] | |
| 1206 | + ldr r1, =0x00000800 | |
| 1207 | + str r1, [r0, #0x020] | |
| 1208 | + ldr r1, =0x00000227 | |
| 1209 | + str r1, [r0, #0x818] | |
| 1210 | + ldr r1, =0x0002552D | |
| 1211 | + str r1, [r0, #0x004] | |
| 1212 | + ldr r1, =0x00011006 | |
| 1213 | + str r1, [r0, #0x404] | |
| 1214 | + ldr r1, =0x00000000 | |
| 1215 | + str r1, [r0, #0x01C] | |
| 1216 | +.endm | |
| 1217 | + | |
| 1218 | +.macro imx6ull_lpddr2_evk_setting | |
| 1219 | + ldr r0, =IOMUXC_BASE_ADDR | |
| 1220 | + ldr r1, =0x00080000 | |
| 1221 | + str r1, [r0, #0x4B4] | |
| 1222 | + ldr r1, =0x00000000 | |
| 1223 | + str r1, [r0, #0x4AC] | |
| 1224 | + ldr r1, =0x00000030 | |
| 1225 | + str r1, [r0, #0x27C] | |
| 1226 | + str r1, [r0, #0x250] | |
| 1227 | + str r1, [r0, #0x24C] | |
| 1228 | + str r1, [r0, #0x490] | |
| 1229 | + str r1, [r0, #0x288] | |
| 1230 | + | |
| 1231 | + ldr r1, =0x00000000 | |
| 1232 | + str r1, [r0, #0x270] | |
| 1233 | + str r1, [r0, #0x260] | |
| 1234 | + str r1, [r0, #0x264] | |
| 1235 | + | |
| 1236 | + ldr r1, =0x00000030 | |
| 1237 | + str r1, [r0, #0x4A0] | |
| 1238 | + | |
| 1239 | + ldr r1, =0x00020000 | |
| 1240 | + str r1, [r0, #0x494] | |
| 1241 | + | |
| 1242 | + ldr r1, =0x00003030 | |
| 1243 | + str r1, [r0, #0x280] | |
| 1244 | + ldr r1, =0x00003030 | |
| 1245 | + str r1, [r0, #0x284] | |
| 1246 | + | |
| 1247 | + ldr r1, =0x00020000 | |
| 1248 | + str r1, [r0, #0x4B0] | |
| 1249 | + | |
| 1250 | + ldr r1, =0x00000030 | |
| 1251 | + str r1, [r0, #0x498] | |
| 1252 | + str r1, [r0, #0x4A4] | |
| 1253 | + str r1, [r0, #0x244] | |
| 1254 | + str r1, [r0, #0x248] | |
| 1255 | + | |
| 1256 | + ldr r0, =MMDC_P0_BASE_ADDR | |
| 1257 | + ldr r1, =0x00008000 | |
| 1258 | + str r1, [r0, #0x1C] | |
| 1259 | + ldr r1, =0x1b4700c7 | |
| 1260 | + str r1, [r0, #0x85c] | |
| 1261 | + ldr r1, =0xA1390003 | |
| 1262 | + str r1, [r0, #0x800] | |
| 1263 | + ldr r1, =0x23400A38 | |
| 1264 | + str r1, [r0, #0x890] | |
| 1265 | + ldr r1, =0x00000800 | |
| 1266 | + str r1, [r0, #0x8b8] | |
| 1267 | + ldr r1, =0x33333333 | |
| 1268 | + str r1, [r0, #0x81C] | |
| 1269 | + str r1, [r0, #0x820] | |
| 1270 | + ldr r1, =0xF3333333 | |
| 1271 | + str r1, [r0, #0x82C] | |
| 1272 | + str r1, [r0, #0x830] | |
| 1273 | + ldr r1, =0x20000000 | |
| 1274 | + str r1, [r0, #0x83C] | |
| 1275 | + ldr r1, =0x40403439 | |
| 1276 | + str r1, [r0, #0x848] | |
| 1277 | + ldr r1, =0x4040342D | |
| 1278 | + str r1, [r0, #0x850] | |
| 1279 | + ldr r1, =0x00921012 | |
| 1280 | + str r1, [r0, #0x8C0] | |
| 1281 | + ldr r1, =0x00000800 | |
| 1282 | + str r1, [r0, #0x8B8] | |
| 1283 | + | |
| 1284 | + ldr r1, =0x00020052 | |
| 1285 | + str r1, [r0, #0x004] | |
| 1286 | + ldr r1, =0x00000000 | |
| 1287 | + str r1, [r0, #0x008] | |
| 1288 | + ldr r1, =0x33374133 | |
| 1289 | + str r1, [r0, #0x00C] | |
| 1290 | + ldr r1, =0x00100A82 | |
| 1291 | + str r1, [r0, #0x010] | |
| 1292 | + ldr r1, =0x00170557 | |
| 1293 | + str r1, [r0, #0x038] | |
| 1294 | + ldr r1, =0x00000093 | |
| 1295 | + str r1, [r0, #0x014] | |
| 1296 | + ldr r1, =0x00201748 | |
| 1297 | + str r1, [r0, #0x018] | |
| 1298 | + ldr r1, =0x0F9F26D2 | |
| 1299 | + str r1, [r0, #0x02C] | |
| 1300 | + ldr r1, =0x009F0010 | |
| 1301 | + str r1, [r0, #0x030] | |
| 1302 | + ldr r1, =0x00000047 | |
| 1303 | + str r1, [r0, #0x040] | |
| 1304 | + ldr r1, =0x83100000 | |
| 1305 | + str r1, [r0, #0x000] | |
| 1306 | + ldr r1, =0x00008010 | |
| 1307 | + str r1, [r0, #0x01C] | |
| 1308 | + ldr r1, =0x003F8030 | |
| 1309 | + str r1, [r0, #0x01C] | |
| 1310 | + ldr r1, =0xFF0A8030 | |
| 1311 | + str r1, [r0, #0x01C] | |
| 1312 | + ldr r1, =0x82018030 | |
| 1313 | + str r1, [r0, #0x01C] | |
| 1314 | + ldr r1, =0x04028030 | |
| 1315 | + str r1, [r0, #0x01C] | |
| 1316 | + ldr r1, =0x01038030 | |
| 1317 | + str r1, [r0, #0x01C] | |
| 1318 | + ldr r1, =0x00001800 | |
| 1319 | + str r1, [r0, #0x020] | |
| 1320 | + ldr r1, =0x00000000 | |
| 1321 | + str r1, [r0, #0x818] | |
| 1322 | + ldr r1, =0xA1310003 | |
| 1323 | + str r1, [r0, #0x800] | |
| 1324 | + ldr r1, =0x00025552 | |
| 1325 | + str r1, [r0, #0x004] | |
| 1326 | + ldr r1, =0x00011006 | |
| 1327 | + str r1, [r0, #0x404] | |
| 1328 | + ldr r1, =0x00000000 | |
| 1329 | + str r1, [r0, #0x01C] | |
| 1330 | +.endm | |
| 1331 | + | |
| 1332 | +.macro imx6_clock_gating | |
| 1333 | + ldr r0, =CCM_BASE_ADDR | |
| 1334 | + ldr r1, =0xFFFFFFFF | |
| 1335 | + str r1, [r0, #0x68] | |
| 1336 | + str r1, [r0, #0x6C] | |
| 1337 | + str r1, [r0, #0x70] | |
| 1338 | + str r1, [r0, #0x74] | |
| 1339 | + str r1, [r0, #0x78] | |
| 1340 | + str r1, [r0, #0x7C] | |
| 1341 | + str r1, [r0, #0x80] | |
| 1342 | + | |
| 1343 | +#ifdef CONFIG_IMX_OPTEE | |
| 1344 | + ldr r0, =0x20e4024 | |
| 1345 | + ldr r1, =0x1 | |
| 1346 | + str r1, [r0] | |
| 1347 | +#endif | |
| 1348 | +.endm | |
| 1349 | + | |
| 1350 | +.macro imx6_qos_setting | |
| 1351 | +.endm | |
| 1352 | + | |
| 1353 | +.macro imx6_ddr_setting | |
| 1354 | +#if defined (CONFIG_TARGET_MX6ULL_9X9_EVK) | |
| 1355 | + imx6ull_lpddr2_evk_setting | |
| 1356 | +#else | |
| 1357 | + imx6ull_ddr3_evk_setting | |
| 1358 | +#endif | |
| 1359 | +.endm | |
| 1360 | + | |
| 1361 | +/* include the common plugin code here */ | |
| 1362 | +#include <asm/arch/mx6_plugin.S> | |
| 1363 | diff --git a/configs/alientek-imx6ull-v20_defconfig b/configs/alientek-imx6ull-v20_defconfig | |
| 1364 | new file mode 100644 | |
| 1365 | index 00000000..1af20da1 | |
| 1366 | --- /dev/null | |
| 1367 | +++ b/configs/alientek-imx6ull-v20_defconfig | |
| 1368 | @@ -0,0 +1,113 @@ | |
| 1369 | +CONFIG_ARM=y | |
| 1370 | +CONFIG_ARCH_MX6=y | |
| 1371 | +CONFIG_SYS_MALLOC_LEN=0x1000000 | |
| 1372 | +CONFIG_NR_DRAM_BANKS=1 | |
| 1373 | +CONFIG_SYS_MEMTEST_START=0x80000000 | |
| 1374 | +CONFIG_SYS_MEMTEST_END=0x88000000 | |
| 1375 | +CONFIG_ENV_SIZE=0x2000 | |
| 1376 | +CONFIG_ENV_OFFSET=0xE0000 | |
| 1377 | +CONFIG_MX6ULL=y | |
| 1378 | +CONFIG_TARGET_ALIENTEK_IMX6ULL=y | |
| 1379 | +# CONFIG_LDO_BYPASS_CHECK is not set | |
| 1380 | +CONFIG_SYS_I2C_MXC_I2C1=y | |
| 1381 | +CONFIG_SYS_I2C_MXC_I2C2=y | |
| 1382 | +CONFIG_DM_GPIO=y | |
| 1383 | +CONFIG_DEFAULT_DEVICE_TREE="alientek-imx6ull-v20" | |
| 1384 | +CONFIG_SUPPORT_RAW_INITRD=y | |
| 1385 | +CONFIG_USE_BOOTCOMMAND=y | |
| 1386 | +CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" | |
| 1387 | +CONFIG_ARCH_MISC_INIT=y | |
| 1388 | +CONFIG_BOOTDELAY=3 | |
| 1389 | +# CONFIG_CONSOLE_MUX is not set | |
| 1390 | +CONFIG_SYS_CONSOLE_IS_IN_ENV=y | |
| 1391 | +CONFIG_BOARD_EARLY_INIT_F=y | |
| 1392 | +CONFIG_HUSH_PARSER=y | |
| 1393 | +CONFIG_SYS_MAXARGS=32 | |
| 1394 | +CONFIG_SYS_PBSIZE=532 | |
| 1395 | +CONFIG_CMD_BOOTZ=y | |
| 1396 | +# CONFIG_CMD_IMLS is not set | |
| 1397 | +CONFIG_CMD_MEMTEST=y | |
| 1398 | +CONFIG_CMD_GPIO=y | |
| 1399 | +CONFIG_CMD_I2C=y | |
| 1400 | +CONFIG_CMD_MMC=y | |
| 1401 | +CONFIG_CMD_SF=y | |
| 1402 | +CONFIG_CMD_USB=y | |
| 1403 | +CONFIG_CMD_DHCP=y | |
| 1404 | +CONFIG_CMD_PING=y | |
| 1405 | +CONFIG_CMD_BMP=y | |
| 1406 | +CONFIG_CMD_CACHE=y | |
| 1407 | +CONFIG_CMD_RNG=y | |
| 1408 | +CONFIG_CMD_NET=y | |
| 1409 | +CONFIG_CMD_EXT2=y | |
| 1410 | +CONFIG_CMD_EXT4=y | |
| 1411 | +CONFIG_CMD_EXT4_WRITE=y | |
| 1412 | +CONFIG_CMD_FAT=y | |
| 1413 | +CONFIG_CMD_FS_GENERIC=y | |
| 1414 | +CONFIG_OF_CONTROL=y | |
| 1415 | +CONFIG_ENV_OVERWRITE=y | |
| 1416 | +CONFIG_ENV_IS_IN_MMC=y | |
| 1417 | +CONFIG_SYS_RELOC_GD_ENV_ADDR=y | |
| 1418 | +CONFIG_SYS_MMC_ENV_DEV=1 | |
| 1419 | +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | |
| 1420 | +CONFIG_USE_ETHPRIME=y | |
| 1421 | +CONFIG_ETHPRIME="eth1" | |
| 1422 | +CONFIG_BOUNCE_BUFFER=y | |
| 1423 | +CONFIG_FSL_DCP_RNG=y | |
| 1424 | +CONFIG_DM_74X164=y | |
| 1425 | +CONFIG_DM_I2C=y | |
| 1426 | +CONFIG_SYS_I2C_MXC=y | |
| 1427 | +CONFIG_FSL_USDHC=y | |
| 1428 | +CONFIG_MTD=y | |
| 1429 | +CONFIG_DM_SPI_FLASH=y | |
| 1430 | +CONFIG_SF_DEFAULT_SPEED=40000000 | |
| 1431 | +CONFIG_SPI_FLASH_STMICRO=y | |
| 1432 | +CONFIG_PHYLIB=y | |
| 1433 | +CONFIG_PHY_SMCS=y | |
| 1434 | +CONFIG_DM_ETH_PHY=y | |
| 1435 | +CONFIG_FEC_MXC=y | |
| 1436 | +CONFIG_MII=y | |
| 1437 | +CONFIG_PINCTRL=y | |
| 1438 | +CONFIG_PINCTRL_IMX6=y | |
| 1439 | +CONFIG_DM_REGULATOR=y | |
| 1440 | +CONFIG_DM_REGULATOR_FIXED=y | |
| 1441 | +CONFIG_DM_REGULATOR_GPIO=y | |
| 1442 | +CONFIG_DM_RNG=y | |
| 1443 | +CONFIG_DM_SERIAL=y | |
| 1444 | +CONFIG_MXC_UART=y | |
| 1445 | +CONFIG_SPI=y | |
| 1446 | +CONFIG_DM_SPI=y | |
| 1447 | +CONFIG_FSL_QSPI=y | |
| 1448 | +CONFIG_SOFT_SPI=y | |
| 1449 | +CONFIG_IMX_THERMAL=y | |
| 1450 | +CONFIG_USB=y | |
| 1451 | +CONFIG_USB_MAX_CONTROLLER_COUNT=2 | |
| 1452 | +CONFIG_USB_STORAGE=y | |
| 1453 | +CONFIG_CMD_USB_MASS_STORAGE=y | |
| 1454 | +CONFIG_USB_HOST_ETHER=y | |
| 1455 | +CONFIG_USB_ETHER_ASIX=y | |
| 1456 | +CONFIG_VIDEO=y | |
| 1457 | +CONFIG_VIDEO_LINK=y | |
| 1458 | +CONFIG_VIDEO_LOGO=y | |
| 1459 | +CONFIG_SYS_WHITE_ON_BLACK=y | |
| 1460 | +CONFIG_VIDEO_MXS=y | |
| 1461 | +CONFIG_SPLASH_SCREEN=y | |
| 1462 | +CONFIG_SPLASH_SCREEN_ALIGN=y | |
| 1463 | +CONFIG_BMP_16BPP=y | |
| 1464 | + | |
| 1465 | +CONFIG_USB_GADGET=y | |
| 1466 | +CONFIG_USB_GADGET_DOWNLOAD=y | |
| 1467 | +CONFIG_USB_GADGET_MANUFACTURER="FSL" | |
| 1468 | +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 | |
| 1469 | +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 | |
| 1470 | +CONFIG_CI_UDC=y | |
| 1471 | + | |
| 1472 | +CONFIG_CMD_FASTBOOT=y | |
| 1473 | +CONFIG_USB_FUNCTION_FASTBOOT=y | |
| 1474 | +CONFIG_FASTBOOT_UUU_SUPPORT=y | |
| 1475 | +CONFIG_FASTBOOT=y | |
| 1476 | +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 | |
| 1477 | +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | |
| 1478 | +CONFIG_FASTBOOT_FLASH=y | |
| 1479 | +CONFIG_EFI_PARTITION=y | |
| 1480 | +CONFIG_CMD_CRC32=y | |
| 1481 | +CONFIG_CRC32_VERIFY=y | |
| 1482 | diff --git a/configs/alientek-imx6ull-v24_defconfig b/configs/alientek-imx6ull-v24_defconfig | |
| 1483 | new file mode 100644 | |
| 1484 | index 00000000..79128a1d | |
| 1485 | --- /dev/null | |
| 1486 | +++ b/configs/alientek-imx6ull-v24_defconfig | |
| 1487 | @@ -0,0 +1,114 @@ | |
| 1488 | +CONFIG_ARM=y | |
| 1489 | +CONFIG_ARCH_MX6=y | |
| 1490 | +CONFIG_SYS_MALLOC_LEN=0x1000000 | |
| 1491 | +CONFIG_NR_DRAM_BANKS=1 | |
| 1492 | +CONFIG_SYS_MEMTEST_START=0x80000000 | |
| 1493 | +CONFIG_SYS_MEMTEST_END=0x88000000 | |
| 1494 | +CONFIG_ENV_SIZE=0x2000 | |
| 1495 | +CONFIG_ENV_OFFSET=0xE0000 | |
| 1496 | +CONFIG_MX6ULL=y | |
| 1497 | +CONFIG_TARGET_ALIENTEK_IMX6ULL=y | |
| 1498 | +# CONFIG_LDO_BYPASS_CHECK is not set | |
| 1499 | +CONFIG_SYS_I2C_MXC_I2C1=y | |
| 1500 | +CONFIG_SYS_I2C_MXC_I2C2=y | |
| 1501 | +CONFIG_DM_GPIO=y | |
| 1502 | +CONFIG_DEFAULT_DEVICE_TREE="alientek-imx6ull-v24" | |
| 1503 | +CONFIG_SUPPORT_RAW_INITRD=y | |
| 1504 | +CONFIG_USE_BOOTCOMMAND=y | |
| 1505 | +CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" | |
| 1506 | +CONFIG_ARCH_MISC_INIT=y | |
| 1507 | +CONFIG_BOOTDELAY=3 | |
| 1508 | +# CONFIG_CONSOLE_MUX is not set | |
| 1509 | +CONFIG_SYS_CONSOLE_IS_IN_ENV=y | |
| 1510 | +CONFIG_BOARD_EARLY_INIT_F=y | |
| 1511 | +CONFIG_HUSH_PARSER=y | |
| 1512 | +CONFIG_SYS_MAXARGS=32 | |
| 1513 | +CONFIG_SYS_PBSIZE=532 | |
| 1514 | +CONFIG_CMD_BOOTZ=y | |
| 1515 | +# CONFIG_CMD_IMLS is not set | |
| 1516 | +CONFIG_CMD_MEMTEST=y | |
| 1517 | +CONFIG_CMD_GPIO=y | |
| 1518 | +CONFIG_CMD_I2C=y | |
| 1519 | +CONFIG_CMD_MMC=y | |
| 1520 | +CONFIG_CMD_SF=y | |
| 1521 | +CONFIG_CMD_USB=y | |
| 1522 | +CONFIG_CMD_DHCP=y | |
| 1523 | +CONFIG_CMD_PING=y | |
| 1524 | +CONFIG_CMD_BMP=y | |
| 1525 | +CONFIG_CMD_CACHE=y | |
| 1526 | +CONFIG_CMD_RNG=y | |
| 1527 | +CONFIG_CMD_NET=y | |
| 1528 | +CONFIG_CMD_EXT2=y | |
| 1529 | +CONFIG_CMD_EXT4=y | |
| 1530 | +CONFIG_CMD_EXT4_WRITE=y | |
| 1531 | +CONFIG_CMD_FAT=y | |
| 1532 | +CONFIG_CMD_FS_GENERIC=y | |
| 1533 | +CONFIG_OF_CONTROL=y | |
| 1534 | +CONFIG_ENV_OVERWRITE=y | |
| 1535 | +CONFIG_ENV_IS_IN_MMC=y | |
| 1536 | +CONFIG_SYS_RELOC_GD_ENV_ADDR=y | |
| 1537 | +CONFIG_SYS_MMC_ENV_DEV=1 | |
| 1538 | +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y | |
| 1539 | +CONFIG_USE_ETHPRIME=y | |
| 1540 | +CONFIG_ETHPRIME="eth1" | |
| 1541 | +CONFIG_BOUNCE_BUFFER=y | |
| 1542 | +CONFIG_FSL_DCP_RNG=y | |
| 1543 | +CONFIG_DM_74X164=y | |
| 1544 | +CONFIG_DM_I2C=y | |
| 1545 | +CONFIG_SYS_I2C_MXC=y | |
| 1546 | +CONFIG_FSL_USDHC=y | |
| 1547 | +CONFIG_MTD=y | |
| 1548 | +CONFIG_DM_SPI_FLASH=y | |
| 1549 | +CONFIG_SF_DEFAULT_SPEED=40000000 | |
| 1550 | +CONFIG_SPI_FLASH_STMICRO=y | |
| 1551 | +CONFIG_PHYLIB=y | |
| 1552 | +CONFIG_PHY_MICREL=y | |
| 1553 | +CONFIG_PHY_MICREL_KSZ8XXX=y | |
| 1554 | +CONFIG_DM_ETH_PHY=y | |
| 1555 | +CONFIG_FEC_MXC=y | |
| 1556 | +CONFIG_MII=y | |
| 1557 | +CONFIG_PINCTRL=y | |
| 1558 | +CONFIG_PINCTRL_IMX6=y | |
| 1559 | +CONFIG_DM_REGULATOR=y | |
| 1560 | +CONFIG_DM_REGULATOR_FIXED=y | |
| 1561 | +CONFIG_DM_REGULATOR_GPIO=y | |
| 1562 | +CONFIG_DM_RNG=y | |
| 1563 | +CONFIG_DM_SERIAL=y | |
| 1564 | +CONFIG_MXC_UART=y | |
| 1565 | +CONFIG_SPI=y | |
| 1566 | +CONFIG_DM_SPI=y | |
| 1567 | +CONFIG_FSL_QSPI=y | |
| 1568 | +CONFIG_SOFT_SPI=y | |
| 1569 | +CONFIG_IMX_THERMAL=y | |
| 1570 | +CONFIG_USB=y | |
| 1571 | +CONFIG_USB_MAX_CONTROLLER_COUNT=2 | |
| 1572 | +CONFIG_USB_STORAGE=y | |
| 1573 | +CONFIG_CMD_USB_MASS_STORAGE=y | |
| 1574 | +CONFIG_USB_HOST_ETHER=y | |
| 1575 | +CONFIG_USB_ETHER_ASIX=y | |
| 1576 | +CONFIG_VIDEO=y | |
| 1577 | +CONFIG_VIDEO_LINK=y | |
| 1578 | +CONFIG_VIDEO_LOGO=y | |
| 1579 | +CONFIG_SYS_WHITE_ON_BLACK=y | |
| 1580 | +CONFIG_VIDEO_MXS=y | |
| 1581 | +CONFIG_SPLASH_SCREEN=y | |
| 1582 | +CONFIG_SPLASH_SCREEN_ALIGN=y | |
| 1583 | +CONFIG_BMP_16BPP=y | |
| 1584 | + | |
| 1585 | +CONFIG_USB_GADGET=y | |
| 1586 | +CONFIG_USB_GADGET_DOWNLOAD=y | |
| 1587 | +CONFIG_USB_GADGET_MANUFACTURER="FSL" | |
| 1588 | +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 | |
| 1589 | +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 | |
| 1590 | +CONFIG_CI_UDC=y | |
| 1591 | + | |
| 1592 | +CONFIG_CMD_FASTBOOT=y | |
| 1593 | +CONFIG_USB_FUNCTION_FASTBOOT=y | |
| 1594 | +CONFIG_FASTBOOT_UUU_SUPPORT=y | |
| 1595 | +CONFIG_FASTBOOT=y | |
| 1596 | +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 | |
| 1597 | +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | |
| 1598 | +CONFIG_FASTBOOT_FLASH=y | |
| 1599 | +CONFIG_EFI_PARTITION=y | |
| 1600 | +CONFIG_CMD_CRC32=y | |
| 1601 | +CONFIG_CRC32_VERIFY=y | |
| 1602 | diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c | |
| 1603 | index 50e15cd3..be7bf91c 100644 | |
| 1604 | --- a/drivers/net/phy/phy.c | |
| 1605 | +++ b/drivers/net/phy/phy.c | |
| 1606 | @@ -182,6 +182,8 @@ int genphy_config_aneg(struct phy_device *phydev) | |
| 1607 | { | |
| 1608 | int result; | |
| 1609 | ||
| 1610 | + phy_reset(phydev); | |
| 1611 | + | |
| 1612 | if (phydev->autoneg != AUTONEG_ENABLE) | |
| 1613 | return genphy_setup_forced(phydev); | |
| 1614 | ||
| 1615 | diff --git a/include/configs/alientek-imx6ull.h b/include/configs/alientek-imx6ull.h | |
| 1616 | new file mode 100644 | |
| 1617 | index 00000000..c27fef3f | |
| 1618 | --- /dev/null | |
| 1619 | +++ b/include/configs/alientek-imx6ull.h | |
| 1620 | @@ -0,0 +1,204 @@ | |
| 1621 | +/* SPDX-License-Identifier: GPL-2.0+ */ | |
| 1622 | +/* | |
| 1623 | + * Copyright (C) 2016 Freescale Semiconductor, Inc. | |
| 1624 | + * Copyright 2017 NXP | |
| 1625 | + * | |
| 1626 | + * Configuration settings for the Freescale i.MX6UL 14x14 EVK board. | |
| 1627 | + */ | |
| 1628 | +#ifndef __ALIENTEK_IMX6ULL_CONFIG_H | |
| 1629 | +#define __ALIENTEK_IMX6ULL_CONFIG_H | |
| 1630 | + | |
| 1631 | +#ifdef CONFIG_CMD_NET | |
| 1632 | +#define CONFIG_FEC_ENET_DEV 1 | |
| 1633 | +#endif | |
| 1634 | + | |
| 1635 | +#include <asm/arch/imx-regs.h> | |
| 1636 | +#include <linux/sizes.h> | |
| 1637 | +#include <linux/stringify.h> | |
| 1638 | +#include "mx6_common.h" | |
| 1639 | +#include <asm/mach-imx/gpio.h> | |
| 1640 | +#include "imx_env.h" | |
| 1641 | + | |
| 1642 | +#define is_mx6ull_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6ULL_9X9_EVK) | |
| 1643 | + | |
| 1644 | +#ifdef CONFIG_TARGET_MX6ULL_9X9_EVK | |
| 1645 | +#define BOOTARGS_CMA_SIZE "cma=96M " | |
| 1646 | +#else | |
| 1647 | +#define BOOTARGS_CMA_SIZE "" | |
| 1648 | +#endif | |
| 1649 | + | |
| 1650 | +#define CFG_MXC_UART_BASE UART1_BASE | |
| 1651 | + | |
| 1652 | +/* MMC Configs */ | |
| 1653 | +#ifdef CONFIG_FSL_USDHC | |
| 1654 | +#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR | |
| 1655 | + | |
| 1656 | +/* NAND pin conflicts with usdhc2 */ | |
| 1657 | +#ifdef CONFIG_NAND_MXS | |
| 1658 | +#define CONFIG_SYS_FSL_USDHC_NUM 1 | |
| 1659 | +#else | |
| 1660 | +#define CONFIG_SYS_FSL_USDHC_NUM 2 | |
| 1661 | +#endif | |
| 1662 | +#endif | |
| 1663 | + | |
| 1664 | +#ifdef CONFIG_NAND_BOOT | |
| 1665 | +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs)" | |
| 1666 | +#else | |
| 1667 | +#define MFG_NAND_PARTITION "" | |
| 1668 | +#endif | |
| 1669 | + | |
| 1670 | +#define CFG_MFG_ENV_SETTINGS \ | |
| 1671 | + CFG_MFG_ENV_SETTINGS_DEFAULT \ | |
| 1672 | + "initrd_addr=0x86800000\0" \ | |
| 1673 | + "initrd_high=0xffffffff\0" \ | |
| 1674 | + "emmc_dev=1\0"\ | |
| 1675 | + "emmc_ack=1\0"\ | |
| 1676 | + "sd_dev=1\0" \ | |
| 1677 | + "mtdparts=" MFG_NAND_PARTITION \ | |
| 1678 | + "\0"\ | |
| 1679 | + | |
| 1680 | +#if defined(CONFIG_NAND_BOOT) | |
| 1681 | +#define CFG_EXTRA_ENV_SETTINGS \ | |
| 1682 | + CFG_MFG_ENV_SETTINGS \ | |
| 1683 | + TEE_ENV \ | |
| 1684 | + "splashimage=0x8c000000\0" \ | |
| 1685 | + "fdt_addr=0x83000000\0" \ | |
| 1686 | + "fdt_high=0xffffffff\0" \ | |
| 1687 | + "tee_addr=0x84000000\0" \ | |
| 1688 | + "console=ttymxc0\0" \ | |
| 1689 | + "bootargs=console=ttymxc0,115200 ubi.mtd=nandrootfs " \ | |
| 1690 | + "root=ubi0:rootfs rootfstype=ubifs " \ | |
| 1691 | + BOOTARGS_CMA_SIZE \ | |
| 1692 | + MFG_NAND_PARTITION \ | |
| 1693 | + "\0" \ | |
| 1694 | + "bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\ | |
| 1695 | + "nand read ${fdt_addr} 0x5000000 0x100000;"\ | |
| 1696 | + "if test ${tee} = yes; then " \ | |
| 1697 | + "nand read ${tee_addr} 0x6000000 0x400000;"\ | |
| 1698 | + "bootm ${tee_addr} - ${fdt_addr};" \ | |
| 1699 | + "else " \ | |
| 1700 | + "bootz ${loadaddr} - ${fdt_addr};" \ | |
| 1701 | + "fi\0" | |
| 1702 | + | |
| 1703 | +#else | |
| 1704 | +#define CFG_EXTRA_ENV_SETTINGS \ | |
| 1705 | + CFG_MFG_ENV_SETTINGS \ | |
| 1706 | + TEE_ENV \ | |
| 1707 | + "script=boot.scr\0" \ | |
| 1708 | + "image=zImage\0" \ | |
| 1709 | + "console=ttymxc0\0" \ | |
| 1710 | + "fdt_high=0xffffffff\0" \ | |
| 1711 | + "initrd_high=0xffffffff\0" \ | |
| 1712 | + "fdt_file=undefined\0" \ | |
| 1713 | + "fdt_addr=0x83000000\0" \ | |
| 1714 | + "tee_addr=0x84000000\0" \ | |
| 1715 | + "tee_file=undefined\0" \ | |
| 1716 | + "boot_fdt=try\0" \ | |
| 1717 | + "ip_dyn=yes\0" \ | |
| 1718 | + "splashimage=0x8c000000\0" \ | |
| 1719 | + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ | |
| 1720 | + "mmcpart=1\0" \ | |
| 1721 | + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ | |
| 1722 | + "mmcautodetect=yes\0" \ | |
| 1723 | + "mmcargs=setenv bootargs console=${console},${baudrate} " \ | |
| 1724 | + BOOTARGS_CMA_SIZE \ | |
| 1725 | + "root=${mmcroot}\0" \ | |
| 1726 | + "loadbootscript=" \ | |
| 1727 | + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ | |
| 1728 | + "bootscript=echo Running bootscript from mmc ...; " \ | |
| 1729 | + "source\0" \ | |
| 1730 | + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ | |
| 1731 | + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ | |
| 1732 | + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ | |
| 1733 | + "mmcboot=echo Booting from mmc ...; " \ | |
| 1734 | + "run mmcargs; " \ | |
| 1735 | + "if test ${tee} = yes; then " \ | |
| 1736 | + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ | |
| 1737 | + "else " \ | |
| 1738 | + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ | |
| 1739 | + "if run loadfdt; then " \ | |
| 1740 | + "bootz ${loadaddr} - ${fdt_addr}; " \ | |
| 1741 | + "else " \ | |
| 1742 | + "if test ${boot_fdt} = try; then " \ | |
| 1743 | + "bootz; " \ | |
| 1744 | + "else " \ | |
| 1745 | + "echo WARN: Cannot load the DT; " \ | |
| 1746 | + "fi; " \ | |
| 1747 | + "fi; " \ | |
| 1748 | + "else " \ | |
| 1749 | + "bootz; " \ | |
| 1750 | + "fi; " \ | |
| 1751 | + "fi;\0" \ | |
| 1752 | + "netargs=setenv bootargs console=${console},${baudrate} " \ | |
| 1753 | + BOOTARGS_CMA_SIZE \ | |
| 1754 | + "root=/dev/nfs " \ | |
| 1755 | + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
| 1756 | + "netboot=echo Booting from net ...; " \ | |
| 1757 | + "${usb_net_cmd}; " \ | |
| 1758 | + "run netargs; " \ | |
| 1759 | + "if test ${ip_dyn} = yes; then " \ | |
| 1760 | + "setenv get_cmd dhcp; " \ | |
| 1761 | + "else " \ | |
| 1762 | + "setenv get_cmd tftp; " \ | |
| 1763 | + "fi; " \ | |
| 1764 | + "${get_cmd} ${image}; " \ | |
| 1765 | + "if test ${tee} = yes; then " \ | |
| 1766 | + "${get_cmd} ${tee_addr} ${tee_file}; " \ | |
| 1767 | + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ | |
| 1768 | + "bootm ${tee_addr} - ${fdt_addr}; " \ | |
| 1769 | + "else " \ | |
| 1770 | + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ | |
| 1771 | + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ | |
| 1772 | + "bootz ${loadaddr} - ${fdt_addr}; " \ | |
| 1773 | + "else " \ | |
| 1774 | + "if test ${boot_fdt} = try; then " \ | |
| 1775 | + "bootz; " \ | |
| 1776 | + "else " \ | |
| 1777 | + "echo WARN: Cannot load the DT; " \ | |
| 1778 | + "fi; " \ | |
| 1779 | + "fi; " \ | |
| 1780 | + "else " \ | |
| 1781 | + "bootz; " \ | |
| 1782 | + "fi; " \ | |
| 1783 | + "fi;\0" \ | |
| 1784 | + "findfdt="\ | |
| 1785 | + "if test $fdt_file = undefined; then " \ | |
| 1786 | + "if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \ | |
| 1787 | + "setenv fdt_file imx6ulz-14x14-evk.dtb; fi; " \ | |
| 1788 | + "if test $board_name = EVK && test $board_rev = 9X9; then " \ | |
| 1789 | + "setenv fdt_file imx6ull-9x9-evk.dtb; fi; " \ | |
| 1790 | + "if test $board_name = EVK && test $board_rev = 14X14; then " \ | |
| 1791 | + "setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \ | |
| 1792 | + "if test $fdt_file = undefined; then " \ | |
| 1793 | + "echo WARNING: Could not determine dtb to use; " \ | |
| 1794 | + "fi; " \ | |
| 1795 | + "fi;\0" \ | |
| 1796 | + "findtee="\ | |
| 1797 | + "if test $tee_file = undefined; then " \ | |
| 1798 | + "if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \ | |
| 1799 | + "setenv tee_file uTee-6ulzevk; fi; " \ | |
| 1800 | + "if test $board_name = EVK && test $board_rev = 9X9; then " \ | |
| 1801 | + "setenv tee_file uTee-6ullevk; fi; " \ | |
| 1802 | + "if test $board_name = EVK && test $board_rev = 14X14; then " \ | |
| 1803 | + "setenv tee_file uTee-6ullevk; fi; " \ | |
| 1804 | + "if test $tee_file = undefined; then " \ | |
| 1805 | + "echo WARNING: Could not determine tee to use; " \ | |
| 1806 | + "fi; " \ | |
| 1807 | + "fi;\0" \ | |
| 1808 | + | |
| 1809 | +#endif | |
| 1810 | + | |
| 1811 | +/* Miscellaneous configurable options */ | |
| 1812 | + | |
| 1813 | +/* Physical Memory Map */ | |
| 1814 | +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR | |
| 1815 | + | |
| 1816 | +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM | |
| 1817 | +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
| 1818 | +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
| 1819 | + | |
| 1820 | +/* environment organization */ | |
| 1821 | + | |
| 1822 | +/* NAND stuff */ | |
| 1823 | +#define CFG_SYS_NAND_BASE 0x40000000 | |
| 1824 | +#endif | |
