build-imxboard.git

UBOOT:IGKBoard-IMX8MP:Add u-boot patch file

wenxue.guo

2023-12-12 be049f3c7c552259535ac46e423d65e32b16dc3d

commit \| author \| age
be049f	1	diff --git a/.gitignore b/.gitignore
W	2	index 3a4d056e..1893a337 100644
	3	--- a/.gitignore
	4	+++ b/.gitignore
	5	@@ -30,6 +30,7 @@
	6	*.order
	7	*.patch
	8	*.s
	9	+*.S
	10	*.su
	11	*.swp
	12	*.tab.[ch]
	13	diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
	14	index 8b65ac0b..eb0435fa 100644
	15	--- a/arch/arm/dts/Makefile
	16	+++ b/arch/arm/dts/Makefile
	17	@@ -1030,6 +1030,7 @@ dtb-$(CONFIG_ARCH_IMX8ULP) += \
	18	imx8ulp-watch.dtb
	19
	20	dtb-$(CONFIG_ARCH_IMX8M) += \
	21	+ igkboard-imx8mp.dtb \
	22	imx8mm-data-modul-edm-sbc.dtb \
	23	imx8mm-ddr4-evk.dtb \
	24	imx8mm-ddr4-ab2.dtb \
	25	diff --git a/arch/arm/dts/igkboard-imx8mp-u-boot.dtsi b/arch/arm/dts/igkboard-imx8mp-u-boot.dtsi
	26	new file mode 100644
	27	index 00000000..1199f90f
	28	--- /dev/null
	29	+++ b/arch/arm/dts/igkboard-imx8mp-u-boot.dtsi
	30	@@ -0,0 +1,70 @@
	31	+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	32	+/*
	33	+ * Copy from imx8mp-venice-u-boot.dtsi
	34	+ */
	35	+
	36	+#include "imx8mp-u-boot.dtsi"
	37	+
	38	+/ {
	39	+ wdt-reboot {
	40	+ compatible = "wdt-reboot";
	41	+ wdt = <&wdog1>;
	42	+ u-boot,dm-spl;
	43	+ };
	44	+};
	45	+
	46	+&gpio1 {
	47	+ u-boot,dm-spl;
	48	+};
	49	+
	50	+&gpio2 {
	51	+ u-boot,dm-spl;
	52	+};
	53	+
	54	+&gpio3 {
	55	+ u-boot,dm-spl;
	56	+};
	57	+
	58	+&gpio4 {
	59	+ u-boot,dm-spl;
	60	+};
	61	+
	62	+&gpio5 {
	63	+ u-boot,dm-spl;
	64	+};
	65	+
	66	+&uart2 {
	67	+ u-boot,dm-spl;
	68	+};
	69	+
	70	+&pinctrl_uart2 {
	71	+ u-boot,dm-spl;
	72	+};
	73	+
	74	+&usdhc3 {
	75	+ u-boot,dm-spl;
	76	+};
	77	+
	78	+&pinctrl_usdhc3 {
	79	+ u-boot,dm-spl;
	80	+};
	81	+
	82	+&i2c1 {
	83	+ u-boot,dm-spl;
	84	+};
	85	+
	86	+&pinctrl_i2c1 {
	87	+ u-boot,dm-spl;
	88	+};
	89	+
	90	+&i2c2 {
	91	+ u-boot,dm-spl;
	92	+};
	93	+
	94	+&wdog1 {
	95	+ u-boot,dm-spl;
	96	+};
	97	+
	98	+&pinctrl_wdog {
	99	+ u-boot,dm-spl;
	100	+};
	101	diff --git a/arch/arm/dts/igkboard-imx8mp.dts b/arch/arm/dts/igkboard-imx8mp.dts
	102	new file mode 100644
	103	index 00000000..9e9a5338
	104	--- /dev/null
	105	+++ b/arch/arm/dts/igkboard-imx8mp.dts
	106	@@ -0,0 +1,489 @@
	107	+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	108	+/*
	109	+ * Copyright 2023 LingYun IoT System Studio.
	110	+ */
	111	+
	112	+/dts-v1/;
	113	+
	114	+#include <dt-bindings/usb/pd.h>
	115	+#include "imx8mp.dtsi"
	116	+
	117	+/*+------------------------+
	118	+ \| root node \|
	119	+ +------------------------+*/
	120	+/ {
	121	+ model = "LingYun IoT Gateway Kits Board based on i.MX8MP";
	122	+ compatible = "lingyun,igkboard-imx8mp", "fsl,imx8mp";
	123	+
	124	+ /* console and bootargs */
	125	+ chosen {
	126	+ bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
	127	+ stdout-path = &uart2;
	128	+ };
	129	+
	130	+ /* MT53D512M32D2DS-053 WT:D, 8GB LPDDR4 */
	131	+ memory@80000000 {
	132	+ device_type = "memory";
	133	+ reg = <0x0 0x80000000 0 0x80000000>;
	134	+ };
	135	+
	136	+ /* SD2_RESET_B for TF card */
	137	+ reg_usdhc2_vmmc: regulator-usdhc2 {
	138	+ compatible = "regulator-fixed";
	139	+ regulator-name = "VSD_3V3";
	140	+ regulator-min-microvolt = <3300000>;
	141	+ regulator-max-microvolt = <3300000>;
	142	+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
	143	+ enable-active-high;
	144	+ startup-delay-us = <100>;
	145	+ off-on-delay-us = <12000>;
	146	+ };
	147	+
	148	+ leds {
	149	+ compatible = "gpio-leds";
	150	+ pinctrl-names = "default";
	151	+ pinctrl-0 = <&pinctrl_gpio_led>;
	152	+
	153	+ sysled {
	154	+ label = "sysled";
	155	+ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
	156	+ default-state = "on";
	157	+ };
	158	+ };
	159	+};
	160	+
	161	+/*+------------------------+
	162	+ \| power key & reset \|
	163	+ +------------------------+*/
	164	+
	165	+&snvs_pwrkey {
	166	+ status = "okay";
	167	+};
	168	+
	169	+&wdog1 {
	170	+ pinctrl-names = "default";
	171	+ pinctrl-0 = <&pinctrl_wdog>;
	172	+ fsl,ext-reset-output;
	173	+ status = "okay";
	174	+};
	175	+
	176	+/*+------------------------+
	177	+ \| console usart2 \|
	178	+ +------------------------+*/
	179	+&uart2 {
	180	+ pinctrl-names = "default";
	181	+ pinctrl-0 = <&pinctrl_uart2>;
	182	+ status = "okay";
	183	+};
	184	+
	185	+/*+------------------------+
	186	+ \| 8GB eMMC on SD3 \|
	187	+ +------------------------+*/
	188	+
	189	+/* KLM8G1GETF-B041 8GB eMMC */
	190	+&usdhc3 {
	191	+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
	192	+ pinctrl-0 = <&pinctrl_usdhc3>;
	193	+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	194	+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	195	+ bus-width = <8>;
	196	+ non-removable;
	197	+ status = "okay";
	198	+};
	199	+
	200	+/*+------------------------+
	201	+ \| TF Card on SD2 \|
	202	+ +------------------------+*/
	203	+
	204	+&usdhc2 {
	205	+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
	206	+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	207	+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	208	+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	209	+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	210	+ vmmc-supply = <&reg_usdhc2_vmmc>;
	211	+ bus-width = <4>;
	212	+ no-1-8-v;
	213	+ status = "okay";
	214	+};
	215	+
	216	+/*+------------------------+
	217	+ \| Typec USB for download \|
	218	+ +------------------------+*/
	219	+
	220	+&usb3_phy0 {
	221	+ fsl,phy-tx-vref-tune = <6>;
	222	+ fsl,phy-tx-rise-tune = <0>;
	223	+ fsl,phy-tx-preemp-amp-tune = <3>;
	224	+ fsl,phy-comp-dis-tune = <7>;
	225	+ fsl,pcs-tx-deemph-3p5db = <0x21>;
	226	+ fsl,phy-pcs-tx-swing-full = <0x7f>;
	227	+ status = "okay";
	228	+};
	229	+
	230	+&usb3_0 {
	231	+ status = "okay";
	232	+};
	233	+
	234	+&usb_dwc3_0 {
	235	+ dr_mode = "peripheral";
	236	+ hnp-disable;
	237	+ srp-disable;
	238	+ adp-disable;
	239	+ status = "okay";
	240	+};
	241	+
	242	+/*+------------------------+
	243	+ \| 2xUSB Host on USB Hub \|
	244	+ +------------------------+*/
	245	+
	246	+/* Renesas USB 3.0 Hub uPD720210 */
	247	+&usb3_phy1 {
	248	+ fsl,phy-tx-preemp-amp-tune = <2>;
	249	+ status = "okay";
	250	+};
	251	+
	252	+&usb3_1 {
	253	+ status = "okay";
	254	+};
	255	+
	256	+&usb_dwc3_1 {
	257	+ dr_mode = "host";
	258	+ status = "okay";
	259	+};
	260	+
	261	+/*+------------------------+
	262	+ \| Ethernet \|
	263	+ +------------------------+*/
	264	+
	265	+&eqos {
	266	+ pinctrl-names = "default";
	267	+ pinctrl-0 = <&pinctrl_eqos>;
	268	+ phy-mode = "rgmii-id";
	269	+ phy-handle = <&ethphy0>;
	270	+ snps,reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
	271	+ snps,reset-delays-us = <100000 200000 150000>;
	272	+ status = "okay";
	273	+
	274	+ mdio {
	275	+ compatible = "snps,dwmac-mdio";
	276	+ #address-cells = <1>;
	277	+ #size-cells = <0>;
	278	+
	279	+ ethphy0: ethernet-phy@1 {
	280	+ compatible = "ethernet-phy-ieee802.3-c22";
	281	+ reg = <0>;
	282	+ eee-broken-1000t;
	283	+ };
	284	+ };
	285	+};
	286	+
	287	+&fec {
	288	+ pinctrl-names = "default";
	289	+ pinctrl-0 = <&pinctrl_fec>;
	290	+ phy-mode = "rgmii-id";
	291	+ phy-handle = <&ethphy1>;
	292	+ phy-reset-duration = <200>;
	293	+ phy-reset-post-delay = <150>;
	294	+ phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
	295	+
	296	+ fsl,magic-packet;
	297	+ status = "okay";
	298	+
	299	+ mdio {
	300	+ #address-cells = <1>;
	301	+ #size-cells = <0>;
	302	+
	303	+ ethphy1: ethernet-phy@1 {
	304	+ compatible = "ethernet-phy-ieee802.3-c22";
	305	+ reg = <0>;
	306	+ eee-broken-1000t;
	307	+ };
	308	+ };
	309	+};
	310	+
	311	+/*+------------------------+
	312	+ \| PCA9450CHN PMIC \|
	313	+ +------------------------+*/
	314	+
	315	+&i2c1 {
	316	+ clock-frequency = <100000>;
	317	+ pinctrl-names = "default";
	318	+ pinctrl-0 = <&pinctrl_i2c1>;
	319	+ status = "okay";
	320	+
	321	+ pmic: pca9450@25 {
	322	+ reg = <0x25>;
	323	+ compatible = "nxp,pca9450c", "nxp,pca9450b", "nxp,pca9450";
	324	+ /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
	325	+ pinctrl-0 = <&pinctrl_pmic>;
	326	+ gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
	327	+
	328	+ regulators {
	329	+ #address-cells = <1>;
	330	+ #size-cells = <0>;
	331	+
	332	+ pca9450,pmic-buck2-uses-i2c-dvs;
	333	+ /* Run/Standby voltage */
	334	+ pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
	335	+
	336	+ buck1_reg: regulator@0 {
	337	+ reg = <0>;
	338	+ regulator-compatible = "buck1";
	339	+ regulator-min-microvolt = <600000>;
	340	+ regulator-max-microvolt = <2187500>;
	341	+ regulator-boot-on;
	342	+ regulator-always-on;
	343	+ regulator-ramp-delay = <3125>;
	344	+ };
	345	+
	346	+ buck2_reg: regulator@1 {
	347	+ reg = <1>;
	348	+ regulator-compatible = "buck2";
	349	+ regulator-min-microvolt = <600000>;
	350	+ regulator-max-microvolt = <2187500>;
	351	+ regulator-boot-on;
	352	+ regulator-always-on;
	353	+ regulator-ramp-delay = <3125>;
	354	+ };
	355	+
	356	+ buck4_reg: regulator@3 {
	357	+ reg = <3>;
	358	+ regulator-compatible = "buck4";
	359	+ regulator-min-microvolt = <600000>;
	360	+ regulator-max-microvolt = <3400000>;
	361	+ regulator-boot-on;
	362	+ regulator-always-on;
	363	+ };
	364	+
	365	+ buck5_reg: regulator@4 {
	366	+ reg = <4>;
	367	+ regulator-compatible = "buck5";
	368	+ regulator-min-microvolt = <600000>;
	369	+ regulator-max-microvolt = <3400000>;
	370	+ regulator-boot-on;
	371	+ regulator-always-on;
	372	+ };
	373	+
	374	+ buck6_reg: regulator@5 {
	375	+ reg = <5>;
	376	+ regulator-compatible = "buck6";
	377	+ regulator-min-microvolt = <600000>;
	378	+ regulator-max-microvolt = <3400000>;
	379	+ regulator-boot-on;
	380	+ regulator-always-on;
	381	+ };
	382	+
	383	+ ldo1_reg: regulator@6 {
	384	+ reg = <6>;
	385	+ regulator-compatible = "ldo1";
	386	+ regulator-min-microvolt = <1600000>;
	387	+ regulator-max-microvolt = <3300000>;
	388	+ regulator-boot-on;
	389	+ regulator-always-on;
	390	+ };
	391	+
	392	+ ldo2_reg: regulator@7 {
	393	+ reg = <7>;
	394	+ regulator-compatible = "ldo2";
	395	+ regulator-min-microvolt = <800000>;
	396	+ regulator-max-microvolt = <1150000>;
	397	+ regulator-boot-on;
	398	+ regulator-always-on;
	399	+ };
	400	+
	401	+ ldo3_reg: regulator@8 {
	402	+ reg = <8>;
	403	+ regulator-compatible = "ldo3";
	404	+ regulator-min-microvolt = <800000>;
	405	+ regulator-max-microvolt = <3300000>;
	406	+ regulator-boot-on;
	407	+ regulator-always-on;
	408	+ };
	409	+
	410	+ ldo4_reg: regulator@9 {
	411	+ reg = <9>;
	412	+ regulator-compatible = "ldo4";
	413	+ regulator-min-microvolt = <800000>;
	414	+ regulator-max-microvolt = <3300000>;
	415	+ regulator-boot-on;
	416	+ regulator-always-on;
	417	+ };
	418	+
	419	+ ldo5_reg: regulator@10 {
	420	+ reg = <10>;
	421	+ regulator-compatible = "ldo5";
	422	+ regulator-min-microvolt = <1800000>;
	423	+ regulator-max-microvolt = <3300000>;
	424	+ };
	425	+ };
	426	+ };
	427	+};
	428	+
	429	+
	430	+&iomuxc {
	431	+ pinctrl-names = "default";
	432	+
	433	+ pinctrl_gpio_led: gpioledgrp {
	434	+ fsl,pins = <
	435	+ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
	436	+ >;
	437	+ };
	438	+
	439	+ pinctrl_uart2: uart2grp {
	440	+ fsl,pins = <
	441	+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
	442	+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
	443	+ >;
	444	+ };
	445	+
	446	+ pinctrl_i2c1: i2c1grp {
	447	+ fsl,pins = <
	448	+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
	449	+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
	450	+ >;
	451	+ };
	452	+
	453	+ pinctrl_pmic: pmicirq {
	454	+ fsl,pins = <
	455	+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
	456	+ >;
	457	+ };
	458	+
	459	+ pinctrl_usdhc2: usdhc2grp {
	460	+ fsl,pins = <
	461	+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
	462	+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
	463	+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
	464	+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
	465	+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
	466	+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
	467	+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
	468	+ >;
	469	+ };
	470	+
	471	+ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
	472	+ fsl,pins = <
	473	+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
	474	+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
	475	+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
	476	+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
	477	+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
	478	+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
	479	+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
	480	+ >;
	481	+ };
	482	+
	483	+ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
	484	+ fsl,pins = <
	485	+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
	486	+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
	487	+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
	488	+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
	489	+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
	490	+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
	491	+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
	492	+ >;
	493	+ };
	494	+
	495	+ pinctrl_usdhc2_gpio: usdhc2grp-gpio {
	496	+ fsl,pins = <
	497	+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
	498	+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
	499	+ >;
	500	+ };
	501	+
	502	+ pinctrl_usdhc3: usdhc3grp {
	503	+ fsl,pins = <
	504	+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
	505	+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
	506	+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
	507	+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
	508	+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
	509	+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
	510	+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
	511	+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
	512	+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
	513	+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
	514	+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
	515	+ >;
	516	+ };
	517	+
	518	+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
	519	+ fsl,pins = <
	520	+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
	521	+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
	522	+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
	523	+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
	524	+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
	525	+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
	526	+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
	527	+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
	528	+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
	529	+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
	530	+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
	531	+ >;
	532	+ };
	533	+
	534	+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
	535	+ fsl,pins = <
	536	+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
	537	+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
	538	+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
	539	+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
	540	+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
	541	+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
	542	+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
	543	+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
	544	+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
	545	+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
	546	+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
	547	+ >;
	548	+ };
	549	+
	550	+ pinctrl_eqos: eqosgrp {
	551	+ fsl,pins = <
	552	+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
	553	+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
	554	+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
	555	+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
	556	+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
	557	+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
	558	+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
	559	+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
	560	+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
	561	+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
	562	+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
	563	+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
	564	+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
	565	+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
	566	+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
	567	+ >;
	568	+ };
	569	+
	570	+ pinctrl_fec: fecgrp {
	571	+ fsl,pins = <
	572	+ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
	573	+ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
	574	+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
	575	+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
	576	+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
	577	+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
	578	+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
	579	+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
	580	+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
	581	+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
	582	+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
	583	+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
	584	+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
	585	+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
	586	+ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
	587	+ >;
	588	+ };
	589	+
	590	+ pinctrl_wdog: wdoggrp {
	591	+ fsl,pins = <
	592	+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
	593	+ >;
	594	+ };
	595	+};
	596	diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
	597	index b1240279..aae1f644 100644
	598	--- a/arch/arm/mach-imx/imx8m/Kconfig
	599	+++ b/arch/arm/mach-imx/imx8m/Kconfig
	600	@@ -318,6 +318,16 @@ config TARGET_IMX8MP_EVK
	601	select ARCH_MISC_INIT
	602	select SPL_CRYPTO if SPL
	603
	604	+config TARGET_IGKBOARD_IMX8MP
	605	+ bool "LingYun IoT Gateway Kits Board based on i.MX8M Plus"
	606	+ select IMX8MP
	607	+ select SUPPORT_SPL
	608	+ select IMX8M_LPDDR4
	609	+ select FSL_CAAM
	610	+ select FSL_BLOB
	611	+ select ARCH_MISC_INIT
	612	+ select SPL_CRYPTO if SPL
	613	+
	614	config TARGET_IMX8MP_VENICE
	615	bool "Support Gateworks Venice iMX8M Plus module"
	616	select BINMAN
	617	@@ -481,5 +491,6 @@ source "board/technexion/pico-imx8mq/Kconfig"
	618	source "board/variscite/imx8mn_var_som/Kconfig"
	619	source "board/toradex/verdin-imx8mm/Kconfig"
	620	source "board/toradex/verdin-imx8mp/Kconfig"
	621	+source "board/lingyun/igkboard-imx8mp/Kconfig"
	622
	623	endif
	624	diff --git a/board/lingyun/igkboard-imx8mp/Kconfig b/board/lingyun/igkboard-imx8mp/Kconfig
	625	new file mode 100644
	626	index 00000000..50ec59bc
	627	--- /dev/null
	628	+++ b/board/lingyun/igkboard-imx8mp/Kconfig
	629	@@ -0,0 +1,15 @@
	630	+if TARGET_IGKBOARD_IMX8MP
	631	+
	632	+config SYS_BOARD
	633	+ default "igkboard-imx8mp"
	634	+
	635	+config SYS_VENDOR
	636	+ default "lingyun"
	637	+
	638	+config SYS_CONFIG_NAME
	639	+ default "igkboard-imx8mp"
	640	+
	641	+config IMX_CONFIG
	642	+ default "board/lingyun/igkboard-imx8mp/imximage-8mp-lpddr4.cfg"
	643	+
	644	+endif
	645	diff --git a/board/lingyun/igkboard-imx8mp/MAINTAINERS b/board/lingyun/igkboard-imx8mp/MAINTAINERS
	646	new file mode 100644
	647	index 00000000..76066977
	648	--- /dev/null
	649	+++ b/board/lingyun/igkboard-imx8mp/MAINTAINERS
	650	@@ -0,0 +1,7 @@
	651	+IGKBoard i.MX8MP
	652	+M: Wenxue Guo <guowenxue@gmail.com>
	653	+S: Maintained
	654	+B: board/freescale/imx8mp_evk/
	655	+F: board/lingyun/igkboard-imx8mp/
	656	+F: include/configs/igkboard-imx8mp.h
	657	+F: configs/igkboard-imx8mp_defconfig
	658	diff --git a/board/lingyun/igkboard-imx8mp/Makefile b/board/lingyun/igkboard-imx8mp/Makefile
	659	new file mode 100644
	660	index 00000000..05c561ed
	661	--- /dev/null
	662	+++ b/board/lingyun/igkboard-imx8mp/Makefile
	663	@@ -0,0 +1,13 @@
	664	+#
	665	+# Copyright 2019 NXP
	666	+#
	667	+# SPDX-License-Identifier: GPL-2.0+
	668	+#
	669	+
	670	+obj-y += igkboard-imx8mp.o
	671	+obj-y += ../../freescale/common/mmc.o
	672	+
	673	+ifdef CONFIG_SPL_BUILD
	674	+obj-y += spl.o
	675	+obj-y += lpddr4_timing.o
	676	+endif
	677	diff --git a/board/lingyun/igkboard-imx8mp/igkboard-imx8mp.c b/board/lingyun/igkboard-imx8mp/igkboard-imx8mp.c
	678	new file mode 100644
	679	index 00000000..189ab3b1
	680	--- /dev/null
	681	+++ b/board/lingyun/igkboard-imx8mp/igkboard-imx8mp.c
	682	@@ -0,0 +1,513 @@
	683	+// SPDX-License-Identifier: GPL-2.0+
	684	+/*
	685	+ * Copyright 2019 NXP
	686	+ */
	687	+
	688	+#include <common.h>
	689	+#include <efi_loader.h>
	690	+#include <env.h>
	691	+#include <errno.h>
	692	+#include <init.h>
	693	+#include <miiphy.h>
	694	+#include <netdev.h>
	695	+#include <linux/delay.h>
	696	+#include <asm/global_data.h>
	697	+#include <asm/io.h>
	698	+#include <asm/mach-imx/iomux-v3.h>
	699	+#include <asm-generic/gpio.h>
	700	+#include <asm/arch/imx8mp_pins.h>
	701	+#include <asm/arch/clock.h>
	702	+#include <asm/arch/sys_proto.h>
	703	+#include <asm/mach-imx/gpio.h>
	704	+#include <asm/mach-imx/mxc_i2c.h>
	705	+#include <spl.h>
	706	+#include <asm/mach-imx/dma.h>
	707	+#include <power/pmic.h>
	708	+#include "../../freescale/common/tcpc.h"
	709	+#include <usb.h>
	710	+#include <dwc3-uboot.h>
	711	+#include <mmc.h>
	712	+
	713	+DECLARE_GLOBAL_DATA_PTR;
	714	+
	715	+#define UART_PAD_CTRL (PAD_CTL_DSE6 \| PAD_CTL_FSEL1)
	716	+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 \| PAD_CTL_ODE \| PAD_CTL_PUE \| PAD_CTL_PE)
	717	+
	718	+static iomux_v3_cfg_t const uart_pads[] = {
	719	+ MX8MP_PAD_UART2_RXD__UART2_DCE_RX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	720	+ MX8MP_PAD_UART2_TXD__UART2_DCE_TX \| MUX_PAD_CTRL(UART_PAD_CTRL),
	721	+};
	722	+
	723	+static iomux_v3_cfg_t const wdog_pads[] = {
	724	+ MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B \| MUX_PAD_CTRL(WDOG_PAD_CTRL),
	725	+};
	726	+
	727	+#ifdef CONFIG_NAND_MXS
	728	+
	729	+static void setup_gpmi_nand(void)
	730	+{
	731	+ init_nand_clk();
	732	+}
	733	+#endif
	734	+
	735	+#if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
	736	+struct efi_fw_image fw_images[] = {
	737	+ {
	738	+ .image_type_id = IMX_BOOT_IMAGE_GUID,
	739	+ .fw_name = u"IMX8MP-EVK-RAW",
	740	+ .image_index = 1,
	741	+ },
	742	+};
	743	+
	744	+struct efi_capsule_update_info update_info = {
	745	+ .dfu_string = "mmc 2=flash-bin raw 0 0x2000 mmcpart 1",
	746	+ .images = fw_images,
	747	+};
	748	+
	749	+u8 num_image_type_guids = ARRAY_SIZE(fw_images);
	750	+#endif /* EFI_HAVE_CAPSULE_SUPPORT */
	751	+
	752	+int board_early_init_f(void)
	753	+{
	754	+ struct wdog_regs wdog = (struct wdog_regs )WDOG1_BASE_ADDR;
	755	+
	756	+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
	757	+
	758	+ set_wdog_reset(wdog);
	759	+
	760	+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
	761	+
	762	+ init_uart_clk(1);
	763	+
	764	+ return 0;
	765	+}
	766	+
	767	+#ifdef CONFIG_OF_BOARD_SETUP
	768	+int ft_board_setup(void blob, struct bd_info bd)
	769	+{
	770	+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
	771	+#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK
	772	+ int rc;
	773	+ phys_addr_t ecc_start = 0x120000000;
	774	+ size_t ecc_size = 0x20000000;
	775	+
	776	+ rc = add_res_mem_dt_node(blob, "ecc", ecc_start, ecc_size);
	777	+ if (rc < 0) {
	778	+ printf("Could not create ecc reserved-memory node.\n");
	779	+ return rc;
	780	+ }
	781	+#else
	782	+ int rc;
	783	+ phys_addr_t ecc0_start = 0xb0000000;
	784	+ phys_addr_t ecc1_start = 0x130000000;
	785	+ phys_addr_t ecc2_start = 0x1b0000000;
	786	+ size_t ecc_size = 0x10000000;
	787	+
	788	+ rc = add_res_mem_dt_node(blob, "ecc", ecc0_start, ecc_size);
	789	+ if (rc < 0) {
	790	+ printf("Could not create ecc0 reserved-memory node.\n");
	791	+ return rc;
	792	+ }
	793	+
	794	+ rc = add_res_mem_dt_node(blob, "ecc", ecc1_start, ecc_size);
	795	+ if (rc < 0) {
	796	+ printf("Could not create ecc1 reserved-memory node.\n");
	797	+ return rc;
	798	+ }
	799	+
	800	+ rc = add_res_mem_dt_node(blob, "ecc", ecc2_start, ecc_size);
	801	+ if (rc < 0) {
	802	+ printf("Could not create ecc2 reserved-memory node.\n");
	803	+ return rc;
	804	+ }
	805	+#endif
	806	+#endif
	807	+
	808	+ return 0;
	809	+}
	810	+#endif
	811	+
	812	+#ifdef CONFIG_USB_TCPC
	813	+struct tcpc_port port1;
	814	+struct tcpc_port port2;
	815	+
	816	+static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr)
	817	+{
	818	+ struct udevice *bus;
	819	+ struct udevice *i2c_dev = NULL;
	820	+ int ret;
	821	+ uint8_t valb;
	822	+
	823	+ ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus);
	824	+ if (ret) {
	825	+ printf("%s: Can't find bus\n", __func__);
	826	+ return -EINVAL;
	827	+ }
	828	+
	829	+ ret = dm_i2c_probe(bus, addr, 0, &i2c_dev);
	830	+ if (ret) {
	831	+ printf("%s: Can't find device id=0x%x\n",
	832	+ __func__, addr);
	833	+ return -ENODEV;
	834	+ }
	835	+
	836	+ ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1);
	837	+ if (ret) {
	838	+ printf("%s dm_i2c_read failed, err %d\n", __func__, ret);
	839	+ return -EIO;
	840	+ }
	841	+ valb \|= 0x4; /* Set DB_EXIT to exit dead battery mode */
	842	+ ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1);
	843	+ if (ret) {
	844	+ printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
	845	+ return -EIO;
	846	+ }
	847	+
	848	+ /* Set OVP threshold to 23V */
	849	+ valb = 0x6;
	850	+ ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1);
	851	+ if (ret) {
	852	+ printf("%s dm_i2c_write failed, err %d\n", __func__, ret);
	853	+ return -EIO;
	854	+ }
	855	+
	856	+ return 0;
	857	+}
	858	+
	859	+int pd_switch_snk_enable(struct tcpc_port *port)
	860	+{
	861	+ if (port == &port1) {
	862	+ debug("Setup pd switch on port 1\n");
	863	+ return setup_pd_switch(1, 0x72);
	864	+ } else
	865	+ return -EINVAL;
	866	+}
	867	+
	868	+/* Port2 is the power supply, port 1 does not support power */
	869	+struct tcpc_port_config port1_config = {
	870	+ .i2c_bus = 1, /i2c2/
	871	+ .addr = 0x50,
	872	+ .port_type = TYPEC_PORT_UFP,
	873	+ .max_snk_mv = 20000,
	874	+ .max_snk_ma = 3000,
	875	+ .max_snk_mw = 45000,
	876	+ .op_snk_mv = 15000,
	877	+ .switch_setup_func = &pd_switch_snk_enable,
	878	+ .disable_pd = true,
	879	+};
	880	+
	881	+struct tcpc_port_config port2_config = {
	882	+ .i2c_bus = 2, /i2c3/
	883	+ .addr = 0x50,
	884	+ .port_type = TYPEC_PORT_UFP,
	885	+ .max_snk_mv = 20000,
	886	+ .max_snk_ma = 3000,
	887	+ .max_snk_mw = 45000,
	888	+ .op_snk_mv = 15000,
	889	+};
	890	+
	891	+#define USB_TYPEC_SEL IMX_GPIO_NR(4, 20)
	892	+#define USB_TYPEC_EN IMX_GPIO_NR(2, 20)
	893	+
	894	+static iomux_v3_cfg_t ss_mux_gpio[] = {
	895	+ MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	896	+ MX8MP_PAD_SD2_WP__GPIO2_IO20 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	897	+};
	898	+
	899	+void ss_mux_select(enum typec_cc_polarity pol)
	900	+{
	901	+ if (pol == TYPEC_POLARITY_CC1)
	902	+ gpio_direction_output(USB_TYPEC_SEL, 0);
	903	+ else
	904	+ gpio_direction_output(USB_TYPEC_SEL, 1);
	905	+}
	906	+
	907	+static int setup_typec(void)
	908	+{
	909	+ int ret;
	910	+ struct gpio_desc per_12v_desc;
	911	+
	912	+ debug("tcpc_init port 2\n");
	913	+ ret = tcpc_init(&port2, port2_config, NULL);
	914	+ if (ret) {
	915	+ printf("%s: tcpc port2 init failed, err=%d\n",
	916	+ __func__, ret);
	917	+ } else if (tcpc_pd_sink_check_charging(&port2)) {
	918	+ printf("Power supply on USB2\n");
	919	+
	920	+ /* Enable PER 12V, any check before it? */
	921	+ ret = dm_gpio_lookup_name("gpio@20_1", &per_12v_desc);
	922	+ if (ret) {
	923	+ printf("%s lookup gpio@20_1 failed ret = %d\n", __func__, ret);
	924	+ return -ENODEV;
	925	+ }
	926	+
	927	+ ret = dm_gpio_request(&per_12v_desc, "per_12v_en");
	928	+ if (ret) {
	929	+ printf("%s request per_12v failed ret = %d\n", __func__, ret);
	930	+ return -EIO;
	931	+ }
	932	+
	933	+ /* Enable PER 12V regulator */
	934	+ dm_gpio_set_dir_flags(&per_12v_desc, GPIOD_IS_OUT \| GPIOD_IS_OUT_ACTIVE);
	935	+ }
	936	+
	937	+ debug("tcpc_init port 1\n");
	938	+ imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
	939	+ gpio_request(USB_TYPEC_SEL, "typec_sel");
	940	+ gpio_request(USB_TYPEC_EN, "typec_en");
	941	+ gpio_direction_output(USB_TYPEC_EN, 0);
	942	+
	943	+ ret = tcpc_init(&port1, port1_config, &ss_mux_select);
	944	+ if (ret) {
	945	+ printf("%s: tcpc port1 init failed, err=%d\n",
	946	+ __func__, ret);
	947	+ } else {
	948	+ return ret;
	949	+ }
	950	+
	951	+ return ret;
	952	+}
	953	+#endif
	954	+
	955	+#ifdef CONFIG_USB_DWC3
	956	+
	957	+#define USB_PHY_CTRL0 0xF0040
	958	+#define USB_PHY_CTRL0_REF_SSP_EN BIT(2)
	959	+
	960	+#define USB_PHY_CTRL1 0xF0044
	961	+#define USB_PHY_CTRL1_RESET BIT(0)
	962	+#define USB_PHY_CTRL1_COMMONONN BIT(1)
	963	+#define USB_PHY_CTRL1_ATERESET BIT(3)
	964	+#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19)
	965	+#define USB_PHY_CTRL1_VDATDETENB0 BIT(20)
	966	+
	967	+#define USB_PHY_CTRL2 0xF0048
	968	+#define USB_PHY_CTRL2_TXENABLEN0 BIT(8)
	969	+
	970	+#define USB_PHY_CTRL6 0xF0058
	971	+
	972	+#define HSIO_GPR_BASE (0x32F10000U)
	973	+#define HSIO_GPR_REG_0 (HSIO_GPR_BASE)
	974	+#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT (1)
	975	+#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN (0x1U << HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT)
	976	+
	977	+
	978	+static struct dwc3_device dwc3_device_data = {
	979	+#ifdef CONFIG_SPL_BUILD
	980	+ .maximum_speed = USB_SPEED_HIGH,
	981	+#else
	982	+ .maximum_speed = USB_SPEED_SUPER,
	983	+#endif
	984	+ .base = USB1_BASE_ADDR,
	985	+ .dr_mode = USB_DR_MODE_PERIPHERAL,
	986	+ .index = 0,
	987	+ .power_down_scale = 2,
	988	+};
	989	+
	990	+int usb_gadget_handle_interrupts(int index)
	991	+{
	992	+ dwc3_uboot_handle_interrupt(index);
	993	+ return 0;
	994	+}
	995	+
	996	+static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
	997	+{
	998	+ u32 RegData;
	999	+
	1000	+ /* enable usb clock via hsio gpr */
	1001	+ RegData = readl(HSIO_GPR_REG_0);
	1002	+ RegData \|= HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN;
	1003	+ writel(RegData, HSIO_GPR_REG_0);
	1004	+
	1005	+ /* USB3.0 PHY signal fsel for 100M ref */
	1006	+ RegData = readl(dwc3->base + USB_PHY_CTRL0);
	1007	+ RegData = (RegData & 0xfffff81f) \| (0x2a<<5);
	1008	+ writel(RegData, dwc3->base + USB_PHY_CTRL0);
	1009	+
	1010	+ RegData = readl(dwc3->base + USB_PHY_CTRL6);
	1011	+ RegData &=~0x1;
	1012	+ writel(RegData, dwc3->base + USB_PHY_CTRL6);
	1013	+
	1014	+ RegData = readl(dwc3->base + USB_PHY_CTRL1);
	1015	+ RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 \| USB_PHY_CTRL1_VDATDETENB0 \|
	1016	+ USB_PHY_CTRL1_COMMONONN);
	1017	+ RegData \|= USB_PHY_CTRL1_RESET \| USB_PHY_CTRL1_ATERESET;
	1018	+ writel(RegData, dwc3->base + USB_PHY_CTRL1);
	1019	+
	1020	+ RegData = readl(dwc3->base + USB_PHY_CTRL0);
	1021	+ RegData \|= USB_PHY_CTRL0_REF_SSP_EN;
	1022	+ writel(RegData, dwc3->base + USB_PHY_CTRL0);
	1023	+
	1024	+ RegData = readl(dwc3->base + USB_PHY_CTRL2);
	1025	+ RegData \|= USB_PHY_CTRL2_TXENABLEN0;
	1026	+ writel(RegData, dwc3->base + USB_PHY_CTRL2);
	1027	+
	1028	+ RegData = readl(dwc3->base + USB_PHY_CTRL1);
	1029	+ RegData &= ~(USB_PHY_CTRL1_RESET \| USB_PHY_CTRL1_ATERESET);
	1030	+ writel(RegData, dwc3->base + USB_PHY_CTRL1);
	1031	+}
	1032	+#endif
	1033	+
	1034	+#if defined(CONFIG_USB_DWC3) \|\| defined(CONFIG_USB_XHCI_IMX8M)
	1035	+#define USB2_PWR_EN IMX_GPIO_NR(1, 14)
	1036	+int board_usb_init(int index, enum usb_init_type init)
	1037	+{
	1038	+ int ret = 0;
	1039	+
	1040	+ if (index == 0 && init == USB_INIT_DEVICE) {
	1041	+ imx8m_usb_power(index, true);
	1042	+#ifdef CONFIG_USB_TCPC
	1043	+ ret = tcpc_setup_ufp_mode(&port1);
	1044	+ if (ret)
	1045	+ return ret;
	1046	+#endif
	1047	+ dwc3_nxp_usb_phy_init(&dwc3_device_data);
	1048	+ return dwc3_uboot_init(&dwc3_device_data);
	1049	+ } else if (index == 0 && init == USB_INIT_HOST) {
	1050	+#ifdef CONFIG_USB_TCPC
	1051	+ ret = tcpc_setup_dfp_mode(&port1);
	1052	+#endif
	1053	+ return ret;
	1054	+ }
	1055	+
	1056	+ return 0;
	1057	+}
	1058	+
	1059	+int board_usb_cleanup(int index, enum usb_init_type init)
	1060	+{
	1061	+ int ret = 0;
	1062	+ if (index == 0 && init == USB_INIT_DEVICE) {
	1063	+ dwc3_uboot_exit(index);
	1064	+ imx8m_usb_power(index, false);
	1065	+ } else if (index == 0 && init == USB_INIT_HOST) {
	1066	+#ifdef CONFIG_USB_TCPC
	1067	+ ret = tcpc_disable_src_vbus(&port1);
	1068	+#endif
	1069	+ }
	1070	+
	1071	+ return ret;
	1072	+}
	1073	+
	1074	+#ifdef CONFIG_USB_TCPC
	1075	+/* Not used so far */
	1076	+int board_typec_get_mode(int index)
	1077	+{
	1078	+ int ret = 0;
	1079	+ enum typec_cc_polarity pol;
	1080	+ enum typec_cc_state state;
	1081	+
	1082	+ if (index == 0) {
	1083	+ tcpc_setup_ufp_mode(&port1);
	1084	+
	1085	+ ret = tcpc_get_cc_status(&port1, &pol, &state);
	1086	+ if (!ret) {
	1087	+ if (state == TYPEC_STATE_SRC_RD_RA \|\| state == TYPEC_STATE_SRC_RD)
	1088	+ return USB_INIT_HOST;
	1089	+ }
	1090	+
	1091	+ return USB_INIT_DEVICE;
	1092	+ } else {
	1093	+ return USB_INIT_HOST;
	1094	+ }
	1095	+}
	1096	+#endif
	1097	+#endif
	1098	+
	1099	+static void setup_fec(void)
	1100	+{
	1101	+ struct iomuxc_gpr_base_regs *gpr =
	1102	+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
	1103	+
	1104	+ /* Enable RGMII TX clk output */
	1105	+ setbits_le32(&gpr->gpr[1], BIT(22));
	1106	+}
	1107	+
	1108	+static int setup_eqos(void)
	1109	+{
	1110	+ struct iomuxc_gpr_base_regs *gpr =
	1111	+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
	1112	+
	1113	+ /* set INTF as RGMII, enable RGMII TXC clock */
	1114	+ clrsetbits_le32(&gpr->gpr[1],
	1115	+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
	1116	+ setbits_le32(&gpr->gpr[1], BIT(19) \| BIT(21));
	1117	+
	1118	+ return set_clk_eqos(ENET_125MHZ);
	1119	+}
	1120	+
	1121	+#if CONFIG_IS_ENABLED(NET)
	1122	+int board_phy_config(struct phy_device *phydev)
	1123	+{
	1124	+ if (phydev->drv->config)
	1125	+ phydev->drv->config(phydev);
	1126	+ return 0;
	1127	+}
	1128	+#endif
	1129	+
	1130	+int board_init(void)
	1131	+{
	1132	+#ifdef CONFIG_USB_TCPC
	1133	+ setup_typec();
	1134	+#endif
	1135	+
	1136	+ if (IS_ENABLED(CONFIG_FEC_MXC)) {
	1137	+ setup_fec();
	1138	+ }
	1139	+
	1140	+ if (IS_ENABLED(CONFIG_DWC_ETH_QOS)) {
	1141	+ setup_eqos();
	1142	+ }
	1143	+
	1144	+#ifdef CONFIG_NAND_MXS
	1145	+ setup_gpmi_nand();
	1146	+#endif
	1147	+
	1148	+#if defined(CONFIG_USB_DWC3) \|\| defined(CONFIG_USB_XHCI_IMX8M)
	1149	+ init_usb_clk();
	1150	+#endif
	1151	+
	1152	+ return 0;
	1153	+}
	1154	+
	1155	+int board_late_init(void)
	1156	+{
	1157	+#ifdef CONFIG_ENV_IS_IN_MMC
	1158	+ board_late_mmc_env_init();
	1159	+#endif
	1160	+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	1161	+ env_set("board_name", "EVK");
	1162	+ env_set("board_rev", "iMX8MP");
	1163	+#endif
	1164	+
	1165	+ return 0;
	1166	+}
	1167	+
	1168	+#ifdef CONFIG_ANDROID_SUPPORT
	1169	+bool is_power_key_pressed(void) {
	1170	+ return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6)));
	1171	+}
	1172	+#endif
	1173	+
	1174	+#ifdef CONFIG_SPL_MMC
	1175	+#define UBOOT_RAW_SECTOR_OFFSET 0x40
	1176	+unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc)
	1177	+{
	1178	+ u32 boot_dev = spl_boot_device();
	1179	+ switch (boot_dev) {
	1180	+ case BOOT_DEVICE_MMC2:
	1181	+ return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET;
	1182	+ default:
	1183	+ return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR;
	1184	+ }
	1185	+}
	1186	+#endif
	1187	+
	1188	+#ifdef CONFIG_FSL_FASTBOOT
	1189	+#ifdef CONFIG_ANDROID_RECOVERY
	1190	+int is_recovery_key_pressing(void)
	1191	+{
	1192	+ return 0; /* TODO */
	1193	+}
	1194	+#endif /* CONFIG_ANDROID_RECOVERY */
	1195	+#endif /* CONFIG_FSL_FASTBOOT */
	1196	diff --git a/board/lingyun/igkboard-imx8mp/imximage-8mp-lpddr4.cfg b/board/lingyun/igkboard-imx8mp/imximage-8mp-lpddr4.cfg
	1197	new file mode 100644
	1198	index 00000000..6dedf172
	1199	--- /dev/null
	1200	+++ b/board/lingyun/igkboard-imx8mp/imximage-8mp-lpddr4.cfg
	1201	@@ -0,0 +1,9 @@
	1202	+/* SPDX-License-Identifier: GPL-2.0+ */
	1203	+/*
	1204	+ * Copyright 2021 NXP
	1205	+ */
	1206	+
	1207	+
	1208	+ROM_VERSION v2
	1209	+BOOT_FROM sd
	1210	+LOADER u-boot-spl-ddr.bin 0x920000
	1211	diff --git a/board/lingyun/igkboard-imx8mp/lpddr4_timing.c b/board/lingyun/igkboard-imx8mp/lpddr4_timing.c
	1212	new file mode 100644
	1213	index 00000000..8c5306d5
	1214	--- /dev/null
	1215	+++ b/board/lingyun/igkboard-imx8mp/lpddr4_timing.c
	1216	@@ -0,0 +1,2048 @@
	1217	+// SPDX-License-Identifier: GPL-2.0+
	1218	+/*
	1219	+ * Copyright 2019 NXP
	1220	+ */
	1221	+
	1222	+#include <linux/kernel.h>
	1223	+#include <asm/arch/ddr.h>
	1224	+
	1225	+struct dram_cfg_param ddr_ddrc_cfg[] = {
	1226	+ / Initialize DDRC registers /
	1227	+ { 0x3d400304, 0x1 },
	1228	+ { 0x3d400030, 0x1 },
	1229	+ { 0x3d400000, 0xa3080020 },
	1230	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	1231	+ { 0x3d400020, 0x223 },
	1232	+ { 0x3d400024, 0x124f800 },
	1233	+ { 0x3d400064, 0x4900a8 },
	1234	+ { 0x3d400070, 0x1027f90 },
	1235	+ { 0x3d400074, 0x790 },
	1236	+ { 0x3d4000d0, 0xc0030495 },
	1237	+ { 0x3d4000d4, 0x770000 },
	1238	+ { 0x3d4000dc, 0xc40024 },
	1239	+#else
	1240	+ { 0x3d400020, 0x1323 },
	1241	+ { 0x3d400024, 0x1e84800 },
	1242	+ { 0x3d400064, 0x7a017c },
	1243	+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
	1244	+ { 0x3d400070, 0x1027f54 },
	1245	+#else
	1246	+ { 0x3d400070, 0x1027f10 },
	1247	+#endif
	1248	+ { 0x3d400074, 0x7b0 },
	1249	+ { 0x3d4000d0, 0xc00307a3 },
	1250	+ { 0x3d4000d4, 0xc50000 },
	1251	+ { 0x3d4000dc, 0xf4003f },
	1252	+#endif
	1253	+ { 0x3d4000e0, 0x330000 },
	1254	+ { 0x3d4000e8, 0x660048 },
	1255	+ { 0x3d4000ec, 0x160048 },
	1256	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	1257	+ { 0x3d400100, 0x1618141a },
	1258	+ { 0x3d400104, 0x504a6 },
	1259	+ { 0x3d40010c, 0x909000 },
	1260	+ { 0x3d400110, 0xb04060b },
	1261	+ { 0x3d400114, 0x2030909 },
	1262	+ { 0x3d400118, 0x1010006 },
	1263	+ { 0x3d40011c, 0x301 },
	1264	+ { 0x3d400130, 0x20500 },
	1265	+ { 0x3d400134, 0xb100002 },
	1266	+ { 0x3d400138, 0xad },
	1267	+ { 0x3d400144, 0x78003c },
	1268	+ { 0x3d400180, 0x2580012 },
	1269	+ { 0x3d400184, 0x1e0493e },
	1270	+ { 0x3d400188, 0x0 },
	1271	+ { 0x3d400190, 0x4938208 },
	1272	+ { 0x3d400194, 0x80303 },
	1273	+ { 0x3d4001b4, 0x1308 },
	1274	+#else
	1275	+ { 0x3d400100, 0x2028222a },
	1276	+ { 0x3d400104, 0x807bf },
	1277	+ { 0x3d40010c, 0xe0e000 },
	1278	+ { 0x3d400110, 0x12040a12 },
	1279	+ { 0x3d400114, 0x2050f0f },
	1280	+ { 0x3d400118, 0x1010009 },
	1281	+ { 0x3d40011c, 0x501 },
	1282	+ { 0x3d400130, 0x20800 },
	1283	+ { 0x3d400134, 0xe100002 },
	1284	+ { 0x3d400138, 0x184 },
	1285	+ { 0x3d400144, 0xc80064 },
	1286	+ { 0x3d400180, 0x3e8001e },
	1287	+ { 0x3d400184, 0x3207a12 },
	1288	+ { 0x3d400188, 0x0 },
	1289	+ { 0x3d400190, 0x49f820e },
	1290	+ { 0x3d400194, 0x80303 },
	1291	+ { 0x3d4001b4, 0x1f0e },
	1292	+#endif
	1293	+ { 0x3d4001a0, 0xe0400018 },
	1294	+ { 0x3d4001a4, 0xdf00e4 },
	1295	+ { 0x3d4001a8, 0x80000000 },
	1296	+ { 0x3d4001b0, 0x11 },
	1297	+ { 0x3d4001c0, 0x1 },
	1298	+ { 0x3d4001c4, 0x1 },
	1299	+ { 0x3d4000f4, 0xc99 },
	1300	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	1301	+ { 0x3d400108, 0x60c1514 },
	1302	+ { 0x3d400200, 0x16 },
	1303	+ { 0x3d40020c, 0x0 },
	1304	+ { 0x3d400210, 0x1f1f },
	1305	+ { 0x3d400204, 0x80808 },
	1306	+ { 0x3d400214, 0x7070707 },
	1307	+ { 0x3d400218, 0x68070707 },
	1308	+ { 0x3d40021c, 0xf08 },
	1309	+ { 0x3d400250, 0x1f05 },
	1310	+ { 0x3d400254, 0x1f },
	1311	+ { 0x3d400264, 0x90003ff },
	1312	+ { 0x3d40026c, 0x20003ff },
	1313	+ { 0x3d400400, 0x111 },
	1314	+ { 0x3d400408, 0x72ff },
	1315	+ { 0x3d400494, 0x1000e00 },
	1316	+ { 0x3d400498, 0x3ff0000 },
	1317	+ { 0x3d40049c, 0x1000e00 },
	1318	+ { 0x3d4004a0, 0x3ff0000 },
	1319	+ { 0x3d402020, 0x21 },
	1320	+ { 0x3d402024, 0x30d400 },
	1321	+ { 0x3d402050, 0x20d000 },
	1322	+ { 0x3d402064, 0xc001c },
	1323	+#else
	1324	+ { 0x3d400108, 0x9121c1c },
	1325	+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
	1326	+ { 0x3d400200, 0x13 },
	1327	+ { 0x3d40020c, 0x13131300 },
	1328	+ { 0x3d400210, 0x1f1f },
	1329	+ { 0x3d400204, 0x50505 },
	1330	+ { 0x3d400214, 0x4040404 },
	1331	+ { 0x3d400218, 0x68040404 },
	1332	+#else
	1333	+ { 0x3d400200, 0x16 },
	1334	+ { 0x3d40020c, 0x0 },
	1335	+ { 0x3d400210, 0x1f1f },
	1336	+ { 0x3d400204, 0x80808 },
	1337	+ { 0x3d400214, 0x7070707 },
	1338	+ { 0x3d400218, 0x68070707 },
	1339	+#endif
	1340	+ { 0x3d40021c, 0xf08 },
	1341	+ { 0x3d400250, 0x1705 },
	1342	+ { 0x3d400254, 0x2c },
	1343	+ { 0x3d40025c, 0x4000030 },
	1344	+ { 0x3d400264, 0x900093e7 },
	1345	+ { 0x3d40026c, 0x2005574 },
	1346	+ { 0x3d400400, 0x111 },
	1347	+ { 0x3d400404, 0x72ff },
	1348	+ { 0x3d400408, 0x72ff },
	1349	+ { 0x3d400494, 0x2100e07 },
	1350	+ { 0x3d400498, 0x620096 },
	1351	+ { 0x3d40049c, 0x1100e07 },
	1352	+ { 0x3d4004a0, 0xc8012c },
	1353	+ { 0x3d402020, 0x1021 },
	1354	+ { 0x3d402024, 0x30d400 },
	1355	+ { 0x3d402050, 0x20d000 },
	1356	+ { 0x3d402064, 0xc0026 },
	1357	+#endif
	1358	+ { 0x3d4020dc, 0x840000 },
	1359	+ { 0x3d4020e0, 0x330000 },
	1360	+ { 0x3d4020e8, 0x660048 },
	1361	+ { 0x3d4020ec, 0x160048 },
	1362	+ { 0x3d402100, 0xa040305 },
	1363	+ { 0x3d402104, 0x30407 },
	1364	+ { 0x3d402108, 0x203060b },
	1365	+ { 0x3d40210c, 0x505000 },
	1366	+ { 0x3d402110, 0x2040202 },
	1367	+ { 0x3d402114, 0x2030202 },
	1368	+ { 0x3d402118, 0x1010004 },
	1369	+ { 0x3d40211c, 0x301 },
	1370	+ { 0x3d402130, 0x20300 },
	1371	+ { 0x3d402134, 0xa100002 },
	1372	+ { 0x3d402138, 0x27 },
	1373	+ { 0x3d402144, 0x14000a },
	1374	+ { 0x3d402180, 0x640004 },
	1375	+ { 0x3d402190, 0x3818200 },
	1376	+ { 0x3d402194, 0x80303 },
	1377	+ { 0x3d4021b4, 0x100 },
	1378	+ { 0x3d4020f4, 0xc99 },
	1379	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	1380	+ { 0x3d403020, 0x21 },
	1381	+ { 0x3d403024, 0xc3500 },
	1382	+ { 0x3d403050, 0x20d000 },
	1383	+ { 0x3d403064, 0x30007 },
	1384	+#else
	1385	+ { 0x3d403020, 0x1021 },
	1386	+ { 0x3d403024, 0xc3500 },
	1387	+ { 0x3d403050, 0x20d000 },
	1388	+ { 0x3d403064, 0x3000a },
	1389	+#endif
	1390	+ { 0x3d4030dc, 0x840000 },
	1391	+ { 0x3d4030e0, 0x330000 },
	1392	+ { 0x3d4030e8, 0x660048 },
	1393	+ { 0x3d4030ec, 0x160048 },
	1394	+ { 0x3d403100, 0xa010102 },
	1395	+ { 0x3d403104, 0x30404 },
	1396	+ { 0x3d403108, 0x203060b },
	1397	+ { 0x3d40310c, 0x505000 },
	1398	+ { 0x3d403110, 0x2040202 },
	1399	+ { 0x3d403114, 0x2030202 },
	1400	+ { 0x3d403118, 0x1010004 },
	1401	+ { 0x3d40311c, 0x301 },
	1402	+ { 0x3d403130, 0x20300 },
	1403	+ { 0x3d403134, 0xa100002 },
	1404	+ { 0x3d403138, 0xa },
	1405	+ { 0x3d403144, 0x50003 },
	1406	+ { 0x3d403180, 0x190004 },
	1407	+ { 0x3d403190, 0x3818200 },
	1408	+ { 0x3d403194, 0x80303 },
	1409	+ { 0x3d4031b4, 0x100 },
	1410	+ { 0x3d4030f4, 0xc99 },
	1411	+ { 0x3d400028, 0x0 },
	1412	+};
	1413	+
	1414	+/* PHY Initialize Configuration */
	1415	+struct dram_cfg_param ddr_ddrphy_cfg[] = {
	1416	+ { 0x100a0, 0x0 },
	1417	+ { 0x100a1, 0x1 },
	1418	+ { 0x100a2, 0x2 },
	1419	+ { 0x100a3, 0x3 },
	1420	+ { 0x100a4, 0x4 },
	1421	+ { 0x100a5, 0x5 },
	1422	+ { 0x100a6, 0x6 },
	1423	+ { 0x100a7, 0x7 },
	1424	+ { 0x110a0, 0x0 },
	1425	+ { 0x110a1, 0x1 },
	1426	+ { 0x110a2, 0x3 },
	1427	+ { 0x110a3, 0x4 },
	1428	+ { 0x110a4, 0x5 },
	1429	+ { 0x110a5, 0x2 },
	1430	+ { 0x110a6, 0x7 },
	1431	+ { 0x110a7, 0x6 },
	1432	+ { 0x120a0, 0x0 },
	1433	+ { 0x120a1, 0x1 },
	1434	+ { 0x120a2, 0x3 },
	1435	+ { 0x120a3, 0x2 },
	1436	+ { 0x120a4, 0x5 },
	1437	+ { 0x120a5, 0x4 },
	1438	+ { 0x120a6, 0x7 },
	1439	+ { 0x120a7, 0x6 },
	1440	+ { 0x130a0, 0x0 },
	1441	+ { 0x130a1, 0x1 },
	1442	+ { 0x130a2, 0x2 },
	1443	+ { 0x130a3, 0x3 },
	1444	+ { 0x130a4, 0x4 },
	1445	+ { 0x130a5, 0x5 },
	1446	+ { 0x130a6, 0x6 },
	1447	+ { 0x130a7, 0x7 },
	1448	+ { 0x1005f, 0x1ff },
	1449	+ { 0x1015f, 0x1ff },
	1450	+ { 0x1105f, 0x1ff },
	1451	+ { 0x1115f, 0x1ff },
	1452	+ { 0x1205f, 0x1ff },
	1453	+ { 0x1215f, 0x1ff },
	1454	+ { 0x1305f, 0x1ff },
	1455	+ { 0x1315f, 0x1ff },
	1456	+ { 0x11005f, 0x1ff },
	1457	+ { 0x11015f, 0x1ff },
	1458	+ { 0x11105f, 0x1ff },
	1459	+ { 0x11115f, 0x1ff },
	1460	+ { 0x11205f, 0x1ff },
	1461	+ { 0x11215f, 0x1ff },
	1462	+ { 0x11305f, 0x1ff },
	1463	+ { 0x11315f, 0x1ff },
	1464	+ { 0x21005f, 0x1ff },
	1465	+ { 0x21015f, 0x1ff },
	1466	+ { 0x21105f, 0x1ff },
	1467	+ { 0x21115f, 0x1ff },
	1468	+ { 0x21205f, 0x1ff },
	1469	+ { 0x21215f, 0x1ff },
	1470	+ { 0x21305f, 0x1ff },
	1471	+ { 0x21315f, 0x1ff },
	1472	+ { 0x55, 0x1ff },
	1473	+ { 0x1055, 0x1ff },
	1474	+ { 0x2055, 0x1ff },
	1475	+ { 0x3055, 0x1ff },
	1476	+ { 0x4055, 0x1ff },
	1477	+ { 0x5055, 0x1ff },
	1478	+ { 0x6055, 0x1ff },
	1479	+ { 0x7055, 0x1ff },
	1480	+ { 0x8055, 0x1ff },
	1481	+ { 0x9055, 0x1ff },
	1482	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	1483	+ { 0x200c5, 0xa },
	1484	+#else
	1485	+ { 0x200c5, 0x18 },
	1486	+#endif
	1487	+ { 0x1200c5, 0x7 },
	1488	+ { 0x2200c5, 0x7 },
	1489	+ { 0x2002e, 0x2 },
	1490	+ { 0x12002e, 0x2 },
	1491	+ { 0x22002e, 0x2 },
	1492	+ { 0x90204, 0x0 },
	1493	+ { 0x190204, 0x0 },
	1494	+ { 0x290204, 0x0 },
	1495	+ { 0x20024, 0x1e3 },
	1496	+ { 0x2003a, 0x2 },
	1497	+ { 0x120024, 0x1e3 },
	1498	+ { 0x2003a, 0x2 },
	1499	+ { 0x220024, 0x1e3 },
	1500	+ { 0x2003a, 0x2 },
	1501	+ { 0x20056, 0x3 },
	1502	+ { 0x120056, 0x3 },
	1503	+ { 0x220056, 0x3 },
	1504	+ { 0x1004d, 0xe00 },
	1505	+ { 0x1014d, 0xe00 },
	1506	+ { 0x1104d, 0xe00 },
	1507	+ { 0x1114d, 0xe00 },
	1508	+ { 0x1204d, 0xe00 },
	1509	+ { 0x1214d, 0xe00 },
	1510	+ { 0x1304d, 0xe00 },
	1511	+ { 0x1314d, 0xe00 },
	1512	+ { 0x11004d, 0xe00 },
	1513	+ { 0x11014d, 0xe00 },
	1514	+ { 0x11104d, 0xe00 },
	1515	+ { 0x11114d, 0xe00 },
	1516	+ { 0x11204d, 0xe00 },
	1517	+ { 0x11214d, 0xe00 },
	1518	+ { 0x11304d, 0xe00 },
	1519	+ { 0x11314d, 0xe00 },
	1520	+ { 0x21004d, 0xe00 },
	1521	+ { 0x21014d, 0xe00 },
	1522	+ { 0x21104d, 0xe00 },
	1523	+ { 0x21114d, 0xe00 },
	1524	+ { 0x21204d, 0xe00 },
	1525	+ { 0x21214d, 0xe00 },
	1526	+ { 0x21304d, 0xe00 },
	1527	+ { 0x21314d, 0xe00 },
	1528	+ { 0x10049, 0xeba },
	1529	+ { 0x10149, 0xeba },
	1530	+ { 0x11049, 0xeba },
	1531	+ { 0x11149, 0xeba },
	1532	+ { 0x12049, 0xeba },
	1533	+ { 0x12149, 0xeba },
	1534	+ { 0x13049, 0xeba },
	1535	+ { 0x13149, 0xeba },
	1536	+ { 0x110049, 0xeba },
	1537	+ { 0x110149, 0xeba },
	1538	+ { 0x111049, 0xeba },
	1539	+ { 0x111149, 0xeba },
	1540	+ { 0x112049, 0xeba },
	1541	+ { 0x112149, 0xeba },
	1542	+ { 0x113049, 0xeba },
	1543	+ { 0x113149, 0xeba },
	1544	+ { 0x210049, 0xeba },
	1545	+ { 0x210149, 0xeba },
	1546	+ { 0x211049, 0xeba },
	1547	+ { 0x211149, 0xeba },
	1548	+ { 0x212049, 0xeba },
	1549	+ { 0x212149, 0xeba },
	1550	+ { 0x213049, 0xeba },
	1551	+ { 0x213149, 0xeba },
	1552	+ { 0x43, 0x63 },
	1553	+ { 0x1043, 0x63 },
	1554	+ { 0x2043, 0x63 },
	1555	+ { 0x3043, 0x63 },
	1556	+ { 0x4043, 0x63 },
	1557	+ { 0x5043, 0x63 },
	1558	+ { 0x6043, 0x63 },
	1559	+ { 0x7043, 0x63 },
	1560	+ { 0x8043, 0x63 },
	1561	+ { 0x9043, 0x63 },
	1562	+ { 0x20018, 0x3 },
	1563	+ { 0x20075, 0x4 },
	1564	+ { 0x20050, 0x0 },
	1565	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	1566	+ { 0x20008, 0x258 },
	1567	+#else
	1568	+ { 0x20008, 0x3e8 },
	1569	+#endif
	1570	+ { 0x120008, 0x64 },
	1571	+ { 0x220008, 0x19 },
	1572	+ { 0x20088, 0x9 },
	1573	+ { 0x200b2, 0x104 },
	1574	+ { 0x10043, 0x5a1 },
	1575	+ { 0x10143, 0x5a1 },
	1576	+ { 0x11043, 0x5a1 },
	1577	+ { 0x11143, 0x5a1 },
	1578	+ { 0x12043, 0x5a1 },
	1579	+ { 0x12143, 0x5a1 },
	1580	+ { 0x13043, 0x5a1 },
	1581	+ { 0x13143, 0x5a1 },
	1582	+ { 0x1200b2, 0x104 },
	1583	+ { 0x110043, 0x5a1 },
	1584	+ { 0x110143, 0x5a1 },
	1585	+ { 0x111043, 0x5a1 },
	1586	+ { 0x111143, 0x5a1 },
	1587	+ { 0x112043, 0x5a1 },
	1588	+ { 0x112143, 0x5a1 },
	1589	+ { 0x113043, 0x5a1 },
	1590	+ { 0x113143, 0x5a1 },
	1591	+ { 0x2200b2, 0x104 },
	1592	+ { 0x210043, 0x5a1 },
	1593	+ { 0x210143, 0x5a1 },
	1594	+ { 0x211043, 0x5a1 },
	1595	+ { 0x211143, 0x5a1 },
	1596	+ { 0x212043, 0x5a1 },
	1597	+ { 0x212143, 0x5a1 },
	1598	+ { 0x213043, 0x5a1 },
	1599	+ { 0x213143, 0x5a1 },
	1600	+ { 0x200fa, 0x1 },
	1601	+ { 0x1200fa, 0x1 },
	1602	+ { 0x2200fa, 0x1 },
	1603	+ { 0x20019, 0x1 },
	1604	+ { 0x120019, 0x1 },
	1605	+ { 0x220019, 0x1 },
	1606	+ { 0x200f0, 0x660 },
	1607	+ { 0x200f1, 0x0 },
	1608	+ { 0x200f2, 0x4444 },
	1609	+ { 0x200f3, 0x8888 },
	1610	+ { 0x200f4, 0x5665 },
	1611	+ { 0x200f5, 0x0 },
	1612	+ { 0x200f6, 0x0 },
	1613	+ { 0x200f7, 0xf000 },
	1614	+ { 0x20025, 0x0 },
	1615	+ { 0x2002d, 0x0 },
	1616	+ { 0x12002d, 0x0 },
	1617	+ { 0x22002d, 0x0 },
	1618	+ { 0x2007d, 0x212 },
	1619	+ { 0x12007d, 0x212 },
	1620	+ { 0x22007d, 0x212 },
	1621	+ { 0x2007c, 0x61 },
	1622	+ { 0x12007c, 0x61 },
	1623	+ { 0x22007c, 0x61 },
	1624	+ { 0x1004a, 0x500 },
	1625	+ { 0x1104a, 0x500 },
	1626	+ { 0x1204a, 0x500 },
	1627	+ { 0x1304a, 0x500 },
	1628	+ { 0x2002c, 0x0 },
	1629	+};
	1630	+
	1631	+/* ddr phy trained csr */
	1632	+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
	1633	+ { 0x200b2, 0x0 },
	1634	+ { 0x1200b2, 0x0 },
	1635	+ { 0x2200b2, 0x0 },
	1636	+ { 0x200cb, 0x0 },
	1637	+ { 0x10043, 0x0 },
	1638	+ { 0x110043, 0x0 },
	1639	+ { 0x210043, 0x0 },
	1640	+ { 0x10143, 0x0 },
	1641	+ { 0x110143, 0x0 },
	1642	+ { 0x210143, 0x0 },
	1643	+ { 0x11043, 0x0 },
	1644	+ { 0x111043, 0x0 },
	1645	+ { 0x211043, 0x0 },
	1646	+ { 0x11143, 0x0 },
	1647	+ { 0x111143, 0x0 },
	1648	+ { 0x211143, 0x0 },
	1649	+ { 0x12043, 0x0 },
	1650	+ { 0x112043, 0x0 },
	1651	+ { 0x212043, 0x0 },
	1652	+ { 0x12143, 0x0 },
	1653	+ { 0x112143, 0x0 },
	1654	+ { 0x212143, 0x0 },
	1655	+ { 0x13043, 0x0 },
	1656	+ { 0x113043, 0x0 },
	1657	+ { 0x213043, 0x0 },
	1658	+ { 0x13143, 0x0 },
	1659	+ { 0x113143, 0x0 },
	1660	+ { 0x213143, 0x0 },
	1661	+ { 0x80, 0x0 },
	1662	+ { 0x100080, 0x0 },
	1663	+ { 0x200080, 0x0 },
	1664	+ { 0x1080, 0x0 },
	1665	+ { 0x101080, 0x0 },
	1666	+ { 0x201080, 0x0 },
	1667	+ { 0x2080, 0x0 },
	1668	+ { 0x102080, 0x0 },
	1669	+ { 0x202080, 0x0 },
	1670	+ { 0x3080, 0x0 },
	1671	+ { 0x103080, 0x0 },
	1672	+ { 0x203080, 0x0 },
	1673	+ { 0x4080, 0x0 },
	1674	+ { 0x104080, 0x0 },
	1675	+ { 0x204080, 0x0 },
	1676	+ { 0x5080, 0x0 },
	1677	+ { 0x105080, 0x0 },
	1678	+ { 0x205080, 0x0 },
	1679	+ { 0x6080, 0x0 },
	1680	+ { 0x106080, 0x0 },
	1681	+ { 0x206080, 0x0 },
	1682	+ { 0x7080, 0x0 },
	1683	+ { 0x107080, 0x0 },
	1684	+ { 0x207080, 0x0 },
	1685	+ { 0x8080, 0x0 },
	1686	+ { 0x108080, 0x0 },
	1687	+ { 0x208080, 0x0 },
	1688	+ { 0x9080, 0x0 },
	1689	+ { 0x109080, 0x0 },
	1690	+ { 0x209080, 0x0 },
	1691	+ { 0x10080, 0x0 },
	1692	+ { 0x110080, 0x0 },
	1693	+ { 0x210080, 0x0 },
	1694	+ { 0x10180, 0x0 },
	1695	+ { 0x110180, 0x0 },
	1696	+ { 0x210180, 0x0 },
	1697	+ { 0x11080, 0x0 },
	1698	+ { 0x111080, 0x0 },
	1699	+ { 0x211080, 0x0 },
	1700	+ { 0x11180, 0x0 },
	1701	+ { 0x111180, 0x0 },
	1702	+ { 0x211180, 0x0 },
	1703	+ { 0x12080, 0x0 },
	1704	+ { 0x112080, 0x0 },
	1705	+ { 0x212080, 0x0 },
	1706	+ { 0x12180, 0x0 },
	1707	+ { 0x112180, 0x0 },
	1708	+ { 0x212180, 0x0 },
	1709	+ { 0x13080, 0x0 },
	1710	+ { 0x113080, 0x0 },
	1711	+ { 0x213080, 0x0 },
	1712	+ { 0x13180, 0x0 },
	1713	+ { 0x113180, 0x0 },
	1714	+ { 0x213180, 0x0 },
	1715	+ { 0x10081, 0x0 },
	1716	+ { 0x110081, 0x0 },
	1717	+ { 0x210081, 0x0 },
	1718	+ { 0x10181, 0x0 },
	1719	+ { 0x110181, 0x0 },
	1720	+ { 0x210181, 0x0 },
	1721	+ { 0x11081, 0x0 },
	1722	+ { 0x111081, 0x0 },
	1723	+ { 0x211081, 0x0 },
	1724	+ { 0x11181, 0x0 },
	1725	+ { 0x111181, 0x0 },
	1726	+ { 0x211181, 0x0 },
	1727	+ { 0x12081, 0x0 },
	1728	+ { 0x112081, 0x0 },
	1729	+ { 0x212081, 0x0 },
	1730	+ { 0x12181, 0x0 },
	1731	+ { 0x112181, 0x0 },
	1732	+ { 0x212181, 0x0 },
	1733	+ { 0x13081, 0x0 },
	1734	+ { 0x113081, 0x0 },
	1735	+ { 0x213081, 0x0 },
	1736	+ { 0x13181, 0x0 },
	1737	+ { 0x113181, 0x0 },
	1738	+ { 0x213181, 0x0 },
	1739	+ { 0x100d0, 0x0 },
	1740	+ { 0x1100d0, 0x0 },
	1741	+ { 0x2100d0, 0x0 },
	1742	+ { 0x101d0, 0x0 },
	1743	+ { 0x1101d0, 0x0 },
	1744	+ { 0x2101d0, 0x0 },
	1745	+ { 0x110d0, 0x0 },
	1746	+ { 0x1110d0, 0x0 },
	1747	+ { 0x2110d0, 0x0 },
	1748	+ { 0x111d0, 0x0 },
	1749	+ { 0x1111d0, 0x0 },
	1750	+ { 0x2111d0, 0x0 },
	1751	+ { 0x120d0, 0x0 },
	1752	+ { 0x1120d0, 0x0 },
	1753	+ { 0x2120d0, 0x0 },
	1754	+ { 0x121d0, 0x0 },
	1755	+ { 0x1121d0, 0x0 },
	1756	+ { 0x2121d0, 0x0 },
	1757	+ { 0x130d0, 0x0 },
	1758	+ { 0x1130d0, 0x0 },
	1759	+ { 0x2130d0, 0x0 },
	1760	+ { 0x131d0, 0x0 },
	1761	+ { 0x1131d0, 0x0 },
	1762	+ { 0x2131d0, 0x0 },
	1763	+ { 0x100d1, 0x0 },
	1764	+ { 0x1100d1, 0x0 },
	1765	+ { 0x2100d1, 0x0 },
	1766	+ { 0x101d1, 0x0 },
	1767	+ { 0x1101d1, 0x0 },
	1768	+ { 0x2101d1, 0x0 },
	1769	+ { 0x110d1, 0x0 },
	1770	+ { 0x1110d1, 0x0 },
	1771	+ { 0x2110d1, 0x0 },
	1772	+ { 0x111d1, 0x0 },
	1773	+ { 0x1111d1, 0x0 },
	1774	+ { 0x2111d1, 0x0 },
	1775	+ { 0x120d1, 0x0 },
	1776	+ { 0x1120d1, 0x0 },
	1777	+ { 0x2120d1, 0x0 },
	1778	+ { 0x121d1, 0x0 },
	1779	+ { 0x1121d1, 0x0 },
	1780	+ { 0x2121d1, 0x0 },
	1781	+ { 0x130d1, 0x0 },
	1782	+ { 0x1130d1, 0x0 },
	1783	+ { 0x2130d1, 0x0 },
	1784	+ { 0x131d1, 0x0 },
	1785	+ { 0x1131d1, 0x0 },
	1786	+ { 0x2131d1, 0x0 },
	1787	+ { 0x10068, 0x0 },
	1788	+ { 0x10168, 0x0 },
	1789	+ { 0x10268, 0x0 },
	1790	+ { 0x10368, 0x0 },
	1791	+ { 0x10468, 0x0 },
	1792	+ { 0x10568, 0x0 },
	1793	+ { 0x10668, 0x0 },
	1794	+ { 0x10768, 0x0 },
	1795	+ { 0x10868, 0x0 },
	1796	+ { 0x11068, 0x0 },
	1797	+ { 0x11168, 0x0 },
	1798	+ { 0x11268, 0x0 },
	1799	+ { 0x11368, 0x0 },
	1800	+ { 0x11468, 0x0 },
	1801	+ { 0x11568, 0x0 },
	1802	+ { 0x11668, 0x0 },
	1803	+ { 0x11768, 0x0 },
	1804	+ { 0x11868, 0x0 },
	1805	+ { 0x12068, 0x0 },
	1806	+ { 0x12168, 0x0 },
	1807	+ { 0x12268, 0x0 },
	1808	+ { 0x12368, 0x0 },
	1809	+ { 0x12468, 0x0 },
	1810	+ { 0x12568, 0x0 },
	1811	+ { 0x12668, 0x0 },
	1812	+ { 0x12768, 0x0 },
	1813	+ { 0x12868, 0x0 },
	1814	+ { 0x13068, 0x0 },
	1815	+ { 0x13168, 0x0 },
	1816	+ { 0x13268, 0x0 },
	1817	+ { 0x13368, 0x0 },
	1818	+ { 0x13468, 0x0 },
	1819	+ { 0x13568, 0x0 },
	1820	+ { 0x13668, 0x0 },
	1821	+ { 0x13768, 0x0 },
	1822	+ { 0x13868, 0x0 },
	1823	+ { 0x10069, 0x0 },
	1824	+ { 0x10169, 0x0 },
	1825	+ { 0x10269, 0x0 },
	1826	+ { 0x10369, 0x0 },
	1827	+ { 0x10469, 0x0 },
	1828	+ { 0x10569, 0x0 },
	1829	+ { 0x10669, 0x0 },
	1830	+ { 0x10769, 0x0 },
	1831	+ { 0x10869, 0x0 },
	1832	+ { 0x11069, 0x0 },
	1833	+ { 0x11169, 0x0 },
	1834	+ { 0x11269, 0x0 },
	1835	+ { 0x11369, 0x0 },
	1836	+ { 0x11469, 0x0 },
	1837	+ { 0x11569, 0x0 },
	1838	+ { 0x11669, 0x0 },
	1839	+ { 0x11769, 0x0 },
	1840	+ { 0x11869, 0x0 },
	1841	+ { 0x12069, 0x0 },
	1842	+ { 0x12169, 0x0 },
	1843	+ { 0x12269, 0x0 },
	1844	+ { 0x12369, 0x0 },
	1845	+ { 0x12469, 0x0 },
	1846	+ { 0x12569, 0x0 },
	1847	+ { 0x12669, 0x0 },
	1848	+ { 0x12769, 0x0 },
	1849	+ { 0x12869, 0x0 },
	1850	+ { 0x13069, 0x0 },
	1851	+ { 0x13169, 0x0 },
	1852	+ { 0x13269, 0x0 },
	1853	+ { 0x13369, 0x0 },
	1854	+ { 0x13469, 0x0 },
	1855	+ { 0x13569, 0x0 },
	1856	+ { 0x13669, 0x0 },
	1857	+ { 0x13769, 0x0 },
	1858	+ { 0x13869, 0x0 },
	1859	+ { 0x1008c, 0x0 },
	1860	+ { 0x11008c, 0x0 },
	1861	+ { 0x21008c, 0x0 },
	1862	+ { 0x1018c, 0x0 },
	1863	+ { 0x11018c, 0x0 },
	1864	+ { 0x21018c, 0x0 },
	1865	+ { 0x1108c, 0x0 },
	1866	+ { 0x11108c, 0x0 },
	1867	+ { 0x21108c, 0x0 },
	1868	+ { 0x1118c, 0x0 },
	1869	+ { 0x11118c, 0x0 },
	1870	+ { 0x21118c, 0x0 },
	1871	+ { 0x1208c, 0x0 },
	1872	+ { 0x11208c, 0x0 },
	1873	+ { 0x21208c, 0x0 },
	1874	+ { 0x1218c, 0x0 },
	1875	+ { 0x11218c, 0x0 },
	1876	+ { 0x21218c, 0x0 },
	1877	+ { 0x1308c, 0x0 },
	1878	+ { 0x11308c, 0x0 },
	1879	+ { 0x21308c, 0x0 },
	1880	+ { 0x1318c, 0x0 },
	1881	+ { 0x11318c, 0x0 },
	1882	+ { 0x21318c, 0x0 },
	1883	+ { 0x1008d, 0x0 },
	1884	+ { 0x11008d, 0x0 },
	1885	+ { 0x21008d, 0x0 },
	1886	+ { 0x1018d, 0x0 },
	1887	+ { 0x11018d, 0x0 },
	1888	+ { 0x21018d, 0x0 },
	1889	+ { 0x1108d, 0x0 },
	1890	+ { 0x11108d, 0x0 },
	1891	+ { 0x21108d, 0x0 },
	1892	+ { 0x1118d, 0x0 },
	1893	+ { 0x11118d, 0x0 },
	1894	+ { 0x21118d, 0x0 },
	1895	+ { 0x1208d, 0x0 },
	1896	+ { 0x11208d, 0x0 },
	1897	+ { 0x21208d, 0x0 },
	1898	+ { 0x1218d, 0x0 },
	1899	+ { 0x11218d, 0x0 },
	1900	+ { 0x21218d, 0x0 },
	1901	+ { 0x1308d, 0x0 },
	1902	+ { 0x11308d, 0x0 },
	1903	+ { 0x21308d, 0x0 },
	1904	+ { 0x1318d, 0x0 },
	1905	+ { 0x11318d, 0x0 },
	1906	+ { 0x21318d, 0x0 },
	1907	+ { 0x100c0, 0x0 },
	1908	+ { 0x1100c0, 0x0 },
	1909	+ { 0x2100c0, 0x0 },
	1910	+ { 0x101c0, 0x0 },
	1911	+ { 0x1101c0, 0x0 },
	1912	+ { 0x2101c0, 0x0 },
	1913	+ { 0x102c0, 0x0 },
	1914	+ { 0x1102c0, 0x0 },
	1915	+ { 0x2102c0, 0x0 },
	1916	+ { 0x103c0, 0x0 },
	1917	+ { 0x1103c0, 0x0 },
	1918	+ { 0x2103c0, 0x0 },
	1919	+ { 0x104c0, 0x0 },
	1920	+ { 0x1104c0, 0x0 },
	1921	+ { 0x2104c0, 0x0 },
	1922	+ { 0x105c0, 0x0 },
	1923	+ { 0x1105c0, 0x0 },
	1924	+ { 0x2105c0, 0x0 },
	1925	+ { 0x106c0, 0x0 },
	1926	+ { 0x1106c0, 0x0 },
	1927	+ { 0x2106c0, 0x0 },
	1928	+ { 0x107c0, 0x0 },
	1929	+ { 0x1107c0, 0x0 },
	1930	+ { 0x2107c0, 0x0 },
	1931	+ { 0x108c0, 0x0 },
	1932	+ { 0x1108c0, 0x0 },
	1933	+ { 0x2108c0, 0x0 },
	1934	+ { 0x110c0, 0x0 },
	1935	+ { 0x1110c0, 0x0 },
	1936	+ { 0x2110c0, 0x0 },
	1937	+ { 0x111c0, 0x0 },
	1938	+ { 0x1111c0, 0x0 },
	1939	+ { 0x2111c0, 0x0 },
	1940	+ { 0x112c0, 0x0 },
	1941	+ { 0x1112c0, 0x0 },
	1942	+ { 0x2112c0, 0x0 },
	1943	+ { 0x113c0, 0x0 },
	1944	+ { 0x1113c0, 0x0 },
	1945	+ { 0x2113c0, 0x0 },
	1946	+ { 0x114c0, 0x0 },
	1947	+ { 0x1114c0, 0x0 },
	1948	+ { 0x2114c0, 0x0 },
	1949	+ { 0x115c0, 0x0 },
	1950	+ { 0x1115c0, 0x0 },
	1951	+ { 0x2115c0, 0x0 },
	1952	+ { 0x116c0, 0x0 },
	1953	+ { 0x1116c0, 0x0 },
	1954	+ { 0x2116c0, 0x0 },
	1955	+ { 0x117c0, 0x0 },
	1956	+ { 0x1117c0, 0x0 },
	1957	+ { 0x2117c0, 0x0 },
	1958	+ { 0x118c0, 0x0 },
	1959	+ { 0x1118c0, 0x0 },
	1960	+ { 0x2118c0, 0x0 },
	1961	+ { 0x120c0, 0x0 },
	1962	+ { 0x1120c0, 0x0 },
	1963	+ { 0x2120c0, 0x0 },
	1964	+ { 0x121c0, 0x0 },
	1965	+ { 0x1121c0, 0x0 },
	1966	+ { 0x2121c0, 0x0 },
	1967	+ { 0x122c0, 0x0 },
	1968	+ { 0x1122c0, 0x0 },
	1969	+ { 0x2122c0, 0x0 },
	1970	+ { 0x123c0, 0x0 },
	1971	+ { 0x1123c0, 0x0 },
	1972	+ { 0x2123c0, 0x0 },
	1973	+ { 0x124c0, 0x0 },
	1974	+ { 0x1124c0, 0x0 },
	1975	+ { 0x2124c0, 0x0 },
	1976	+ { 0x125c0, 0x0 },
	1977	+ { 0x1125c0, 0x0 },
	1978	+ { 0x2125c0, 0x0 },
	1979	+ { 0x126c0, 0x0 },
	1980	+ { 0x1126c0, 0x0 },
	1981	+ { 0x2126c0, 0x0 },
	1982	+ { 0x127c0, 0x0 },
	1983	+ { 0x1127c0, 0x0 },
	1984	+ { 0x2127c0, 0x0 },
	1985	+ { 0x128c0, 0x0 },
	1986	+ { 0x1128c0, 0x0 },
	1987	+ { 0x2128c0, 0x0 },
	1988	+ { 0x130c0, 0x0 },
	1989	+ { 0x1130c0, 0x0 },
	1990	+ { 0x2130c0, 0x0 },
	1991	+ { 0x131c0, 0x0 },
	1992	+ { 0x1131c0, 0x0 },
	1993	+ { 0x2131c0, 0x0 },
	1994	+ { 0x132c0, 0x0 },
	1995	+ { 0x1132c0, 0x0 },
	1996	+ { 0x2132c0, 0x0 },
	1997	+ { 0x133c0, 0x0 },
	1998	+ { 0x1133c0, 0x0 },
	1999	+ { 0x2133c0, 0x0 },
	2000	+ { 0x134c0, 0x0 },
	2001	+ { 0x1134c0, 0x0 },
	2002	+ { 0x2134c0, 0x0 },
	2003	+ { 0x135c0, 0x0 },
	2004	+ { 0x1135c0, 0x0 },
	2005	+ { 0x2135c0, 0x0 },
	2006	+ { 0x136c0, 0x0 },
	2007	+ { 0x1136c0, 0x0 },
	2008	+ { 0x2136c0, 0x0 },
	2009	+ { 0x137c0, 0x0 },
	2010	+ { 0x1137c0, 0x0 },
	2011	+ { 0x2137c0, 0x0 },
	2012	+ { 0x138c0, 0x0 },
	2013	+ { 0x1138c0, 0x0 },
	2014	+ { 0x2138c0, 0x0 },
	2015	+ { 0x100c1, 0x0 },
	2016	+ { 0x1100c1, 0x0 },
	2017	+ { 0x2100c1, 0x0 },
	2018	+ { 0x101c1, 0x0 },
	2019	+ { 0x1101c1, 0x0 },
	2020	+ { 0x2101c1, 0x0 },
	2021	+ { 0x102c1, 0x0 },
	2022	+ { 0x1102c1, 0x0 },
	2023	+ { 0x2102c1, 0x0 },
	2024	+ { 0x103c1, 0x0 },
	2025	+ { 0x1103c1, 0x0 },
	2026	+ { 0x2103c1, 0x0 },
	2027	+ { 0x104c1, 0x0 },
	2028	+ { 0x1104c1, 0x0 },
	2029	+ { 0x2104c1, 0x0 },
	2030	+ { 0x105c1, 0x0 },
	2031	+ { 0x1105c1, 0x0 },
	2032	+ { 0x2105c1, 0x0 },
	2033	+ { 0x106c1, 0x0 },
	2034	+ { 0x1106c1, 0x0 },
	2035	+ { 0x2106c1, 0x0 },
	2036	+ { 0x107c1, 0x0 },
	2037	+ { 0x1107c1, 0x0 },
	2038	+ { 0x2107c1, 0x0 },
	2039	+ { 0x108c1, 0x0 },
	2040	+ { 0x1108c1, 0x0 },
	2041	+ { 0x2108c1, 0x0 },
	2042	+ { 0x110c1, 0x0 },
	2043	+ { 0x1110c1, 0x0 },
	2044	+ { 0x2110c1, 0x0 },
	2045	+ { 0x111c1, 0x0 },
	2046	+ { 0x1111c1, 0x0 },
	2047	+ { 0x2111c1, 0x0 },
	2048	+ { 0x112c1, 0x0 },
	2049	+ { 0x1112c1, 0x0 },
	2050	+ { 0x2112c1, 0x0 },
	2051	+ { 0x113c1, 0x0 },
	2052	+ { 0x1113c1, 0x0 },
	2053	+ { 0x2113c1, 0x0 },
	2054	+ { 0x114c1, 0x0 },
	2055	+ { 0x1114c1, 0x0 },
	2056	+ { 0x2114c1, 0x0 },
	2057	+ { 0x115c1, 0x0 },
	2058	+ { 0x1115c1, 0x0 },
	2059	+ { 0x2115c1, 0x0 },
	2060	+ { 0x116c1, 0x0 },
	2061	+ { 0x1116c1, 0x0 },
	2062	+ { 0x2116c1, 0x0 },
	2063	+ { 0x117c1, 0x0 },
	2064	+ { 0x1117c1, 0x0 },
	2065	+ { 0x2117c1, 0x0 },
	2066	+ { 0x118c1, 0x0 },
	2067	+ { 0x1118c1, 0x0 },
	2068	+ { 0x2118c1, 0x0 },
	2069	+ { 0x120c1, 0x0 },
	2070	+ { 0x1120c1, 0x0 },
	2071	+ { 0x2120c1, 0x0 },
	2072	+ { 0x121c1, 0x0 },
	2073	+ { 0x1121c1, 0x0 },
	2074	+ { 0x2121c1, 0x0 },
	2075	+ { 0x122c1, 0x0 },
	2076	+ { 0x1122c1, 0x0 },
	2077	+ { 0x2122c1, 0x0 },
	2078	+ { 0x123c1, 0x0 },
	2079	+ { 0x1123c1, 0x0 },
	2080	+ { 0x2123c1, 0x0 },
	2081	+ { 0x124c1, 0x0 },
	2082	+ { 0x1124c1, 0x0 },
	2083	+ { 0x2124c1, 0x0 },
	2084	+ { 0x125c1, 0x0 },
	2085	+ { 0x1125c1, 0x0 },
	2086	+ { 0x2125c1, 0x0 },
	2087	+ { 0x126c1, 0x0 },
	2088	+ { 0x1126c1, 0x0 },
	2089	+ { 0x2126c1, 0x0 },
	2090	+ { 0x127c1, 0x0 },
	2091	+ { 0x1127c1, 0x0 },
	2092	+ { 0x2127c1, 0x0 },
	2093	+ { 0x128c1, 0x0 },
	2094	+ { 0x1128c1, 0x0 },
	2095	+ { 0x2128c1, 0x0 },
	2096	+ { 0x130c1, 0x0 },
	2097	+ { 0x1130c1, 0x0 },
	2098	+ { 0x2130c1, 0x0 },
	2099	+ { 0x131c1, 0x0 },
	2100	+ { 0x1131c1, 0x0 },
	2101	+ { 0x2131c1, 0x0 },
	2102	+ { 0x132c1, 0x0 },
	2103	+ { 0x1132c1, 0x0 },
	2104	+ { 0x2132c1, 0x0 },
	2105	+ { 0x133c1, 0x0 },
	2106	+ { 0x1133c1, 0x0 },
	2107	+ { 0x2133c1, 0x0 },
	2108	+ { 0x134c1, 0x0 },
	2109	+ { 0x1134c1, 0x0 },
	2110	+ { 0x2134c1, 0x0 },
	2111	+ { 0x135c1, 0x0 },
	2112	+ { 0x1135c1, 0x0 },
	2113	+ { 0x2135c1, 0x0 },
	2114	+ { 0x136c1, 0x0 },
	2115	+ { 0x1136c1, 0x0 },
	2116	+ { 0x2136c1, 0x0 },
	2117	+ { 0x137c1, 0x0 },
	2118	+ { 0x1137c1, 0x0 },
	2119	+ { 0x2137c1, 0x0 },
	2120	+ { 0x138c1, 0x0 },
	2121	+ { 0x1138c1, 0x0 },
	2122	+ { 0x2138c1, 0x0 },
	2123	+ { 0x10020, 0x0 },
	2124	+ { 0x110020, 0x0 },
	2125	+ { 0x210020, 0x0 },
	2126	+ { 0x11020, 0x0 },
	2127	+ { 0x111020, 0x0 },
	2128	+ { 0x211020, 0x0 },
	2129	+ { 0x12020, 0x0 },
	2130	+ { 0x112020, 0x0 },
	2131	+ { 0x212020, 0x0 },
	2132	+ { 0x13020, 0x0 },
	2133	+ { 0x113020, 0x0 },
	2134	+ { 0x213020, 0x0 },
	2135	+ { 0x20072, 0x0 },
	2136	+ { 0x20073, 0x0 },
	2137	+ { 0x20074, 0x0 },
	2138	+ { 0x100aa, 0x0 },
	2139	+ { 0x110aa, 0x0 },
	2140	+ { 0x120aa, 0x0 },
	2141	+ { 0x130aa, 0x0 },
	2142	+ { 0x20010, 0x0 },
	2143	+ { 0x120010, 0x0 },
	2144	+ { 0x220010, 0x0 },
	2145	+ { 0x20011, 0x0 },
	2146	+ { 0x120011, 0x0 },
	2147	+ { 0x220011, 0x0 },
	2148	+ { 0x100ae, 0x0 },
	2149	+ { 0x1100ae, 0x0 },
	2150	+ { 0x2100ae, 0x0 },
	2151	+ { 0x100af, 0x0 },
	2152	+ { 0x1100af, 0x0 },
	2153	+ { 0x2100af, 0x0 },
	2154	+ { 0x110ae, 0x0 },
	2155	+ { 0x1110ae, 0x0 },
	2156	+ { 0x2110ae, 0x0 },
	2157	+ { 0x110af, 0x0 },
	2158	+ { 0x1110af, 0x0 },
	2159	+ { 0x2110af, 0x0 },
	2160	+ { 0x120ae, 0x0 },
	2161	+ { 0x1120ae, 0x0 },
	2162	+ { 0x2120ae, 0x0 },
	2163	+ { 0x120af, 0x0 },
	2164	+ { 0x1120af, 0x0 },
	2165	+ { 0x2120af, 0x0 },
	2166	+ { 0x130ae, 0x0 },
	2167	+ { 0x1130ae, 0x0 },
	2168	+ { 0x2130ae, 0x0 },
	2169	+ { 0x130af, 0x0 },
	2170	+ { 0x1130af, 0x0 },
	2171	+ { 0x2130af, 0x0 },
	2172	+ { 0x20020, 0x0 },
	2173	+ { 0x120020, 0x0 },
	2174	+ { 0x220020, 0x0 },
	2175	+ { 0x100a0, 0x0 },
	2176	+ { 0x100a1, 0x0 },
	2177	+ { 0x100a2, 0x0 },
	2178	+ { 0x100a3, 0x0 },
	2179	+ { 0x100a4, 0x0 },
	2180	+ { 0x100a5, 0x0 },
	2181	+ { 0x100a6, 0x0 },
	2182	+ { 0x100a7, 0x0 },
	2183	+ { 0x110a0, 0x0 },
	2184	+ { 0x110a1, 0x0 },
	2185	+ { 0x110a2, 0x0 },
	2186	+ { 0x110a3, 0x0 },
	2187	+ { 0x110a4, 0x0 },
	2188	+ { 0x110a5, 0x0 },
	2189	+ { 0x110a6, 0x0 },
	2190	+ { 0x110a7, 0x0 },
	2191	+ { 0x120a0, 0x0 },
	2192	+ { 0x120a1, 0x0 },
	2193	+ { 0x120a2, 0x0 },
	2194	+ { 0x120a3, 0x0 },
	2195	+ { 0x120a4, 0x0 },
	2196	+ { 0x120a5, 0x0 },
	2197	+ { 0x120a6, 0x0 },
	2198	+ { 0x120a7, 0x0 },
	2199	+ { 0x130a0, 0x0 },
	2200	+ { 0x130a1, 0x0 },
	2201	+ { 0x130a2, 0x0 },
	2202	+ { 0x130a3, 0x0 },
	2203	+ { 0x130a4, 0x0 },
	2204	+ { 0x130a5, 0x0 },
	2205	+ { 0x130a6, 0x0 },
	2206	+ { 0x130a7, 0x0 },
	2207	+ { 0x2007c, 0x0 },
	2208	+ { 0x12007c, 0x0 },
	2209	+ { 0x22007c, 0x0 },
	2210	+ { 0x2007d, 0x0 },
	2211	+ { 0x12007d, 0x0 },
	2212	+ { 0x22007d, 0x0 },
	2213	+ { 0x400fd, 0x0 },
	2214	+ { 0x400c0, 0x0 },
	2215	+ { 0x90201, 0x0 },
	2216	+ { 0x190201, 0x0 },
	2217	+ { 0x290201, 0x0 },
	2218	+ { 0x90202, 0x0 },
	2219	+ { 0x190202, 0x0 },
	2220	+ { 0x290202, 0x0 },
	2221	+ { 0x90203, 0x0 },
	2222	+ { 0x190203, 0x0 },
	2223	+ { 0x290203, 0x0 },
	2224	+ { 0x90204, 0x0 },
	2225	+ { 0x190204, 0x0 },
	2226	+ { 0x290204, 0x0 },
	2227	+ { 0x90205, 0x0 },
	2228	+ { 0x190205, 0x0 },
	2229	+ { 0x290205, 0x0 },
	2230	+ { 0x90206, 0x0 },
	2231	+ { 0x190206, 0x0 },
	2232	+ { 0x290206, 0x0 },
	2233	+ { 0x90207, 0x0 },
	2234	+ { 0x190207, 0x0 },
	2235	+ { 0x290207, 0x0 },
	2236	+ { 0x90208, 0x0 },
	2237	+ { 0x190208, 0x0 },
	2238	+ { 0x290208, 0x0 },
	2239	+ { 0x10062, 0x0 },
	2240	+ { 0x10162, 0x0 },
	2241	+ { 0x10262, 0x0 },
	2242	+ { 0x10362, 0x0 },
	2243	+ { 0x10462, 0x0 },
	2244	+ { 0x10562, 0x0 },
	2245	+ { 0x10662, 0x0 },
	2246	+ { 0x10762, 0x0 },
	2247	+ { 0x10862, 0x0 },
	2248	+ { 0x11062, 0x0 },
	2249	+ { 0x11162, 0x0 },
	2250	+ { 0x11262, 0x0 },
	2251	+ { 0x11362, 0x0 },
	2252	+ { 0x11462, 0x0 },
	2253	+ { 0x11562, 0x0 },
	2254	+ { 0x11662, 0x0 },
	2255	+ { 0x11762, 0x0 },
	2256	+ { 0x11862, 0x0 },
	2257	+ { 0x12062, 0x0 },
	2258	+ { 0x12162, 0x0 },
	2259	+ { 0x12262, 0x0 },
	2260	+ { 0x12362, 0x0 },
	2261	+ { 0x12462, 0x0 },
	2262	+ { 0x12562, 0x0 },
	2263	+ { 0x12662, 0x0 },
	2264	+ { 0x12762, 0x0 },
	2265	+ { 0x12862, 0x0 },
	2266	+ { 0x13062, 0x0 },
	2267	+ { 0x13162, 0x0 },
	2268	+ { 0x13262, 0x0 },
	2269	+ { 0x13362, 0x0 },
	2270	+ { 0x13462, 0x0 },
	2271	+ { 0x13562, 0x0 },
	2272	+ { 0x13662, 0x0 },
	2273	+ { 0x13762, 0x0 },
	2274	+ { 0x13862, 0x0 },
	2275	+ { 0x20077, 0x0 },
	2276	+ { 0x10001, 0x0 },
	2277	+ { 0x11001, 0x0 },
	2278	+ { 0x12001, 0x0 },
	2279	+ { 0x13001, 0x0 },
	2280	+ { 0x10040, 0x0 },
	2281	+ { 0x10140, 0x0 },
	2282	+ { 0x10240, 0x0 },
	2283	+ { 0x10340, 0x0 },
	2284	+ { 0x10440, 0x0 },
	2285	+ { 0x10540, 0x0 },
	2286	+ { 0x10640, 0x0 },
	2287	+ { 0x10740, 0x0 },
	2288	+ { 0x10840, 0x0 },
	2289	+ { 0x10030, 0x0 },
	2290	+ { 0x10130, 0x0 },
	2291	+ { 0x10230, 0x0 },
	2292	+ { 0x10330, 0x0 },
	2293	+ { 0x10430, 0x0 },
	2294	+ { 0x10530, 0x0 },
	2295	+ { 0x10630, 0x0 },
	2296	+ { 0x10730, 0x0 },
	2297	+ { 0x10830, 0x0 },
	2298	+ { 0x11040, 0x0 },
	2299	+ { 0x11140, 0x0 },
	2300	+ { 0x11240, 0x0 },
	2301	+ { 0x11340, 0x0 },
	2302	+ { 0x11440, 0x0 },
	2303	+ { 0x11540, 0x0 },
	2304	+ { 0x11640, 0x0 },
	2305	+ { 0x11740, 0x0 },
	2306	+ { 0x11840, 0x0 },
	2307	+ { 0x11030, 0x0 },
	2308	+ { 0x11130, 0x0 },
	2309	+ { 0x11230, 0x0 },
	2310	+ { 0x11330, 0x0 },
	2311	+ { 0x11430, 0x0 },
	2312	+ { 0x11530, 0x0 },
	2313	+ { 0x11630, 0x0 },
	2314	+ { 0x11730, 0x0 },
	2315	+ { 0x11830, 0x0 },
	2316	+ { 0x12040, 0x0 },
	2317	+ { 0x12140, 0x0 },
	2318	+ { 0x12240, 0x0 },
	2319	+ { 0x12340, 0x0 },
	2320	+ { 0x12440, 0x0 },
	2321	+ { 0x12540, 0x0 },
	2322	+ { 0x12640, 0x0 },
	2323	+ { 0x12740, 0x0 },
	2324	+ { 0x12840, 0x0 },
	2325	+ { 0x12030, 0x0 },
	2326	+ { 0x12130, 0x0 },
	2327	+ { 0x12230, 0x0 },
	2328	+ { 0x12330, 0x0 },
	2329	+ { 0x12430, 0x0 },
	2330	+ { 0x12530, 0x0 },
	2331	+ { 0x12630, 0x0 },
	2332	+ { 0x12730, 0x0 },
	2333	+ { 0x12830, 0x0 },
	2334	+ { 0x13040, 0x0 },
	2335	+ { 0x13140, 0x0 },
	2336	+ { 0x13240, 0x0 },
	2337	+ { 0x13340, 0x0 },
	2338	+ { 0x13440, 0x0 },
	2339	+ { 0x13540, 0x0 },
	2340	+ { 0x13640, 0x0 },
	2341	+ { 0x13740, 0x0 },
	2342	+ { 0x13840, 0x0 },
	2343	+ { 0x13030, 0x0 },
	2344	+ { 0x13130, 0x0 },
	2345	+ { 0x13230, 0x0 },
	2346	+ { 0x13330, 0x0 },
	2347	+ { 0x13430, 0x0 },
	2348	+ { 0x13530, 0x0 },
	2349	+ { 0x13630, 0x0 },
	2350	+ { 0x13730, 0x0 },
	2351	+ { 0x13830, 0x0 },
	2352	+};
	2353	+
	2354	+/* P0 message block paremeter for training firmware */
	2355	+struct dram_cfg_param ddr_fsp0_cfg[] = {
	2356	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	2357	+ { 0xd0000, 0x0 },
	2358	+ { 0x54003, 0x960 },
	2359	+ { 0x54004, 0x2 },
	2360	+ { 0x54005, 0x2228 },
	2361	+ { 0x54006, 0x14 },
	2362	+ { 0x54008, 0x131f },
	2363	+ { 0x54009, 0xc8 },
	2364	+ { 0x5400b, 0x2 },
	2365	+ { 0x5400f, 0x100 },
	2366	+ { 0x54012, 0x310 },
	2367	+ { 0x54019, 0x24c4 },
	2368	+ { 0x5401a, 0x33 },
	2369	+ { 0x5401b, 0x4866 },
	2370	+ { 0x5401c, 0x4800 },
	2371	+ { 0x5401e, 0x16 },
	2372	+ { 0x5401f, 0x24c4 },
	2373	+ { 0x54020, 0x33 },
	2374	+ { 0x54021, 0x4866 },
	2375	+ { 0x54022, 0x4800 },
	2376	+ { 0x54024, 0x16 },
	2377	+ { 0x5402b, 0x1000 },
	2378	+ { 0x5402c, 0x3 },
	2379	+ { 0x54032, 0xc400 },
	2380	+ { 0x54033, 0x3324 },
	2381	+ { 0x54034, 0x6600 },
	2382	+ { 0x54035, 0x48 },
	2383	+ { 0x54036, 0x48 },
	2384	+ { 0x54037, 0x1600 },
	2385	+ { 0x54038, 0xc400 },
	2386	+ { 0x54039, 0x3324 },
	2387	+#else
	2388	+ { 0xd0000, 0x0 },
	2389	+ { 0x54003, 0xfa0 },
	2390	+ { 0x54004, 0x2 },
	2391	+ { 0x54005, 0x2228 },
	2392	+ { 0x54006, 0x14 },
	2393	+ { 0x54008, 0x131f },
	2394	+ { 0x54009, 0xc8 },
	2395	+ { 0x5400b, 0x2 },
	2396	+ { 0x5400f, 0x100 },
	2397	+ { 0x54012, 0x310 },
	2398	+ { 0x54019, 0x3ff4 },
	2399	+ { 0x5401a, 0x33 },
	2400	+ { 0x5401b, 0x4866 },
	2401	+ { 0x5401c, 0x4800 },
	2402	+ { 0x5401e, 0x16 },
	2403	+ { 0x5401f, 0x3ff4 },
	2404	+ { 0x54020, 0x33 },
	2405	+ { 0x54021, 0x4866 },
	2406	+ { 0x54022, 0x4800 },
	2407	+ { 0x54024, 0x16 },
	2408	+ { 0x5402b, 0x1000 },
	2409	+ { 0x5402c, 0x3 },
	2410	+ { 0x54032, 0xf400 },
	2411	+ { 0x54033, 0x333f },
	2412	+ { 0x54034, 0x6600 },
	2413	+ { 0x54035, 0x48 },
	2414	+ { 0x54036, 0x48 },
	2415	+ { 0x54037, 0x1600 },
	2416	+ { 0x54038, 0xf400 },
	2417	+ { 0x54039, 0x333f },
	2418	+#endif
	2419	+ { 0x5403a, 0x6600 },
	2420	+ { 0x5403b, 0x48 },
	2421	+ { 0x5403c, 0x48 },
	2422	+ { 0x5403d, 0x1600 },
	2423	+ { 0xd0000, 0x1 },
	2424	+};
	2425	+
	2426	+/* P1 message block paremeter for training firmware */
	2427	+struct dram_cfg_param ddr_fsp1_cfg[] = {
	2428	+ { 0xd0000, 0x0 },
	2429	+ { 0x54002, 0x101 },
	2430	+ { 0x54003, 0x190 },
	2431	+ { 0x54004, 0x2 },
	2432	+ { 0x54005, 0x2228 },
	2433	+ { 0x54006, 0x14 },
	2434	+ { 0x54008, 0x121f },
	2435	+ { 0x54009, 0xc8 },
	2436	+ { 0x5400b, 0x2 },
	2437	+ { 0x5400f, 0x100 },
	2438	+ { 0x54012, 0x310 },
	2439	+ { 0x54019, 0x84 },
	2440	+ { 0x5401a, 0x33 },
	2441	+ { 0x5401b, 0x4866 },
	2442	+ { 0x5401c, 0x4800 },
	2443	+ { 0x5401e, 0x16 },
	2444	+ { 0x5401f, 0x84 },
	2445	+ { 0x54020, 0x33 },
	2446	+ { 0x54021, 0x4866 },
	2447	+ { 0x54022, 0x4800 },
	2448	+ { 0x54024, 0x16 },
	2449	+ { 0x5402b, 0x1000 },
	2450	+ { 0x5402c, 0x3 },
	2451	+ { 0x54032, 0x8400 },
	2452	+ { 0x54033, 0x3300 },
	2453	+ { 0x54034, 0x6600 },
	2454	+ { 0x54035, 0x48 },
	2455	+ { 0x54036, 0x48 },
	2456	+ { 0x54037, 0x1600 },
	2457	+ { 0x54038, 0x8400 },
	2458	+ { 0x54039, 0x3300 },
	2459	+ { 0x5403a, 0x6600 },
	2460	+ { 0x5403b, 0x48 },
	2461	+ { 0x5403c, 0x48 },
	2462	+ { 0x5403d, 0x1600 },
	2463	+ { 0xd0000, 0x1 },
	2464	+};
	2465	+
	2466	+/* P2 message block paremeter for training firmware */
	2467	+struct dram_cfg_param ddr_fsp2_cfg[] = {
	2468	+ { 0xd0000, 0x0 },
	2469	+ { 0x54002, 0x102 },
	2470	+ { 0x54003, 0x64 },
	2471	+ { 0x54004, 0x2 },
	2472	+ { 0x54005, 0x2228 },
	2473	+ { 0x54006, 0x14 },
	2474	+ { 0x54008, 0x121f },
	2475	+ { 0x54009, 0xc8 },
	2476	+ { 0x5400b, 0x2 },
	2477	+ { 0x5400f, 0x100 },
	2478	+ { 0x54012, 0x310 },
	2479	+ { 0x54019, 0x84 },
	2480	+ { 0x5401a, 0x33 },
	2481	+ { 0x5401b, 0x4866 },
	2482	+ { 0x5401c, 0x4800 },
	2483	+ { 0x5401e, 0x16 },
	2484	+ { 0x5401f, 0x84 },
	2485	+ { 0x54020, 0x33 },
	2486	+ { 0x54021, 0x4866 },
	2487	+ { 0x54022, 0x4800 },
	2488	+ { 0x54024, 0x16 },
	2489	+ { 0x5402b, 0x1000 },
	2490	+ { 0x5402c, 0x3 },
	2491	+ { 0x54032, 0x8400 },
	2492	+ { 0x54033, 0x3300 },
	2493	+ { 0x54034, 0x6600 },
	2494	+ { 0x54035, 0x48 },
	2495	+ { 0x54036, 0x48 },
	2496	+ { 0x54037, 0x1600 },
	2497	+ { 0x54038, 0x8400 },
	2498	+ { 0x54039, 0x3300 },
	2499	+ { 0x5403a, 0x6600 },
	2500	+ { 0x5403b, 0x48 },
	2501	+ { 0x5403c, 0x48 },
	2502	+ { 0x5403d, 0x1600 },
	2503	+ { 0xd0000, 0x1 },
	2504	+};
	2505	+
	2506	+/* P0 2D message block paremeter for training firmware */
	2507	+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
	2508	+ { 0xd0000, 0x0 },
	2509	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	2510	+ { 0x54003, 0x960 },
	2511	+ { 0x54004, 0x2 },
	2512	+ { 0x54005, 0x2228 },
	2513	+ { 0x54006, 0x14 },
	2514	+ { 0x54008, 0x61 },
	2515	+ { 0x54009, 0xc8 },
	2516	+ { 0x5400b, 0x2 },
	2517	+ { 0x5400f, 0x100 },
	2518	+ { 0x54010, 0x1f7f },
	2519	+ { 0x54012, 0x310 },
	2520	+ { 0x54019, 0x24c4 },
	2521	+ { 0x5401a, 0x33 },
	2522	+ { 0x5401b, 0x4866 },
	2523	+ { 0x5401c, 0x4800 },
	2524	+ { 0x5401e, 0x16 },
	2525	+ { 0x5401f, 0x24c4 },
	2526	+ { 0x54020, 0x33 },
	2527	+ { 0x54021, 0x4866 },
	2528	+ { 0x54022, 0x4800 },
	2529	+ { 0x54024, 0x16 },
	2530	+ { 0x5402b, 0x1000 },
	2531	+ { 0x5402c, 0x3 },
	2532	+ { 0x54032, 0xc400 },
	2533	+ { 0x54033, 0x3324 },
	2534	+ { 0x54034, 0x6600 },
	2535	+ { 0x54035, 0x48 },
	2536	+ { 0x54036, 0x48 },
	2537	+ { 0x54037, 0x1600 },
	2538	+ { 0x54038, 0xc400 },
	2539	+ { 0x54039, 0x3324 },
	2540	+#else
	2541	+ { 0x54003, 0xfa0 },
	2542	+ { 0x54004, 0x2 },
	2543	+ { 0x54005, 0x2228 },
	2544	+ { 0x54006, 0x14 },
	2545	+ { 0x54008, 0x61 },
	2546	+ { 0x54009, 0xc8 },
	2547	+ { 0x5400b, 0x2 },
	2548	+ { 0x5400f, 0x100 },
	2549	+ { 0x54010, 0x1f7f },
	2550	+ { 0x54012, 0x310 },
	2551	+ { 0x54019, 0x3ff4 },
	2552	+ { 0x5401a, 0x33 },
	2553	+ { 0x5401b, 0x4866 },
	2554	+ { 0x5401c, 0x4800 },
	2555	+ { 0x5401e, 0x16 },
	2556	+ { 0x5401f, 0x3ff4 },
	2557	+ { 0x54020, 0x33 },
	2558	+ { 0x54021, 0x4866 },
	2559	+ { 0x54022, 0x4800 },
	2560	+ { 0x54024, 0x16 },
	2561	+ { 0x5402b, 0x1000 },
	2562	+ { 0x5402c, 0x3 },
	2563	+ { 0x54032, 0xf400 },
	2564	+ { 0x54033, 0x333f },
	2565	+ { 0x54034, 0x6600 },
	2566	+ { 0x54035, 0x48 },
	2567	+ { 0x54036, 0x48 },
	2568	+ { 0x54037, 0x1600 },
	2569	+ { 0x54038, 0xf400 },
	2570	+ { 0x54039, 0x333f },
	2571	+#endif
	2572	+ { 0x5403a, 0x6600 },
	2573	+ { 0x5403b, 0x48 },
	2574	+ { 0x5403c, 0x48 },
	2575	+ { 0x5403d, 0x1600 },
	2576	+ { 0xd0000, 0x1 },
	2577	+};
	2578	+
	2579	+/* DRAM PHY init engine image */
	2580	+struct dram_cfg_param ddr_phy_pie[] = {
	2581	+ { 0xd0000, 0x0 },
	2582	+ { 0x90000, 0x10 },
	2583	+ { 0x90001, 0x400 },
	2584	+ { 0x90002, 0x10e },
	2585	+ { 0x90003, 0x0 },
	2586	+ { 0x90004, 0x0 },
	2587	+ { 0x90005, 0x8 },
	2588	+ { 0x90029, 0xb },
	2589	+ { 0x9002a, 0x480 },
	2590	+ { 0x9002b, 0x109 },
	2591	+ { 0x9002c, 0x8 },
	2592	+ { 0x9002d, 0x448 },
	2593	+ { 0x9002e, 0x139 },
	2594	+ { 0x9002f, 0x8 },
	2595	+ { 0x90030, 0x478 },
	2596	+ { 0x90031, 0x109 },
	2597	+ { 0x90032, 0x0 },
	2598	+ { 0x90033, 0xe8 },
	2599	+ { 0x90034, 0x109 },
	2600	+ { 0x90035, 0x2 },
	2601	+ { 0x90036, 0x10 },
	2602	+ { 0x90037, 0x139 },
	2603	+ { 0x90038, 0xb },
	2604	+ { 0x90039, 0x7c0 },
	2605	+ { 0x9003a, 0x139 },
	2606	+ { 0x9003b, 0x44 },
	2607	+ { 0x9003c, 0x633 },
	2608	+ { 0x9003d, 0x159 },
	2609	+ { 0x9003e, 0x14f },
	2610	+ { 0x9003f, 0x630 },
	2611	+ { 0x90040, 0x159 },
	2612	+ { 0x90041, 0x47 },
	2613	+ { 0x90042, 0x633 },
	2614	+ { 0x90043, 0x149 },
	2615	+ { 0x90044, 0x4f },
	2616	+ { 0x90045, 0x633 },
	2617	+ { 0x90046, 0x179 },
	2618	+ { 0x90047, 0x8 },
	2619	+ { 0x90048, 0xe0 },
	2620	+ { 0x90049, 0x109 },
	2621	+ { 0x9004a, 0x0 },
	2622	+ { 0x9004b, 0x7c8 },
	2623	+ { 0x9004c, 0x109 },
	2624	+ { 0x9004d, 0x0 },
	2625	+ { 0x9004e, 0x1 },
	2626	+ { 0x9004f, 0x8 },
	2627	+ { 0x90050, 0x0 },
	2628	+ { 0x90051, 0x45a },
	2629	+ { 0x90052, 0x9 },
	2630	+ { 0x90053, 0x0 },
	2631	+ { 0x90054, 0x448 },
	2632	+ { 0x90055, 0x109 },
	2633	+ { 0x90056, 0x40 },
	2634	+ { 0x90057, 0x633 },
	2635	+ { 0x90058, 0x179 },
	2636	+ { 0x90059, 0x1 },
	2637	+ { 0x9005a, 0x618 },
	2638	+ { 0x9005b, 0x109 },
	2639	+ { 0x9005c, 0x40c0 },
	2640	+ { 0x9005d, 0x633 },
	2641	+ { 0x9005e, 0x149 },
	2642	+ { 0x9005f, 0x8 },
	2643	+ { 0x90060, 0x4 },
	2644	+ { 0x90061, 0x48 },
	2645	+ { 0x90062, 0x4040 },
	2646	+ { 0x90063, 0x633 },
	2647	+ { 0x90064, 0x149 },
	2648	+ { 0x90065, 0x0 },
	2649	+ { 0x90066, 0x4 },
	2650	+ { 0x90067, 0x48 },
	2651	+ { 0x90068, 0x40 },
	2652	+ { 0x90069, 0x633 },
	2653	+ { 0x9006a, 0x149 },
	2654	+ { 0x9006b, 0x10 },
	2655	+ { 0x9006c, 0x4 },
	2656	+ { 0x9006d, 0x18 },
	2657	+ { 0x9006e, 0x0 },
	2658	+ { 0x9006f, 0x4 },
	2659	+ { 0x90070, 0x78 },
	2660	+ { 0x90071, 0x549 },
	2661	+ { 0x90072, 0x633 },
	2662	+ { 0x90073, 0x159 },
	2663	+ { 0x90074, 0xd49 },
	2664	+ { 0x90075, 0x633 },
	2665	+ { 0x90076, 0x159 },
	2666	+ { 0x90077, 0x94a },
	2667	+ { 0x90078, 0x633 },
	2668	+ { 0x90079, 0x159 },
	2669	+ { 0x9007a, 0x441 },
	2670	+ { 0x9007b, 0x633 },
	2671	+ { 0x9007c, 0x149 },
	2672	+ { 0x9007d, 0x42 },
	2673	+ { 0x9007e, 0x633 },
	2674	+ { 0x9007f, 0x149 },
	2675	+ { 0x90080, 0x1 },
	2676	+ { 0x90081, 0x633 },
	2677	+ { 0x90082, 0x149 },
	2678	+ { 0x90083, 0x0 },
	2679	+ { 0x90084, 0xe0 },
	2680	+ { 0x90085, 0x109 },
	2681	+ { 0x90086, 0xa },
	2682	+ { 0x90087, 0x10 },
	2683	+ { 0x90088, 0x109 },
	2684	+ { 0x90089, 0x9 },
	2685	+ { 0x9008a, 0x3c0 },
	2686	+ { 0x9008b, 0x149 },
	2687	+ { 0x9008c, 0x9 },
	2688	+ { 0x9008d, 0x3c0 },
	2689	+ { 0x9008e, 0x159 },
	2690	+ { 0x9008f, 0x18 },
	2691	+ { 0x90090, 0x10 },
	2692	+ { 0x90091, 0x109 },
	2693	+ { 0x90092, 0x0 },
	2694	+ { 0x90093, 0x3c0 },
	2695	+ { 0x90094, 0x109 },
	2696	+ { 0x90095, 0x18 },
	2697	+ { 0x90096, 0x4 },
	2698	+ { 0x90097, 0x48 },
	2699	+ { 0x90098, 0x18 },
	2700	+ { 0x90099, 0x4 },
	2701	+ { 0x9009a, 0x58 },
	2702	+ { 0x9009b, 0xb },
	2703	+ { 0x9009c, 0x10 },
	2704	+ { 0x9009d, 0x109 },
	2705	+ { 0x9009e, 0x1 },
	2706	+ { 0x9009f, 0x10 },
	2707	+ { 0x900a0, 0x109 },
	2708	+ { 0x900a1, 0x5 },
	2709	+ { 0x900a2, 0x7c0 },
	2710	+ { 0x900a3, 0x109 },
	2711	+ { 0x40000, 0x811 },
	2712	+ { 0x40020, 0x880 },
	2713	+ { 0x40040, 0x0 },
	2714	+ { 0x40060, 0x0 },
	2715	+ { 0x40001, 0x4008 },
	2716	+ { 0x40021, 0x83 },
	2717	+ { 0x40041, 0x4f },
	2718	+ { 0x40061, 0x0 },
	2719	+ { 0x40002, 0x4040 },
	2720	+ { 0x40022, 0x83 },
	2721	+ { 0x40042, 0x51 },
	2722	+ { 0x40062, 0x0 },
	2723	+ { 0x40003, 0x811 },
	2724	+ { 0x40023, 0x880 },
	2725	+ { 0x40043, 0x0 },
	2726	+ { 0x40063, 0x0 },
	2727	+ { 0x40004, 0x720 },
	2728	+ { 0x40024, 0xf },
	2729	+ { 0x40044, 0x1740 },
	2730	+ { 0x40064, 0x0 },
	2731	+ { 0x40005, 0x16 },
	2732	+ { 0x40025, 0x83 },
	2733	+ { 0x40045, 0x4b },
	2734	+ { 0x40065, 0x0 },
	2735	+ { 0x40006, 0x716 },
	2736	+ { 0x40026, 0xf },
	2737	+ { 0x40046, 0x2001 },
	2738	+ { 0x40066, 0x0 },
	2739	+ { 0x40007, 0x716 },
	2740	+ { 0x40027, 0xf },
	2741	+ { 0x40047, 0x2800 },
	2742	+ { 0x40067, 0x0 },
	2743	+ { 0x40008, 0x716 },
	2744	+ { 0x40028, 0xf },
	2745	+ { 0x40048, 0xf00 },
	2746	+ { 0x40068, 0x0 },
	2747	+ { 0x40009, 0x720 },
	2748	+ { 0x40029, 0xf },
	2749	+ { 0x40049, 0x1400 },
	2750	+ { 0x40069, 0x0 },
	2751	+ { 0x4000a, 0xe08 },
	2752	+ { 0x4002a, 0xc15 },
	2753	+ { 0x4004a, 0x0 },
	2754	+ { 0x4006a, 0x0 },
	2755	+ { 0x4000b, 0x625 },
	2756	+ { 0x4002b, 0x15 },
	2757	+ { 0x4004b, 0x0 },
	2758	+ { 0x4006b, 0x0 },
	2759	+ { 0x4000c, 0x4028 },
	2760	+ { 0x4002c, 0x80 },
	2761	+ { 0x4004c, 0x0 },
	2762	+ { 0x4006c, 0x0 },
	2763	+ { 0x4000d, 0xe08 },
	2764	+ { 0x4002d, 0xc1a },
	2765	+ { 0x4004d, 0x0 },
	2766	+ { 0x4006d, 0x0 },
	2767	+ { 0x4000e, 0x625 },
	2768	+ { 0x4002e, 0x1a },
	2769	+ { 0x4004e, 0x0 },
	2770	+ { 0x4006e, 0x0 },
	2771	+ { 0x4000f, 0x4040 },
	2772	+ { 0x4002f, 0x80 },
	2773	+ { 0x4004f, 0x0 },
	2774	+ { 0x4006f, 0x0 },
	2775	+ { 0x40010, 0x2604 },
	2776	+ { 0x40030, 0x15 },
	2777	+ { 0x40050, 0x0 },
	2778	+ { 0x40070, 0x0 },
	2779	+ { 0x40011, 0x708 },
	2780	+ { 0x40031, 0x5 },
	2781	+ { 0x40051, 0x0 },
	2782	+ { 0x40071, 0x2002 },
	2783	+ { 0x40012, 0x8 },
	2784	+ { 0x40032, 0x80 },
	2785	+ { 0x40052, 0x0 },
	2786	+ { 0x40072, 0x0 },
	2787	+ { 0x40013, 0x2604 },
	2788	+ { 0x40033, 0x1a },
	2789	+ { 0x40053, 0x0 },
	2790	+ { 0x40073, 0x0 },
	2791	+ { 0x40014, 0x708 },
	2792	+ { 0x40034, 0xa },
	2793	+ { 0x40054, 0x0 },
	2794	+ { 0x40074, 0x2002 },
	2795	+ { 0x40015, 0x4040 },
	2796	+ { 0x40035, 0x80 },
	2797	+ { 0x40055, 0x0 },
	2798	+ { 0x40075, 0x0 },
	2799	+ { 0x40016, 0x60a },
	2800	+ { 0x40036, 0x15 },
	2801	+ { 0x40056, 0x1200 },
	2802	+ { 0x40076, 0x0 },
	2803	+ { 0x40017, 0x61a },
	2804	+ { 0x40037, 0x15 },
	2805	+ { 0x40057, 0x1300 },
	2806	+ { 0x40077, 0x0 },
	2807	+ { 0x40018, 0x60a },
	2808	+ { 0x40038, 0x1a },
	2809	+ { 0x40058, 0x1200 },
	2810	+ { 0x40078, 0x0 },
	2811	+ { 0x40019, 0x642 },
	2812	+ { 0x40039, 0x1a },
	2813	+ { 0x40059, 0x1300 },
	2814	+ { 0x40079, 0x0 },
	2815	+ { 0x4001a, 0x4808 },
	2816	+ { 0x4003a, 0x880 },
	2817	+ { 0x4005a, 0x0 },
	2818	+ { 0x4007a, 0x0 },
	2819	+ { 0x900a4, 0x0 },
	2820	+ { 0x900a5, 0x790 },
	2821	+ { 0x900a6, 0x11a },
	2822	+ { 0x900a7, 0x8 },
	2823	+ { 0x900a8, 0x7aa },
	2824	+ { 0x900a9, 0x2a },
	2825	+ { 0x900aa, 0x10 },
	2826	+ { 0x900ab, 0x7b2 },
	2827	+ { 0x900ac, 0x2a },
	2828	+ { 0x900ad, 0x0 },
	2829	+ { 0x900ae, 0x7c8 },
	2830	+ { 0x900af, 0x109 },
	2831	+ { 0x900b0, 0x10 },
	2832	+ { 0x900b1, 0x10 },
	2833	+ { 0x900b2, 0x109 },
	2834	+ { 0x900b3, 0x10 },
	2835	+ { 0x900b4, 0x2a8 },
	2836	+ { 0x900b5, 0x129 },
	2837	+ { 0x900b6, 0x8 },
	2838	+ { 0x900b7, 0x370 },
	2839	+ { 0x900b8, 0x129 },
	2840	+ { 0x900b9, 0xa },
	2841	+ { 0x900ba, 0x3c8 },
	2842	+ { 0x900bb, 0x1a9 },
	2843	+ { 0x900bc, 0xc },
	2844	+ { 0x900bd, 0x408 },
	2845	+ { 0x900be, 0x199 },
	2846	+ { 0x900bf, 0x14 },
	2847	+ { 0x900c0, 0x790 },
	2848	+ { 0x900c1, 0x11a },
	2849	+ { 0x900c2, 0x8 },
	2850	+ { 0x900c3, 0x4 },
	2851	+ { 0x900c4, 0x18 },
	2852	+ { 0x900c5, 0xe },
	2853	+ { 0x900c6, 0x408 },
	2854	+ { 0x900c7, 0x199 },
	2855	+ { 0x900c8, 0x8 },
	2856	+ { 0x900c9, 0x8568 },
	2857	+ { 0x900ca, 0x108 },
	2858	+ { 0x900cb, 0x18 },
	2859	+ { 0x900cc, 0x790 },
	2860	+ { 0x900cd, 0x16a },
	2861	+ { 0x900ce, 0x8 },
	2862	+ { 0x900cf, 0x1d8 },
	2863	+ { 0x900d0, 0x169 },
	2864	+ { 0x900d1, 0x10 },
	2865	+ { 0x900d2, 0x8558 },
	2866	+ { 0x900d3, 0x168 },
	2867	+ { 0x900d4, 0x70 },
	2868	+ { 0x900d5, 0x788 },
	2869	+ { 0x900d6, 0x16a },
	2870	+ { 0x900d7, 0x1ff8 },
	2871	+ { 0x900d8, 0x85a8 },
	2872	+ { 0x900d9, 0x1e8 },
	2873	+ { 0x900da, 0x50 },
	2874	+ { 0x900db, 0x798 },
	2875	+ { 0x900dc, 0x16a },
	2876	+ { 0x900dd, 0x60 },
	2877	+ { 0x900de, 0x7a0 },
	2878	+ { 0x900df, 0x16a },
	2879	+ { 0x900e0, 0x8 },
	2880	+ { 0x900e1, 0x8310 },
	2881	+ { 0x900e2, 0x168 },
	2882	+ { 0x900e3, 0x8 },
	2883	+ { 0x900e4, 0xa310 },
	2884	+ { 0x900e5, 0x168 },
	2885	+ { 0x900e6, 0xa },
	2886	+ { 0x900e7, 0x408 },
	2887	+ { 0x900e8, 0x169 },
	2888	+ { 0x900e9, 0x6e },
	2889	+ { 0x900ea, 0x0 },
	2890	+ { 0x900eb, 0x68 },
	2891	+ { 0x900ec, 0x0 },
	2892	+ { 0x900ed, 0x408 },
	2893	+ { 0x900ee, 0x169 },
	2894	+ { 0x900ef, 0x0 },
	2895	+ { 0x900f0, 0x8310 },
	2896	+ { 0x900f1, 0x168 },
	2897	+ { 0x900f2, 0x0 },
	2898	+ { 0x900f3, 0xa310 },
	2899	+ { 0x900f4, 0x168 },
	2900	+ { 0x900f5, 0x1ff8 },
	2901	+ { 0x900f6, 0x85a8 },
	2902	+ { 0x900f7, 0x1e8 },
	2903	+ { 0x900f8, 0x68 },
	2904	+ { 0x900f9, 0x798 },
	2905	+ { 0x900fa, 0x16a },
	2906	+ { 0x900fb, 0x78 },
	2907	+ { 0x900fc, 0x7a0 },
	2908	+ { 0x900fd, 0x16a },
	2909	+ { 0x900fe, 0x68 },
	2910	+ { 0x900ff, 0x790 },
	2911	+ { 0x90100, 0x16a },
	2912	+ { 0x90101, 0x8 },
	2913	+ { 0x90102, 0x8b10 },
	2914	+ { 0x90103, 0x168 },
	2915	+ { 0x90104, 0x8 },
	2916	+ { 0x90105, 0xab10 },
	2917	+ { 0x90106, 0x168 },
	2918	+ { 0x90107, 0xa },
	2919	+ { 0x90108, 0x408 },
	2920	+ { 0x90109, 0x169 },
	2921	+ { 0x9010a, 0x58 },
	2922	+ { 0x9010b, 0x0 },
	2923	+ { 0x9010c, 0x68 },
	2924	+ { 0x9010d, 0x0 },
	2925	+ { 0x9010e, 0x408 },
	2926	+ { 0x9010f, 0x169 },
	2927	+ { 0x90110, 0x0 },
	2928	+ { 0x90111, 0x8b10 },
	2929	+ { 0x90112, 0x168 },
	2930	+ { 0x90113, 0x1 },
	2931	+ { 0x90114, 0xab10 },
	2932	+ { 0x90115, 0x168 },
	2933	+ { 0x90116, 0x0 },
	2934	+ { 0x90117, 0x1d8 },
	2935	+ { 0x90118, 0x169 },
	2936	+ { 0x90119, 0x80 },
	2937	+ { 0x9011a, 0x790 },
	2938	+ { 0x9011b, 0x16a },
	2939	+ { 0x9011c, 0x18 },
	2940	+ { 0x9011d, 0x7aa },
	2941	+ { 0x9011e, 0x6a },
	2942	+ { 0x9011f, 0xa },
	2943	+ { 0x90120, 0x0 },
	2944	+ { 0x90121, 0x1e9 },
	2945	+ { 0x90122, 0x8 },
	2946	+ { 0x90123, 0x8080 },
	2947	+ { 0x90124, 0x108 },
	2948	+ { 0x90125, 0xf },
	2949	+ { 0x90126, 0x408 },
	2950	+ { 0x90127, 0x169 },
	2951	+ { 0x90128, 0xc },
	2952	+ { 0x90129, 0x0 },
	2953	+ { 0x9012a, 0x68 },
	2954	+ { 0x9012b, 0x9 },
	2955	+ { 0x9012c, 0x0 },
	2956	+ { 0x9012d, 0x1a9 },
	2957	+ { 0x9012e, 0x0 },
	2958	+ { 0x9012f, 0x408 },
	2959	+ { 0x90130, 0x169 },
	2960	+ { 0x90131, 0x0 },
	2961	+ { 0x90132, 0x8080 },
	2962	+ { 0x90133, 0x108 },
	2963	+ { 0x90134, 0x8 },
	2964	+ { 0x90135, 0x7aa },
	2965	+ { 0x90136, 0x6a },
	2966	+ { 0x90137, 0x0 },
	2967	+ { 0x90138, 0x8568 },
	2968	+ { 0x90139, 0x108 },
	2969	+ { 0x9013a, 0xb7 },
	2970	+ { 0x9013b, 0x790 },
	2971	+ { 0x9013c, 0x16a },
	2972	+ { 0x9013d, 0x1f },
	2973	+ { 0x9013e, 0x0 },
	2974	+ { 0x9013f, 0x68 },
	2975	+ { 0x90140, 0x8 },
	2976	+ { 0x90141, 0x8558 },
	2977	+ { 0x90142, 0x168 },
	2978	+ { 0x90143, 0xf },
	2979	+ { 0x90144, 0x408 },
	2980	+ { 0x90145, 0x169 },
	2981	+ { 0x90146, 0xd },
	2982	+ { 0x90147, 0x0 },
	2983	+ { 0x90148, 0x68 },
	2984	+ { 0x90149, 0x0 },
	2985	+ { 0x9014a, 0x408 },
	2986	+ { 0x9014b, 0x169 },
	2987	+ { 0x9014c, 0x0 },
	2988	+ { 0x9014d, 0x8558 },
	2989	+ { 0x9014e, 0x168 },
	2990	+ { 0x9014f, 0x8 },
	2991	+ { 0x90150, 0x3c8 },
	2992	+ { 0x90151, 0x1a9 },
	2993	+ { 0x90152, 0x3 },
	2994	+ { 0x90153, 0x370 },
	2995	+ { 0x90154, 0x129 },
	2996	+ { 0x90155, 0x20 },
	2997	+ { 0x90156, 0x2aa },
	2998	+ { 0x90157, 0x9 },
	2999	+ { 0x90158, 0x8 },
	3000	+ { 0x90159, 0xe8 },
	3001	+ { 0x9015a, 0x109 },
	3002	+ { 0x9015b, 0x0 },
	3003	+ { 0x9015c, 0x8140 },
	3004	+ { 0x9015d, 0x10c },
	3005	+ { 0x9015e, 0x10 },
	3006	+ { 0x9015f, 0x8138 },
	3007	+ { 0x90160, 0x104 },
	3008	+ { 0x90161, 0x8 },
	3009	+ { 0x90162, 0x448 },
	3010	+ { 0x90163, 0x109 },
	3011	+ { 0x90164, 0xf },
	3012	+ { 0x90165, 0x7c0 },
	3013	+ { 0x90166, 0x109 },
	3014	+ { 0x90167, 0x0 },
	3015	+ { 0x90168, 0xe8 },
	3016	+ { 0x90169, 0x109 },
	3017	+ { 0x9016a, 0x47 },
	3018	+ { 0x9016b, 0x630 },
	3019	+ { 0x9016c, 0x109 },
	3020	+ { 0x9016d, 0x8 },
	3021	+ { 0x9016e, 0x618 },
	3022	+ { 0x9016f, 0x109 },
	3023	+ { 0x90170, 0x8 },
	3024	+ { 0x90171, 0xe0 },
	3025	+ { 0x90172, 0x109 },
	3026	+ { 0x90173, 0x0 },
	3027	+ { 0x90174, 0x7c8 },
	3028	+ { 0x90175, 0x109 },
	3029	+ { 0x90176, 0x8 },
	3030	+ { 0x90177, 0x8140 },
	3031	+ { 0x90178, 0x10c },
	3032	+ { 0x90179, 0x0 },
	3033	+ { 0x9017a, 0x478 },
	3034	+ { 0x9017b, 0x109 },
	3035	+ { 0x9017c, 0x0 },
	3036	+ { 0x9017d, 0x1 },
	3037	+ { 0x9017e, 0x8 },
	3038	+ { 0x9017f, 0x8 },
	3039	+ { 0x90180, 0x4 },
	3040	+ { 0x90181, 0x0 },
	3041	+ { 0x90006, 0x8 },
	3042	+ { 0x90007, 0x7c8 },
	3043	+ { 0x90008, 0x109 },
	3044	+ { 0x90009, 0x0 },
	3045	+ { 0x9000a, 0x400 },
	3046	+ { 0x9000b, 0x106 },
	3047	+ { 0xd00e7, 0x400 },
	3048	+ { 0x90017, 0x0 },
	3049	+ { 0x9001f, 0x29 },
	3050	+ { 0x90026, 0x68 },
	3051	+ { 0x400d0, 0x0 },
	3052	+ { 0x400d1, 0x101 },
	3053	+ { 0x400d2, 0x105 },
	3054	+ { 0x400d3, 0x107 },
	3055	+ { 0x400d4, 0x10f },
	3056	+ { 0x400d5, 0x202 },
	3057	+ { 0x400d6, 0x20a },
	3058	+ { 0x400d7, 0x20b },
	3059	+ { 0x2003a, 0x2 },
	3060	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	3061	+ { 0x2000b, 0x4b },
	3062	+ { 0x2000c, 0x96 },
	3063	+ { 0x2000d, 0x5dc },
	3064	+#else
	3065	+ { 0x200be, 0x3 },
	3066	+ { 0x2000b, 0x7d },
	3067	+ { 0x2000c, 0xfa },
	3068	+ { 0x2000d, 0x9c4 },
	3069	+#endif
	3070	+ { 0x2000e, 0x2c },
	3071	+ { 0x12000b, 0xc },
	3072	+ { 0x12000c, 0x19 },
	3073	+ { 0x12000d, 0xfa },
	3074	+ { 0x12000e, 0x10 },
	3075	+ { 0x22000b, 0x3 },
	3076	+ { 0x22000c, 0x6 },
	3077	+ { 0x22000d, 0x3e },
	3078	+ { 0x22000e, 0x10 },
	3079	+ { 0x9000c, 0x0 },
	3080	+ { 0x9000d, 0x173 },
	3081	+ { 0x9000e, 0x60 },
	3082	+ { 0x9000f, 0x6110 },
	3083	+ { 0x90010, 0x2152 },
	3084	+ { 0x90011, 0xdfbd },
	3085	+ { 0x90012, 0x2060 },
	3086	+ { 0x90013, 0x6152 },
	3087	+ { 0x20010, 0x5a },
	3088	+ { 0x20011, 0x3 },
	3089	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	3090	+ { 0x120010, 0x5a },
	3091	+ { 0x120011, 0x3 },
	3092	+ { 0x220010, 0x5a },
	3093	+ { 0x220011, 0x3 },
	3094	+#endif
	3095	+ { 0x40080, 0xe0 },
	3096	+ { 0x40081, 0x12 },
	3097	+ { 0x40082, 0xe0 },
	3098	+ { 0x40083, 0x12 },
	3099	+ { 0x40084, 0xe0 },
	3100	+ { 0x40085, 0x12 },
	3101	+ { 0x140080, 0xe0 },
	3102	+ { 0x140081, 0x12 },
	3103	+ { 0x140082, 0xe0 },
	3104	+ { 0x140083, 0x12 },
	3105	+ { 0x140084, 0xe0 },
	3106	+ { 0x140085, 0x12 },
	3107	+ { 0x240080, 0xe0 },
	3108	+ { 0x240081, 0x12 },
	3109	+ { 0x240082, 0xe0 },
	3110	+ { 0x240083, 0x12 },
	3111	+ { 0x240084, 0xe0 },
	3112	+ { 0x240085, 0x12 },
	3113	+ { 0x400fd, 0xf },
	3114	+ { 0x10011, 0x1 },
	3115	+ { 0x10012, 0x1 },
	3116	+ { 0x10013, 0x180 },
	3117	+ { 0x10018, 0x1 },
	3118	+ { 0x10002, 0x6209 },
	3119	+ { 0x100b2, 0x1 },
	3120	+ { 0x101b4, 0x1 },
	3121	+ { 0x102b4, 0x1 },
	3122	+ { 0x103b4, 0x1 },
	3123	+ { 0x104b4, 0x1 },
	3124	+ { 0x105b4, 0x1 },
	3125	+ { 0x106b4, 0x1 },
	3126	+ { 0x107b4, 0x1 },
	3127	+ { 0x108b4, 0x1 },
	3128	+ { 0x11011, 0x1 },
	3129	+ { 0x11012, 0x1 },
	3130	+ { 0x11013, 0x180 },
	3131	+ { 0x11018, 0x1 },
	3132	+ { 0x11002, 0x6209 },
	3133	+ { 0x110b2, 0x1 },
	3134	+ { 0x111b4, 0x1 },
	3135	+ { 0x112b4, 0x1 },
	3136	+ { 0x113b4, 0x1 },
	3137	+ { 0x114b4, 0x1 },
	3138	+ { 0x115b4, 0x1 },
	3139	+ { 0x116b4, 0x1 },
	3140	+ { 0x117b4, 0x1 },
	3141	+ { 0x118b4, 0x1 },
	3142	+ { 0x12011, 0x1 },
	3143	+ { 0x12012, 0x1 },
	3144	+ { 0x12013, 0x180 },
	3145	+ { 0x12018, 0x1 },
	3146	+ { 0x12002, 0x6209 },
	3147	+ { 0x120b2, 0x1 },
	3148	+ { 0x121b4, 0x1 },
	3149	+ { 0x122b4, 0x1 },
	3150	+ { 0x123b4, 0x1 },
	3151	+ { 0x124b4, 0x1 },
	3152	+ { 0x125b4, 0x1 },
	3153	+ { 0x126b4, 0x1 },
	3154	+ { 0x127b4, 0x1 },
	3155	+ { 0x128b4, 0x1 },
	3156	+ { 0x13011, 0x1 },
	3157	+ { 0x13012, 0x1 },
	3158	+ { 0x13013, 0x180 },
	3159	+ { 0x13018, 0x1 },
	3160	+ { 0x13002, 0x6209 },
	3161	+ { 0x130b2, 0x1 },
	3162	+ { 0x131b4, 0x1 },
	3163	+ { 0x132b4, 0x1 },
	3164	+ { 0x133b4, 0x1 },
	3165	+ { 0x134b4, 0x1 },
	3166	+ { 0x135b4, 0x1 },
	3167	+ { 0x136b4, 0x1 },
	3168	+ { 0x137b4, 0x1 },
	3169	+ { 0x138b4, 0x1 },
	3170	+ { 0x20089, 0x1 },
	3171	+ { 0x20088, 0x19 },
	3172	+ { 0xc0080, 0x2 },
	3173	+ { 0xd0000, 0x1 }
	3174	+};
	3175	+
	3176	+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
	3177	+ {
	3178	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	3179	+ /* P0 2400mts 1D */
	3180	+ .drate = 2400,
	3181	+#else
	3182	+ /* P0 4000mts 1D */
	3183	+ .drate = 4000,
	3184	+#endif
	3185	+ .fw_type = FW_1D_IMAGE,
	3186	+ .fsp_cfg = ddr_fsp0_cfg,
	3187	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
	3188	+ },
	3189	+ {
	3190	+ /* P1 400mts 1D */
	3191	+ .drate = 400,
	3192	+ .fw_type = FW_1D_IMAGE,
	3193	+ .fsp_cfg = ddr_fsp1_cfg,
	3194	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
	3195	+ },
	3196	+ {
	3197	+ /* P2 100mts 1D */
	3198	+ .drate = 100,
	3199	+ .fw_type = FW_1D_IMAGE,
	3200	+ .fsp_cfg = ddr_fsp2_cfg,
	3201	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
	3202	+ },
	3203	+ {
	3204	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	3205	+ /* P0 2400mts 2D */
	3206	+ .drate = 2400,
	3207	+#else
	3208	+ /* P0 4000mts 2D */
	3209	+ .drate = 4000,
	3210	+#endif
	3211	+ .fw_type = FW_2D_IMAGE,
	3212	+ .fsp_cfg = ddr_fsp0_2d_cfg,
	3213	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
	3214	+ },
	3215	+};
	3216	+
	3217	+/* ddr timing config params */
	3218	+struct dram_timing_info dram_timing = {
	3219	+ .ddrc_cfg = ddr_ddrc_cfg,
	3220	+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
	3221	+ .ddrphy_cfg = ddr_ddrphy_cfg,
	3222	+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
	3223	+ .fsp_msg = ddr_dram_fsp_msg,
	3224	+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
	3225	+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
	3226	+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
	3227	+ .ddrphy_pie = ddr_phy_pie,
	3228	+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
	3229	+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	3230	+ .fsp_table = { 2400, 400, 100, },
	3231	+#else
	3232	+ .fsp_table = { 4000, 400, 100, },
	3233	+#endif
	3234	+};
	3235	+
	3236	+#ifndef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
	3237	+#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
	3238	+void board_dram_ecc_scrub(void)
	3239	+{
	3240	+ ddrc_inline_ecc_scrub(0x0, 0x3ffffff);
	3241	+ ddrc_inline_ecc_scrub(0x20000000, 0x23ffffff);
	3242	+ ddrc_inline_ecc_scrub(0x40000000, 0x43ffffff);
	3243	+ ddrc_inline_ecc_scrub(0x4000000, 0x7ffffff);
	3244	+ ddrc_inline_ecc_scrub(0x24000000, 0x27ffffff);
	3245	+ ddrc_inline_ecc_scrub(0x44000000, 0x47ffffff);
	3246	+ ddrc_inline_ecc_scrub(0x8000000, 0xbffffff);
	3247	+ ddrc_inline_ecc_scrub(0x28000000, 0x2bffffff);
	3248	+ ddrc_inline_ecc_scrub(0x48000000, 0x4bffffff);
	3249	+ ddrc_inline_ecc_scrub(0xc000000, 0xfffffff);
	3250	+ ddrc_inline_ecc_scrub(0x2c000000, 0x2fffffff);
	3251	+ ddrc_inline_ecc_scrub(0x4c000000, 0x4fffffff);
	3252	+ ddrc_inline_ecc_scrub(0x10000000, 0x13ffffff);
	3253	+ ddrc_inline_ecc_scrub(0x30000000, 0x33ffffff);
	3254	+ ddrc_inline_ecc_scrub(0x50000000, 0x53ffffff);
	3255	+ ddrc_inline_ecc_scrub(0x14000000, 0x17ffffff);
	3256	+ ddrc_inline_ecc_scrub(0x34000000, 0x37ffffff);
	3257	+ ddrc_inline_ecc_scrub(0x54000000, 0x57ffffff);
	3258	+ ddrc_inline_ecc_scrub(0x18000000, 0x1bffffff);
	3259	+ ddrc_inline_ecc_scrub(0x38000000, 0x3bffffff);
	3260	+ ddrc_inline_ecc_scrub(0x58000000, 0x5bffffff);
	3261	+ ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff);
	3262	+}
	3263	+#endif
	3264	+#endif
	3265	diff --git a/board/lingyun/igkboard-imx8mp/lpddr4_timing_ndm.c b/board/lingyun/igkboard-imx8mp/lpddr4_timing_ndm.c
	3266	new file mode 100644
	3267	index 00000000..4765618a
	3268	--- /dev/null
	3269	+++ b/board/lingyun/igkboard-imx8mp/lpddr4_timing_ndm.c
	3270	@@ -0,0 +1,1853 @@
	3271	+/*
	3272	+ * Copyright 2021 NXP
	3273	+ *
	3274	+ * SPDX-License-Identifier: GPL-2.0+
	3275	+ *
	3276	+ * Generated code from MX8M_DDR_tool
	3277	+ *
	3278	+ * Align with uboot version:
	3279	+ * imx_v2019.04_5.4.x and above version
	3280	+ * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga:
	3281	+ * please replace #include <asm/arch/ddr.h> with #include <asm/arch/imx8m_ddr.h>
	3282	+ */
	3283	+
	3284	+#include <linux/kernel.h>
	3285	+#include <asm/arch/ddr.h>
	3286	+
	3287	+struct dram_cfg_param ddr_ddrc_cfg[] = {
	3288	+ / Initialize DDRC registers /
	3289	+ { 0x3d400304, 0x1 },
	3290	+ { 0x3d400030, 0x1 },
	3291	+ { 0x3d400000, 0xa3080020 },
	3292	+ { 0x3d400020, 0x1223 },
	3293	+ { 0x3d400024, 0x186a000 },
	3294	+ { 0x3d400064, 0x610130 },
	3295	+ { 0x3d400070, 0x1027f10 },
	3296	+ { 0x3d400074, 0x7b0 },
	3297	+ { 0x3d4000d0, 0xc003061c },
	3298	+ { 0x3d4000d4, 0x9e0000 },
	3299	+ { 0x3d4000dc, 0xd4002d },
	3300	+ { 0x3d4000e0, 0x330000 },
	3301	+ { 0x3d4000e8, 0x660048 },
	3302	+ { 0x3d4000ec, 0x160048 },
	3303	+ { 0x3d400100, 0x1a201b22 },
	3304	+ { 0x3d400104, 0x60633 },
	3305	+ { 0x3d40010c, 0xc0c000 },
	3306	+ { 0x3d400110, 0xf04080f },
	3307	+ { 0x3d400114, 0x2040c0c },
	3308	+ { 0x3d400118, 0x1010007 },
	3309	+ { 0x3d40011c, 0x401 },
	3310	+ { 0x3d400130, 0x20600 },
	3311	+ { 0x3d400134, 0xe100002 },
	3312	+ { 0x3d400138, 0x136 },
	3313	+ { 0x3d400144, 0xa00050 },
	3314	+ { 0x3d400180, 0x3200018 },
	3315	+ { 0x3d400184, 0x28061a8 },
	3316	+ { 0x3d400188, 0x0 },
	3317	+ { 0x3d400190, 0x497820a },
	3318	+ { 0x3d400194, 0x80303 },
	3319	+ { 0x3d4001b4, 0x170a },
	3320	+ { 0x3d4001a0, 0xe0400018 },
	3321	+ { 0x3d4001a4, 0xdf00e4 },
	3322	+ { 0x3d4001a8, 0x80000000 },
	3323	+ { 0x3d4001b0, 0x11 },
	3324	+ { 0x3d4001c0, 0x1 },
	3325	+ { 0x3d4001c4, 0x1 },
	3326	+ { 0x3d4000f4, 0xc99 },
	3327	+ { 0x3d400108, 0x70e1617 },
	3328	+ { 0x3d400200, 0x16 },
	3329	+ { 0x3d40020c, 0x0 },
	3330	+ { 0x3d400210, 0x1f1f },
	3331	+ { 0x3d400204, 0x80808 },
	3332	+ { 0x3d400214, 0x7070707 },
	3333	+ { 0x3d400218, 0x68070707 },
	3334	+ { 0x3d40021c, 0xf08 },
	3335	+ { 0x3d400250, 0x1705 },
	3336	+ { 0x3d400254, 0x2c },
	3337	+ { 0x3d40025c, 0x4000030 },
	3338	+ { 0x3d400264, 0x900093e7 },
	3339	+ { 0x3d40026c, 0x2005574 },
	3340	+ { 0x3d400400, 0x111 },
	3341	+ { 0x3d400404, 0x72ff },
	3342	+ { 0x3d400408, 0x72ff },
	3343	+ { 0x3d400494, 0x2100e07 },
	3344	+ { 0x3d400498, 0x620096 },
	3345	+ { 0x3d40049c, 0x1100e07 },
	3346	+ { 0x3d4004a0, 0xc8012c },
	3347	+ { 0x3d402020, 0x1021 },
	3348	+ { 0x3d402024, 0x30d400 },
	3349	+ { 0x3d402050, 0x20d000 },
	3350	+ { 0x3d402064, 0xc0026 },
	3351	+ { 0x3d4020dc, 0x840000 },
	3352	+ { 0x3d4020e0, 0x330000 },
	3353	+ { 0x3d4020e8, 0x660048 },
	3354	+ { 0x3d4020ec, 0x160048 },
	3355	+ { 0x3d402100, 0xa040305 },
	3356	+ { 0x3d402104, 0x30407 },
	3357	+ { 0x3d402108, 0x203060b },
	3358	+ { 0x3d40210c, 0x505000 },
	3359	+ { 0x3d402110, 0x2040202 },
	3360	+ { 0x3d402114, 0x2030202 },
	3361	+ { 0x3d402118, 0x1010004 },
	3362	+ { 0x3d40211c, 0x301 },
	3363	+ { 0x3d402130, 0x20300 },
	3364	+ { 0x3d402134, 0xa100002 },
	3365	+ { 0x3d402138, 0x27 },
	3366	+ { 0x3d402144, 0x14000a },
	3367	+ { 0x3d402180, 0x640004 },
	3368	+ { 0x3d402190, 0x3818200 },
	3369	+ { 0x3d402194, 0x80303 },
	3370	+ { 0x3d4021b4, 0x100 },
	3371	+ { 0x3d4020f4, 0xc99 },
	3372	+ { 0x3d403020, 0x1021 },
	3373	+ { 0x3d403024, 0xc3500 },
	3374	+ { 0x3d403050, 0x20d000 },
	3375	+ { 0x3d403064, 0x3000a },
	3376	+ { 0x3d4030dc, 0x840000 },
	3377	+ { 0x3d4030e0, 0x330000 },
	3378	+ { 0x3d4030e8, 0x660048 },
	3379	+ { 0x3d4030ec, 0x160048 },
	3380	+ { 0x3d403100, 0xa010102 },
	3381	+ { 0x3d403104, 0x30404 },
	3382	+ { 0x3d403108, 0x203060b },
	3383	+ { 0x3d40310c, 0x505000 },
	3384	+ { 0x3d403110, 0x2040202 },
	3385	+ { 0x3d403114, 0x2030202 },
	3386	+ { 0x3d403118, 0x1010004 },
	3387	+ { 0x3d40311c, 0x301 },
	3388	+ { 0x3d403130, 0x20300 },
	3389	+ { 0x3d403134, 0xa100002 },
	3390	+ { 0x3d403138, 0xa },
	3391	+ { 0x3d403144, 0x50003 },
	3392	+ { 0x3d403180, 0x190004 },
	3393	+ { 0x3d403190, 0x3818200 },
	3394	+ { 0x3d403194, 0x80303 },
	3395	+ { 0x3d4031b4, 0x100 },
	3396	+ { 0x3d4030f4, 0xc99 },
	3397	+ { 0x3d400028, 0x0 },
	3398	+};
	3399	+
	3400	+/* PHY Initialize Configuration */
	3401	+struct dram_cfg_param ddr_ddrphy_cfg[] = {
	3402	+ { 0x100a0, 0x0 },
	3403	+ { 0x100a1, 0x1 },
	3404	+ { 0x100a2, 0x2 },
	3405	+ { 0x100a3, 0x3 },
	3406	+ { 0x100a4, 0x4 },
	3407	+ { 0x100a5, 0x5 },
	3408	+ { 0x100a6, 0x6 },
	3409	+ { 0x100a7, 0x7 },
	3410	+ { 0x110a0, 0x0 },
	3411	+ { 0x110a1, 0x1 },
	3412	+ { 0x110a2, 0x3 },
	3413	+ { 0x110a3, 0x4 },
	3414	+ { 0x110a4, 0x5 },
	3415	+ { 0x110a5, 0x2 },
	3416	+ { 0x110a6, 0x7 },
	3417	+ { 0x110a7, 0x6 },
	3418	+ { 0x120a0, 0x0 },
	3419	+ { 0x120a1, 0x1 },
	3420	+ { 0x120a2, 0x3 },
	3421	+ { 0x120a3, 0x2 },
	3422	+ { 0x120a4, 0x5 },
	3423	+ { 0x120a5, 0x4 },
	3424	+ { 0x120a6, 0x7 },
	3425	+ { 0x120a7, 0x6 },
	3426	+ { 0x130a0, 0x0 },
	3427	+ { 0x130a1, 0x1 },
	3428	+ { 0x130a2, 0x2 },
	3429	+ { 0x130a3, 0x3 },
	3430	+ { 0x130a4, 0x4 },
	3431	+ { 0x130a5, 0x5 },
	3432	+ { 0x130a6, 0x6 },
	3433	+ { 0x130a7, 0x7 },
	3434	+ { 0x1005f, 0x1ff },
	3435	+ { 0x1015f, 0x1ff },
	3436	+ { 0x1105f, 0x1ff },
	3437	+ { 0x1115f, 0x1ff },
	3438	+ { 0x1205f, 0x1ff },
	3439	+ { 0x1215f, 0x1ff },
	3440	+ { 0x1305f, 0x1ff },
	3441	+ { 0x1315f, 0x1ff },
	3442	+ { 0x11005f, 0x1ff },
	3443	+ { 0x11015f, 0x1ff },
	3444	+ { 0x11105f, 0x1ff },
	3445	+ { 0x11115f, 0x1ff },
	3446	+ { 0x11205f, 0x1ff },
	3447	+ { 0x11215f, 0x1ff },
	3448	+ { 0x11305f, 0x1ff },
	3449	+ { 0x11315f, 0x1ff },
	3450	+ { 0x21005f, 0x1ff },
	3451	+ { 0x21015f, 0x1ff },
	3452	+ { 0x21105f, 0x1ff },
	3453	+ { 0x21115f, 0x1ff },
	3454	+ { 0x21205f, 0x1ff },
	3455	+ { 0x21215f, 0x1ff },
	3456	+ { 0x21305f, 0x1ff },
	3457	+ { 0x21315f, 0x1ff },
	3458	+ { 0x55, 0x1ff },
	3459	+ { 0x1055, 0x1ff },
	3460	+ { 0x2055, 0x1ff },
	3461	+ { 0x3055, 0x1ff },
	3462	+ { 0x4055, 0x1ff },
	3463	+ { 0x5055, 0x1ff },
	3464	+ { 0x6055, 0x1ff },
	3465	+ { 0x7055, 0x1ff },
	3466	+ { 0x8055, 0x1ff },
	3467	+ { 0x9055, 0x1ff },
	3468	+ { 0x200c5, 0x19 },
	3469	+ { 0x1200c5, 0x7 },
	3470	+ { 0x2200c5, 0x7 },
	3471	+ { 0x2002e, 0x2 },
	3472	+ { 0x12002e, 0x2 },
	3473	+ { 0x22002e, 0x2 },
	3474	+ { 0x90204, 0x0 },
	3475	+ { 0x190204, 0x0 },
	3476	+ { 0x290204, 0x0 },
	3477	+ { 0x20024, 0x1e3 },
	3478	+ { 0x2003a, 0x2 },
	3479	+ { 0x120024, 0x1e3 },
	3480	+ { 0x2003a, 0x2 },
	3481	+ { 0x220024, 0x1e3 },
	3482	+ { 0x2003a, 0x2 },
	3483	+ { 0x20056, 0x3 },
	3484	+ { 0x120056, 0x3 },
	3485	+ { 0x220056, 0x3 },
	3486	+ { 0x1004d, 0xe00 },
	3487	+ { 0x1014d, 0xe00 },
	3488	+ { 0x1104d, 0xe00 },
	3489	+ { 0x1114d, 0xe00 },
	3490	+ { 0x1204d, 0xe00 },
	3491	+ { 0x1214d, 0xe00 },
	3492	+ { 0x1304d, 0xe00 },
	3493	+ { 0x1314d, 0xe00 },
	3494	+ { 0x11004d, 0xe00 },
	3495	+ { 0x11014d, 0xe00 },
	3496	+ { 0x11104d, 0xe00 },
	3497	+ { 0x11114d, 0xe00 },
	3498	+ { 0x11204d, 0xe00 },
	3499	+ { 0x11214d, 0xe00 },
	3500	+ { 0x11304d, 0xe00 },
	3501	+ { 0x11314d, 0xe00 },
	3502	+ { 0x21004d, 0xe00 },
	3503	+ { 0x21014d, 0xe00 },
	3504	+ { 0x21104d, 0xe00 },
	3505	+ { 0x21114d, 0xe00 },
	3506	+ { 0x21204d, 0xe00 },
	3507	+ { 0x21214d, 0xe00 },
	3508	+ { 0x21304d, 0xe00 },
	3509	+ { 0x21314d, 0xe00 },
	3510	+ { 0x10049, 0xeba },
	3511	+ { 0x10149, 0xeba },
	3512	+ { 0x11049, 0xeba },
	3513	+ { 0x11149, 0xeba },
	3514	+ { 0x12049, 0xeba },
	3515	+ { 0x12149, 0xeba },
	3516	+ { 0x13049, 0xeba },
	3517	+ { 0x13149, 0xeba },
	3518	+ { 0x110049, 0xeba },
	3519	+ { 0x110149, 0xeba },
	3520	+ { 0x111049, 0xeba },
	3521	+ { 0x111149, 0xeba },
	3522	+ { 0x112049, 0xeba },
	3523	+ { 0x112149, 0xeba },
	3524	+ { 0x113049, 0xeba },
	3525	+ { 0x113149, 0xeba },
	3526	+ { 0x210049, 0xeba },
	3527	+ { 0x210149, 0xeba },
	3528	+ { 0x211049, 0xeba },
	3529	+ { 0x211149, 0xeba },
	3530	+ { 0x212049, 0xeba },
	3531	+ { 0x212149, 0xeba },
	3532	+ { 0x213049, 0xeba },
	3533	+ { 0x213149, 0xeba },
	3534	+ { 0x43, 0x63 },
	3535	+ { 0x1043, 0x63 },
	3536	+ { 0x2043, 0x63 },
	3537	+ { 0x3043, 0x63 },
	3538	+ { 0x4043, 0x63 },
	3539	+ { 0x5043, 0x63 },
	3540	+ { 0x6043, 0x63 },
	3541	+ { 0x7043, 0x63 },
	3542	+ { 0x8043, 0x63 },
	3543	+ { 0x9043, 0x63 },
	3544	+ { 0x20018, 0x3 },
	3545	+ { 0x20075, 0x4 },
	3546	+ { 0x20050, 0x0 },
	3547	+ { 0x20008, 0x320 },
	3548	+ { 0x120008, 0x64 },
	3549	+ { 0x220008, 0x19 },
	3550	+ { 0x20088, 0x9 },
	3551	+ { 0x200b2, 0x104 },
	3552	+ { 0x10043, 0x5a1 },
	3553	+ { 0x10143, 0x5a1 },
	3554	+ { 0x11043, 0x5a1 },
	3555	+ { 0x11143, 0x5a1 },
	3556	+ { 0x12043, 0x5a1 },
	3557	+ { 0x12143, 0x5a1 },
	3558	+ { 0x13043, 0x5a1 },
	3559	+ { 0x13143, 0x5a1 },
	3560	+ { 0x1200b2, 0x104 },
	3561	+ { 0x110043, 0x5a1 },
	3562	+ { 0x110143, 0x5a1 },
	3563	+ { 0x111043, 0x5a1 },
	3564	+ { 0x111143, 0x5a1 },
	3565	+ { 0x112043, 0x5a1 },
	3566	+ { 0x112143, 0x5a1 },
	3567	+ { 0x113043, 0x5a1 },
	3568	+ { 0x113143, 0x5a1 },
	3569	+ { 0x2200b2, 0x104 },
	3570	+ { 0x210043, 0x5a1 },
	3571	+ { 0x210143, 0x5a1 },
	3572	+ { 0x211043, 0x5a1 },
	3573	+ { 0x211143, 0x5a1 },
	3574	+ { 0x212043, 0x5a1 },
	3575	+ { 0x212143, 0x5a1 },
	3576	+ { 0x213043, 0x5a1 },
	3577	+ { 0x213143, 0x5a1 },
	3578	+ { 0x200fa, 0x1 },
	3579	+ { 0x1200fa, 0x1 },
	3580	+ { 0x2200fa, 0x1 },
	3581	+ { 0x20019, 0x1 },
	3582	+ { 0x120019, 0x1 },
	3583	+ { 0x220019, 0x1 },
	3584	+ { 0x200f0, 0x660 },
	3585	+ { 0x200f1, 0x0 },
	3586	+ { 0x200f2, 0x4444 },
	3587	+ { 0x200f3, 0x8888 },
	3588	+ { 0x200f4, 0x5665 },
	3589	+ { 0x200f5, 0x0 },
	3590	+ { 0x200f6, 0x0 },
	3591	+ { 0x200f7, 0xf000 },
	3592	+ { 0x20025, 0x0 },
	3593	+ { 0x2002d, 0x0 },
	3594	+ { 0x12002d, 0x0 },
	3595	+ { 0x22002d, 0x0 },
	3596	+ { 0x2007d, 0x212 },
	3597	+ { 0x12007d, 0x212 },
	3598	+ { 0x22007d, 0x212 },
	3599	+ { 0x2007c, 0x61 },
	3600	+ { 0x12007c, 0x61 },
	3601	+ { 0x22007c, 0x61 },
	3602	+ { 0x1004a, 0x500 },
	3603	+ { 0x1104a, 0x500 },
	3604	+ { 0x1204a, 0x500 },
	3605	+ { 0x1304a, 0x500 },
	3606	+ { 0x2002c, 0x0 },
	3607	+};
	3608	+
	3609	+/* ddr phy trained csr */
	3610	+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
	3611	+ { 0x200b2, 0x0 },
	3612	+ { 0x1200b2, 0x0 },
	3613	+ { 0x2200b2, 0x0 },
	3614	+ { 0x200cb, 0x0 },
	3615	+ { 0x10043, 0x0 },
	3616	+ { 0x110043, 0x0 },
	3617	+ { 0x210043, 0x0 },
	3618	+ { 0x10143, 0x0 },
	3619	+ { 0x110143, 0x0 },
	3620	+ { 0x210143, 0x0 },
	3621	+ { 0x11043, 0x0 },
	3622	+ { 0x111043, 0x0 },
	3623	+ { 0x211043, 0x0 },
	3624	+ { 0x11143, 0x0 },
	3625	+ { 0x111143, 0x0 },
	3626	+ { 0x211143, 0x0 },
	3627	+ { 0x12043, 0x0 },
	3628	+ { 0x112043, 0x0 },
	3629	+ { 0x212043, 0x0 },
	3630	+ { 0x12143, 0x0 },
	3631	+ { 0x112143, 0x0 },
	3632	+ { 0x212143, 0x0 },
	3633	+ { 0x13043, 0x0 },
	3634	+ { 0x113043, 0x0 },
	3635	+ { 0x213043, 0x0 },
	3636	+ { 0x13143, 0x0 },
	3637	+ { 0x113143, 0x0 },
	3638	+ { 0x213143, 0x0 },
	3639	+ { 0x80, 0x0 },
	3640	+ { 0x100080, 0x0 },
	3641	+ { 0x200080, 0x0 },
	3642	+ { 0x1080, 0x0 },
	3643	+ { 0x101080, 0x0 },
	3644	+ { 0x201080, 0x0 },
	3645	+ { 0x2080, 0x0 },
	3646	+ { 0x102080, 0x0 },
	3647	+ { 0x202080, 0x0 },
	3648	+ { 0x3080, 0x0 },
	3649	+ { 0x103080, 0x0 },
	3650	+ { 0x203080, 0x0 },
	3651	+ { 0x4080, 0x0 },
	3652	+ { 0x104080, 0x0 },
	3653	+ { 0x204080, 0x0 },
	3654	+ { 0x5080, 0x0 },
	3655	+ { 0x105080, 0x0 },
	3656	+ { 0x205080, 0x0 },
	3657	+ { 0x6080, 0x0 },
	3658	+ { 0x106080, 0x0 },
	3659	+ { 0x206080, 0x0 },
	3660	+ { 0x7080, 0x0 },
	3661	+ { 0x107080, 0x0 },
	3662	+ { 0x207080, 0x0 },
	3663	+ { 0x8080, 0x0 },
	3664	+ { 0x108080, 0x0 },
	3665	+ { 0x208080, 0x0 },
	3666	+ { 0x9080, 0x0 },
	3667	+ { 0x109080, 0x0 },
	3668	+ { 0x209080, 0x0 },
	3669	+ { 0x10080, 0x0 },
	3670	+ { 0x110080, 0x0 },
	3671	+ { 0x210080, 0x0 },
	3672	+ { 0x10180, 0x0 },
	3673	+ { 0x110180, 0x0 },
	3674	+ { 0x210180, 0x0 },
	3675	+ { 0x11080, 0x0 },
	3676	+ { 0x111080, 0x0 },
	3677	+ { 0x211080, 0x0 },
	3678	+ { 0x11180, 0x0 },
	3679	+ { 0x111180, 0x0 },
	3680	+ { 0x211180, 0x0 },
	3681	+ { 0x12080, 0x0 },
	3682	+ { 0x112080, 0x0 },
	3683	+ { 0x212080, 0x0 },
	3684	+ { 0x12180, 0x0 },
	3685	+ { 0x112180, 0x0 },
	3686	+ { 0x212180, 0x0 },
	3687	+ { 0x13080, 0x0 },
	3688	+ { 0x113080, 0x0 },
	3689	+ { 0x213080, 0x0 },
	3690	+ { 0x13180, 0x0 },
	3691	+ { 0x113180, 0x0 },
	3692	+ { 0x213180, 0x0 },
	3693	+ { 0x10081, 0x0 },
	3694	+ { 0x110081, 0x0 },
	3695	+ { 0x210081, 0x0 },
	3696	+ { 0x10181, 0x0 },
	3697	+ { 0x110181, 0x0 },
	3698	+ { 0x210181, 0x0 },
	3699	+ { 0x11081, 0x0 },
	3700	+ { 0x111081, 0x0 },
	3701	+ { 0x211081, 0x0 },
	3702	+ { 0x11181, 0x0 },
	3703	+ { 0x111181, 0x0 },
	3704	+ { 0x211181, 0x0 },
	3705	+ { 0x12081, 0x0 },
	3706	+ { 0x112081, 0x0 },
	3707	+ { 0x212081, 0x0 },
	3708	+ { 0x12181, 0x0 },
	3709	+ { 0x112181, 0x0 },
	3710	+ { 0x212181, 0x0 },
	3711	+ { 0x13081, 0x0 },
	3712	+ { 0x113081, 0x0 },
	3713	+ { 0x213081, 0x0 },
	3714	+ { 0x13181, 0x0 },
	3715	+ { 0x113181, 0x0 },
	3716	+ { 0x213181, 0x0 },
	3717	+ { 0x100d0, 0x0 },
	3718	+ { 0x1100d0, 0x0 },
	3719	+ { 0x2100d0, 0x0 },
	3720	+ { 0x101d0, 0x0 },
	3721	+ { 0x1101d0, 0x0 },
	3722	+ { 0x2101d0, 0x0 },
	3723	+ { 0x110d0, 0x0 },
	3724	+ { 0x1110d0, 0x0 },
	3725	+ { 0x2110d0, 0x0 },
	3726	+ { 0x111d0, 0x0 },
	3727	+ { 0x1111d0, 0x0 },
	3728	+ { 0x2111d0, 0x0 },
	3729	+ { 0x120d0, 0x0 },
	3730	+ { 0x1120d0, 0x0 },
	3731	+ { 0x2120d0, 0x0 },
	3732	+ { 0x121d0, 0x0 },
	3733	+ { 0x1121d0, 0x0 },
	3734	+ { 0x2121d0, 0x0 },
	3735	+ { 0x130d0, 0x0 },
	3736	+ { 0x1130d0, 0x0 },
	3737	+ { 0x2130d0, 0x0 },
	3738	+ { 0x131d0, 0x0 },
	3739	+ { 0x1131d0, 0x0 },
	3740	+ { 0x2131d0, 0x0 },
	3741	+ { 0x100d1, 0x0 },
	3742	+ { 0x1100d1, 0x0 },
	3743	+ { 0x2100d1, 0x0 },
	3744	+ { 0x101d1, 0x0 },
	3745	+ { 0x1101d1, 0x0 },
	3746	+ { 0x2101d1, 0x0 },
	3747	+ { 0x110d1, 0x0 },
	3748	+ { 0x1110d1, 0x0 },
	3749	+ { 0x2110d1, 0x0 },
	3750	+ { 0x111d1, 0x0 },
	3751	+ { 0x1111d1, 0x0 },
	3752	+ { 0x2111d1, 0x0 },
	3753	+ { 0x120d1, 0x0 },
	3754	+ { 0x1120d1, 0x0 },
	3755	+ { 0x2120d1, 0x0 },
	3756	+ { 0x121d1, 0x0 },
	3757	+ { 0x1121d1, 0x0 },
	3758	+ { 0x2121d1, 0x0 },
	3759	+ { 0x130d1, 0x0 },
	3760	+ { 0x1130d1, 0x0 },
	3761	+ { 0x2130d1, 0x0 },
	3762	+ { 0x131d1, 0x0 },
	3763	+ { 0x1131d1, 0x0 },
	3764	+ { 0x2131d1, 0x0 },
	3765	+ { 0x10068, 0x0 },
	3766	+ { 0x10168, 0x0 },
	3767	+ { 0x10268, 0x0 },
	3768	+ { 0x10368, 0x0 },
	3769	+ { 0x10468, 0x0 },
	3770	+ { 0x10568, 0x0 },
	3771	+ { 0x10668, 0x0 },
	3772	+ { 0x10768, 0x0 },
	3773	+ { 0x10868, 0x0 },
	3774	+ { 0x11068, 0x0 },
	3775	+ { 0x11168, 0x0 },
	3776	+ { 0x11268, 0x0 },
	3777	+ { 0x11368, 0x0 },
	3778	+ { 0x11468, 0x0 },
	3779	+ { 0x11568, 0x0 },
	3780	+ { 0x11668, 0x0 },
	3781	+ { 0x11768, 0x0 },
	3782	+ { 0x11868, 0x0 },
	3783	+ { 0x12068, 0x0 },
	3784	+ { 0x12168, 0x0 },
	3785	+ { 0x12268, 0x0 },
	3786	+ { 0x12368, 0x0 },
	3787	+ { 0x12468, 0x0 },
	3788	+ { 0x12568, 0x0 },
	3789	+ { 0x12668, 0x0 },
	3790	+ { 0x12768, 0x0 },
	3791	+ { 0x12868, 0x0 },
	3792	+ { 0x13068, 0x0 },
	3793	+ { 0x13168, 0x0 },
	3794	+ { 0x13268, 0x0 },
	3795	+ { 0x13368, 0x0 },
	3796	+ { 0x13468, 0x0 },
	3797	+ { 0x13568, 0x0 },
	3798	+ { 0x13668, 0x0 },
	3799	+ { 0x13768, 0x0 },
	3800	+ { 0x13868, 0x0 },
	3801	+ { 0x10069, 0x0 },
	3802	+ { 0x10169, 0x0 },
	3803	+ { 0x10269, 0x0 },
	3804	+ { 0x10369, 0x0 },
	3805	+ { 0x10469, 0x0 },
	3806	+ { 0x10569, 0x0 },
	3807	+ { 0x10669, 0x0 },
	3808	+ { 0x10769, 0x0 },
	3809	+ { 0x10869, 0x0 },
	3810	+ { 0x11069, 0x0 },
	3811	+ { 0x11169, 0x0 },
	3812	+ { 0x11269, 0x0 },
	3813	+ { 0x11369, 0x0 },
	3814	+ { 0x11469, 0x0 },
	3815	+ { 0x11569, 0x0 },
	3816	+ { 0x11669, 0x0 },
	3817	+ { 0x11769, 0x0 },
	3818	+ { 0x11869, 0x0 },
	3819	+ { 0x12069, 0x0 },
	3820	+ { 0x12169, 0x0 },
	3821	+ { 0x12269, 0x0 },
	3822	+ { 0x12369, 0x0 },
	3823	+ { 0x12469, 0x0 },
	3824	+ { 0x12569, 0x0 },
	3825	+ { 0x12669, 0x0 },
	3826	+ { 0x12769, 0x0 },
	3827	+ { 0x12869, 0x0 },
	3828	+ { 0x13069, 0x0 },
	3829	+ { 0x13169, 0x0 },
	3830	+ { 0x13269, 0x0 },
	3831	+ { 0x13369, 0x0 },
	3832	+ { 0x13469, 0x0 },
	3833	+ { 0x13569, 0x0 },
	3834	+ { 0x13669, 0x0 },
	3835	+ { 0x13769, 0x0 },
	3836	+ { 0x13869, 0x0 },
	3837	+ { 0x1008c, 0x0 },
	3838	+ { 0x11008c, 0x0 },
	3839	+ { 0x21008c, 0x0 },
	3840	+ { 0x1018c, 0x0 },
	3841	+ { 0x11018c, 0x0 },
	3842	+ { 0x21018c, 0x0 },
	3843	+ { 0x1108c, 0x0 },
	3844	+ { 0x11108c, 0x0 },
	3845	+ { 0x21108c, 0x0 },
	3846	+ { 0x1118c, 0x0 },
	3847	+ { 0x11118c, 0x0 },
	3848	+ { 0x21118c, 0x0 },
	3849	+ { 0x1208c, 0x0 },
	3850	+ { 0x11208c, 0x0 },
	3851	+ { 0x21208c, 0x0 },
	3852	+ { 0x1218c, 0x0 },
	3853	+ { 0x11218c, 0x0 },
	3854	+ { 0x21218c, 0x0 },
	3855	+ { 0x1308c, 0x0 },
	3856	+ { 0x11308c, 0x0 },
	3857	+ { 0x21308c, 0x0 },
	3858	+ { 0x1318c, 0x0 },
	3859	+ { 0x11318c, 0x0 },
	3860	+ { 0x21318c, 0x0 },
	3861	+ { 0x1008d, 0x0 },
	3862	+ { 0x11008d, 0x0 },
	3863	+ { 0x21008d, 0x0 },
	3864	+ { 0x1018d, 0x0 },
	3865	+ { 0x11018d, 0x0 },
	3866	+ { 0x21018d, 0x0 },
	3867	+ { 0x1108d, 0x0 },
	3868	+ { 0x11108d, 0x0 },
	3869	+ { 0x21108d, 0x0 },
	3870	+ { 0x1118d, 0x0 },
	3871	+ { 0x11118d, 0x0 },
	3872	+ { 0x21118d, 0x0 },
	3873	+ { 0x1208d, 0x0 },
	3874	+ { 0x11208d, 0x0 },
	3875	+ { 0x21208d, 0x0 },
	3876	+ { 0x1218d, 0x0 },
	3877	+ { 0x11218d, 0x0 },
	3878	+ { 0x21218d, 0x0 },
	3879	+ { 0x1308d, 0x0 },
	3880	+ { 0x11308d, 0x0 },
	3881	+ { 0x21308d, 0x0 },
	3882	+ { 0x1318d, 0x0 },
	3883	+ { 0x11318d, 0x0 },
	3884	+ { 0x21318d, 0x0 },
	3885	+ { 0x100c0, 0x0 },
	3886	+ { 0x1100c0, 0x0 },
	3887	+ { 0x2100c0, 0x0 },
	3888	+ { 0x101c0, 0x0 },
	3889	+ { 0x1101c0, 0x0 },
	3890	+ { 0x2101c0, 0x0 },
	3891	+ { 0x102c0, 0x0 },
	3892	+ { 0x1102c0, 0x0 },
	3893	+ { 0x2102c0, 0x0 },
	3894	+ { 0x103c0, 0x0 },
	3895	+ { 0x1103c0, 0x0 },
	3896	+ { 0x2103c0, 0x0 },
	3897	+ { 0x104c0, 0x0 },
	3898	+ { 0x1104c0, 0x0 },
	3899	+ { 0x2104c0, 0x0 },
	3900	+ { 0x105c0, 0x0 },
	3901	+ { 0x1105c0, 0x0 },
	3902	+ { 0x2105c0, 0x0 },
	3903	+ { 0x106c0, 0x0 },
	3904	+ { 0x1106c0, 0x0 },
	3905	+ { 0x2106c0, 0x0 },
	3906	+ { 0x107c0, 0x0 },
	3907	+ { 0x1107c0, 0x0 },
	3908	+ { 0x2107c0, 0x0 },
	3909	+ { 0x108c0, 0x0 },
	3910	+ { 0x1108c0, 0x0 },
	3911	+ { 0x2108c0, 0x0 },
	3912	+ { 0x110c0, 0x0 },
	3913	+ { 0x1110c0, 0x0 },
	3914	+ { 0x2110c0, 0x0 },
	3915	+ { 0x111c0, 0x0 },
	3916	+ { 0x1111c0, 0x0 },
	3917	+ { 0x2111c0, 0x0 },
	3918	+ { 0x112c0, 0x0 },
	3919	+ { 0x1112c0, 0x0 },
	3920	+ { 0x2112c0, 0x0 },
	3921	+ { 0x113c0, 0x0 },
	3922	+ { 0x1113c0, 0x0 },
	3923	+ { 0x2113c0, 0x0 },
	3924	+ { 0x114c0, 0x0 },
	3925	+ { 0x1114c0, 0x0 },
	3926	+ { 0x2114c0, 0x0 },
	3927	+ { 0x115c0, 0x0 },
	3928	+ { 0x1115c0, 0x0 },
	3929	+ { 0x2115c0, 0x0 },
	3930	+ { 0x116c0, 0x0 },
	3931	+ { 0x1116c0, 0x0 },
	3932	+ { 0x2116c0, 0x0 },
	3933	+ { 0x117c0, 0x0 },
	3934	+ { 0x1117c0, 0x0 },
	3935	+ { 0x2117c0, 0x0 },
	3936	+ { 0x118c0, 0x0 },
	3937	+ { 0x1118c0, 0x0 },
	3938	+ { 0x2118c0, 0x0 },
	3939	+ { 0x120c0, 0x0 },
	3940	+ { 0x1120c0, 0x0 },
	3941	+ { 0x2120c0, 0x0 },
	3942	+ { 0x121c0, 0x0 },
	3943	+ { 0x1121c0, 0x0 },
	3944	+ { 0x2121c0, 0x0 },
	3945	+ { 0x122c0, 0x0 },
	3946	+ { 0x1122c0, 0x0 },
	3947	+ { 0x2122c0, 0x0 },
	3948	+ { 0x123c0, 0x0 },
	3949	+ { 0x1123c0, 0x0 },
	3950	+ { 0x2123c0, 0x0 },
	3951	+ { 0x124c0, 0x0 },
	3952	+ { 0x1124c0, 0x0 },
	3953	+ { 0x2124c0, 0x0 },
	3954	+ { 0x125c0, 0x0 },
	3955	+ { 0x1125c0, 0x0 },
	3956	+ { 0x2125c0, 0x0 },
	3957	+ { 0x126c0, 0x0 },
	3958	+ { 0x1126c0, 0x0 },
	3959	+ { 0x2126c0, 0x0 },
	3960	+ { 0x127c0, 0x0 },
	3961	+ { 0x1127c0, 0x0 },
	3962	+ { 0x2127c0, 0x0 },
	3963	+ { 0x128c0, 0x0 },
	3964	+ { 0x1128c0, 0x0 },
	3965	+ { 0x2128c0, 0x0 },
	3966	+ { 0x130c0, 0x0 },
	3967	+ { 0x1130c0, 0x0 },
	3968	+ { 0x2130c0, 0x0 },
	3969	+ { 0x131c0, 0x0 },
	3970	+ { 0x1131c0, 0x0 },
	3971	+ { 0x2131c0, 0x0 },
	3972	+ { 0x132c0, 0x0 },
	3973	+ { 0x1132c0, 0x0 },
	3974	+ { 0x2132c0, 0x0 },
	3975	+ { 0x133c0, 0x0 },
	3976	+ { 0x1133c0, 0x0 },
	3977	+ { 0x2133c0, 0x0 },
	3978	+ { 0x134c0, 0x0 },
	3979	+ { 0x1134c0, 0x0 },
	3980	+ { 0x2134c0, 0x0 },
	3981	+ { 0x135c0, 0x0 },
	3982	+ { 0x1135c0, 0x0 },
	3983	+ { 0x2135c0, 0x0 },
	3984	+ { 0x136c0, 0x0 },
	3985	+ { 0x1136c0, 0x0 },
	3986	+ { 0x2136c0, 0x0 },
	3987	+ { 0x137c0, 0x0 },
	3988	+ { 0x1137c0, 0x0 },
	3989	+ { 0x2137c0, 0x0 },
	3990	+ { 0x138c0, 0x0 },
	3991	+ { 0x1138c0, 0x0 },
	3992	+ { 0x2138c0, 0x0 },
	3993	+ { 0x100c1, 0x0 },
	3994	+ { 0x1100c1, 0x0 },
	3995	+ { 0x2100c1, 0x0 },
	3996	+ { 0x101c1, 0x0 },
	3997	+ { 0x1101c1, 0x0 },
	3998	+ { 0x2101c1, 0x0 },
	3999	+ { 0x102c1, 0x0 },
	4000	+ { 0x1102c1, 0x0 },
	4001	+ { 0x2102c1, 0x0 },
	4002	+ { 0x103c1, 0x0 },
	4003	+ { 0x1103c1, 0x0 },
	4004	+ { 0x2103c1, 0x0 },
	4005	+ { 0x104c1, 0x0 },
	4006	+ { 0x1104c1, 0x0 },
	4007	+ { 0x2104c1, 0x0 },
	4008	+ { 0x105c1, 0x0 },
	4009	+ { 0x1105c1, 0x0 },
	4010	+ { 0x2105c1, 0x0 },
	4011	+ { 0x106c1, 0x0 },
	4012	+ { 0x1106c1, 0x0 },
	4013	+ { 0x2106c1, 0x0 },
	4014	+ { 0x107c1, 0x0 },
	4015	+ { 0x1107c1, 0x0 },
	4016	+ { 0x2107c1, 0x0 },
	4017	+ { 0x108c1, 0x0 },
	4018	+ { 0x1108c1, 0x0 },
	4019	+ { 0x2108c1, 0x0 },
	4020	+ { 0x110c1, 0x0 },
	4021	+ { 0x1110c1, 0x0 },
	4022	+ { 0x2110c1, 0x0 },
	4023	+ { 0x111c1, 0x0 },
	4024	+ { 0x1111c1, 0x0 },
	4025	+ { 0x2111c1, 0x0 },
	4026	+ { 0x112c1, 0x0 },
	4027	+ { 0x1112c1, 0x0 },
	4028	+ { 0x2112c1, 0x0 },
	4029	+ { 0x113c1, 0x0 },
	4030	+ { 0x1113c1, 0x0 },
	4031	+ { 0x2113c1, 0x0 },
	4032	+ { 0x114c1, 0x0 },
	4033	+ { 0x1114c1, 0x0 },
	4034	+ { 0x2114c1, 0x0 },
	4035	+ { 0x115c1, 0x0 },
	4036	+ { 0x1115c1, 0x0 },
	4037	+ { 0x2115c1, 0x0 },
	4038	+ { 0x116c1, 0x0 },
	4039	+ { 0x1116c1, 0x0 },
	4040	+ { 0x2116c1, 0x0 },
	4041	+ { 0x117c1, 0x0 },
	4042	+ { 0x1117c1, 0x0 },
	4043	+ { 0x2117c1, 0x0 },
	4044	+ { 0x118c1, 0x0 },
	4045	+ { 0x1118c1, 0x0 },
	4046	+ { 0x2118c1, 0x0 },
	4047	+ { 0x120c1, 0x0 },
	4048	+ { 0x1120c1, 0x0 },
	4049	+ { 0x2120c1, 0x0 },
	4050	+ { 0x121c1, 0x0 },
	4051	+ { 0x1121c1, 0x0 },
	4052	+ { 0x2121c1, 0x0 },
	4053	+ { 0x122c1, 0x0 },
	4054	+ { 0x1122c1, 0x0 },
	4055	+ { 0x2122c1, 0x0 },
	4056	+ { 0x123c1, 0x0 },
	4057	+ { 0x1123c1, 0x0 },
	4058	+ { 0x2123c1, 0x0 },
	4059	+ { 0x124c1, 0x0 },
	4060	+ { 0x1124c1, 0x0 },
	4061	+ { 0x2124c1, 0x0 },
	4062	+ { 0x125c1, 0x0 },
	4063	+ { 0x1125c1, 0x0 },
	4064	+ { 0x2125c1, 0x0 },
	4065	+ { 0x126c1, 0x0 },
	4066	+ { 0x1126c1, 0x0 },
	4067	+ { 0x2126c1, 0x0 },
	4068	+ { 0x127c1, 0x0 },
	4069	+ { 0x1127c1, 0x0 },
	4070	+ { 0x2127c1, 0x0 },
	4071	+ { 0x128c1, 0x0 },
	4072	+ { 0x1128c1, 0x0 },
	4073	+ { 0x2128c1, 0x0 },
	4074	+ { 0x130c1, 0x0 },
	4075	+ { 0x1130c1, 0x0 },
	4076	+ { 0x2130c1, 0x0 },
	4077	+ { 0x131c1, 0x0 },
	4078	+ { 0x1131c1, 0x0 },
	4079	+ { 0x2131c1, 0x0 },
	4080	+ { 0x132c1, 0x0 },
	4081	+ { 0x1132c1, 0x0 },
	4082	+ { 0x2132c1, 0x0 },
	4083	+ { 0x133c1, 0x0 },
	4084	+ { 0x1133c1, 0x0 },
	4085	+ { 0x2133c1, 0x0 },
	4086	+ { 0x134c1, 0x0 },
	4087	+ { 0x1134c1, 0x0 },
	4088	+ { 0x2134c1, 0x0 },
	4089	+ { 0x135c1, 0x0 },
	4090	+ { 0x1135c1, 0x0 },
	4091	+ { 0x2135c1, 0x0 },
	4092	+ { 0x136c1, 0x0 },
	4093	+ { 0x1136c1, 0x0 },
	4094	+ { 0x2136c1, 0x0 },
	4095	+ { 0x137c1, 0x0 },
	4096	+ { 0x1137c1, 0x0 },
	4097	+ { 0x2137c1, 0x0 },
	4098	+ { 0x138c1, 0x0 },
	4099	+ { 0x1138c1, 0x0 },
	4100	+ { 0x2138c1, 0x0 },
	4101	+ { 0x10020, 0x0 },
	4102	+ { 0x110020, 0x0 },
	4103	+ { 0x210020, 0x0 },
	4104	+ { 0x11020, 0x0 },
	4105	+ { 0x111020, 0x0 },
	4106	+ { 0x211020, 0x0 },
	4107	+ { 0x12020, 0x0 },
	4108	+ { 0x112020, 0x0 },
	4109	+ { 0x212020, 0x0 },
	4110	+ { 0x13020, 0x0 },
	4111	+ { 0x113020, 0x0 },
	4112	+ { 0x213020, 0x0 },
	4113	+ { 0x20072, 0x0 },
	4114	+ { 0x20073, 0x0 },
	4115	+ { 0x20074, 0x0 },
	4116	+ { 0x100aa, 0x0 },
	4117	+ { 0x110aa, 0x0 },
	4118	+ { 0x120aa, 0x0 },
	4119	+ { 0x130aa, 0x0 },
	4120	+ { 0x20010, 0x0 },
	4121	+ { 0x120010, 0x0 },
	4122	+ { 0x220010, 0x0 },
	4123	+ { 0x20011, 0x0 },
	4124	+ { 0x120011, 0x0 },
	4125	+ { 0x220011, 0x0 },
	4126	+ { 0x100ae, 0x0 },
	4127	+ { 0x1100ae, 0x0 },
	4128	+ { 0x2100ae, 0x0 },
	4129	+ { 0x100af, 0x0 },
	4130	+ { 0x1100af, 0x0 },
	4131	+ { 0x2100af, 0x0 },
	4132	+ { 0x110ae, 0x0 },
	4133	+ { 0x1110ae, 0x0 },
	4134	+ { 0x2110ae, 0x0 },
	4135	+ { 0x110af, 0x0 },
	4136	+ { 0x1110af, 0x0 },
	4137	+ { 0x2110af, 0x0 },
	4138	+ { 0x120ae, 0x0 },
	4139	+ { 0x1120ae, 0x0 },
	4140	+ { 0x2120ae, 0x0 },
	4141	+ { 0x120af, 0x0 },
	4142	+ { 0x1120af, 0x0 },
	4143	+ { 0x2120af, 0x0 },
	4144	+ { 0x130ae, 0x0 },
	4145	+ { 0x1130ae, 0x0 },
	4146	+ { 0x2130ae, 0x0 },
	4147	+ { 0x130af, 0x0 },
	4148	+ { 0x1130af, 0x0 },
	4149	+ { 0x2130af, 0x0 },
	4150	+ { 0x20020, 0x0 },
	4151	+ { 0x120020, 0x0 },
	4152	+ { 0x220020, 0x0 },
	4153	+ { 0x100a0, 0x0 },
	4154	+ { 0x100a1, 0x0 },
	4155	+ { 0x100a2, 0x0 },
	4156	+ { 0x100a3, 0x0 },
	4157	+ { 0x100a4, 0x0 },
	4158	+ { 0x100a5, 0x0 },
	4159	+ { 0x100a6, 0x0 },
	4160	+ { 0x100a7, 0x0 },
	4161	+ { 0x110a0, 0x0 },
	4162	+ { 0x110a1, 0x0 },
	4163	+ { 0x110a2, 0x0 },
	4164	+ { 0x110a3, 0x0 },
	4165	+ { 0x110a4, 0x0 },
	4166	+ { 0x110a5, 0x0 },
	4167	+ { 0x110a6, 0x0 },
	4168	+ { 0x110a7, 0x0 },
	4169	+ { 0x120a0, 0x0 },
	4170	+ { 0x120a1, 0x0 },
	4171	+ { 0x120a2, 0x0 },
	4172	+ { 0x120a3, 0x0 },
	4173	+ { 0x120a4, 0x0 },
	4174	+ { 0x120a5, 0x0 },
	4175	+ { 0x120a6, 0x0 },
	4176	+ { 0x120a7, 0x0 },
	4177	+ { 0x130a0, 0x0 },
	4178	+ { 0x130a1, 0x0 },
	4179	+ { 0x130a2, 0x0 },
	4180	+ { 0x130a3, 0x0 },
	4181	+ { 0x130a4, 0x0 },
	4182	+ { 0x130a5, 0x0 },
	4183	+ { 0x130a6, 0x0 },
	4184	+ { 0x130a7, 0x0 },
	4185	+ { 0x2007c, 0x0 },
	4186	+ { 0x12007c, 0x0 },
	4187	+ { 0x22007c, 0x0 },
	4188	+ { 0x2007d, 0x0 },
	4189	+ { 0x12007d, 0x0 },
	4190	+ { 0x22007d, 0x0 },
	4191	+ { 0x400fd, 0x0 },
	4192	+ { 0x400c0, 0x0 },
	4193	+ { 0x90201, 0x0 },
	4194	+ { 0x190201, 0x0 },
	4195	+ { 0x290201, 0x0 },
	4196	+ { 0x90202, 0x0 },
	4197	+ { 0x190202, 0x0 },
	4198	+ { 0x290202, 0x0 },
	4199	+ { 0x90203, 0x0 },
	4200	+ { 0x190203, 0x0 },
	4201	+ { 0x290203, 0x0 },
	4202	+ { 0x90204, 0x0 },
	4203	+ { 0x190204, 0x0 },
	4204	+ { 0x290204, 0x0 },
	4205	+ { 0x90205, 0x0 },
	4206	+ { 0x190205, 0x0 },
	4207	+ { 0x290205, 0x0 },
	4208	+ { 0x90206, 0x0 },
	4209	+ { 0x190206, 0x0 },
	4210	+ { 0x290206, 0x0 },
	4211	+ { 0x90207, 0x0 },
	4212	+ { 0x190207, 0x0 },
	4213	+ { 0x290207, 0x0 },
	4214	+ { 0x90208, 0x0 },
	4215	+ { 0x190208, 0x0 },
	4216	+ { 0x290208, 0x0 },
	4217	+ { 0x10062, 0x0 },
	4218	+ { 0x10162, 0x0 },
	4219	+ { 0x10262, 0x0 },
	4220	+ { 0x10362, 0x0 },
	4221	+ { 0x10462, 0x0 },
	4222	+ { 0x10562, 0x0 },
	4223	+ { 0x10662, 0x0 },
	4224	+ { 0x10762, 0x0 },
	4225	+ { 0x10862, 0x0 },
	4226	+ { 0x11062, 0x0 },
	4227	+ { 0x11162, 0x0 },
	4228	+ { 0x11262, 0x0 },
	4229	+ { 0x11362, 0x0 },
	4230	+ { 0x11462, 0x0 },
	4231	+ { 0x11562, 0x0 },
	4232	+ { 0x11662, 0x0 },
	4233	+ { 0x11762, 0x0 },
	4234	+ { 0x11862, 0x0 },
	4235	+ { 0x12062, 0x0 },
	4236	+ { 0x12162, 0x0 },
	4237	+ { 0x12262, 0x0 },
	4238	+ { 0x12362, 0x0 },
	4239	+ { 0x12462, 0x0 },
	4240	+ { 0x12562, 0x0 },
	4241	+ { 0x12662, 0x0 },
	4242	+ { 0x12762, 0x0 },
	4243	+ { 0x12862, 0x0 },
	4244	+ { 0x13062, 0x0 },
	4245	+ { 0x13162, 0x0 },
	4246	+ { 0x13262, 0x0 },
	4247	+ { 0x13362, 0x0 },
	4248	+ { 0x13462, 0x0 },
	4249	+ { 0x13562, 0x0 },
	4250	+ { 0x13662, 0x0 },
	4251	+ { 0x13762, 0x0 },
	4252	+ { 0x13862, 0x0 },
	4253	+ { 0x20077, 0x0 },
	4254	+ { 0x10001, 0x0 },
	4255	+ { 0x11001, 0x0 },
	4256	+ { 0x12001, 0x0 },
	4257	+ { 0x13001, 0x0 },
	4258	+ { 0x10040, 0x0 },
	4259	+ { 0x10140, 0x0 },
	4260	+ { 0x10240, 0x0 },
	4261	+ { 0x10340, 0x0 },
	4262	+ { 0x10440, 0x0 },
	4263	+ { 0x10540, 0x0 },
	4264	+ { 0x10640, 0x0 },
	4265	+ { 0x10740, 0x0 },
	4266	+ { 0x10840, 0x0 },
	4267	+ { 0x10030, 0x0 },
	4268	+ { 0x10130, 0x0 },
	4269	+ { 0x10230, 0x0 },
	4270	+ { 0x10330, 0x0 },
	4271	+ { 0x10430, 0x0 },
	4272	+ { 0x10530, 0x0 },
	4273	+ { 0x10630, 0x0 },
	4274	+ { 0x10730, 0x0 },
	4275	+ { 0x10830, 0x0 },
	4276	+ { 0x11040, 0x0 },
	4277	+ { 0x11140, 0x0 },
	4278	+ { 0x11240, 0x0 },
	4279	+ { 0x11340, 0x0 },
	4280	+ { 0x11440, 0x0 },
	4281	+ { 0x11540, 0x0 },
	4282	+ { 0x11640, 0x0 },
	4283	+ { 0x11740, 0x0 },
	4284	+ { 0x11840, 0x0 },
	4285	+ { 0x11030, 0x0 },
	4286	+ { 0x11130, 0x0 },
	4287	+ { 0x11230, 0x0 },
	4288	+ { 0x11330, 0x0 },
	4289	+ { 0x11430, 0x0 },
	4290	+ { 0x11530, 0x0 },
	4291	+ { 0x11630, 0x0 },
	4292	+ { 0x11730, 0x0 },
	4293	+ { 0x11830, 0x0 },
	4294	+ { 0x12040, 0x0 },
	4295	+ { 0x12140, 0x0 },
	4296	+ { 0x12240, 0x0 },
	4297	+ { 0x12340, 0x0 },
	4298	+ { 0x12440, 0x0 },
	4299	+ { 0x12540, 0x0 },
	4300	+ { 0x12640, 0x0 },
	4301	+ { 0x12740, 0x0 },
	4302	+ { 0x12840, 0x0 },
	4303	+ { 0x12030, 0x0 },
	4304	+ { 0x12130, 0x0 },
	4305	+ { 0x12230, 0x0 },
	4306	+ { 0x12330, 0x0 },
	4307	+ { 0x12430, 0x0 },
	4308	+ { 0x12530, 0x0 },
	4309	+ { 0x12630, 0x0 },
	4310	+ { 0x12730, 0x0 },
	4311	+ { 0x12830, 0x0 },
	4312	+ { 0x13040, 0x0 },
	4313	+ { 0x13140, 0x0 },
	4314	+ { 0x13240, 0x0 },
	4315	+ { 0x13340, 0x0 },
	4316	+ { 0x13440, 0x0 },
	4317	+ { 0x13540, 0x0 },
	4318	+ { 0x13640, 0x0 },
	4319	+ { 0x13740, 0x0 },
	4320	+ { 0x13840, 0x0 },
	4321	+ { 0x13030, 0x0 },
	4322	+ { 0x13130, 0x0 },
	4323	+ { 0x13230, 0x0 },
	4324	+ { 0x13330, 0x0 },
	4325	+ { 0x13430, 0x0 },
	4326	+ { 0x13530, 0x0 },
	4327	+ { 0x13630, 0x0 },
	4328	+ { 0x13730, 0x0 },
	4329	+ { 0x13830, 0x0 },
	4330	+};
	4331	+/* P0 message block paremeter for training firmware */
	4332	+struct dram_cfg_param ddr_fsp0_cfg[] = {
	4333	+ { 0xd0000, 0x0 },
	4334	+ { 0x54003, 0xc80 },
	4335	+ { 0x54004, 0x2 },
	4336	+ { 0x54005, 0x2228 },
	4337	+ { 0x54006, 0x14 },
	4338	+ { 0x54008, 0x131f },
	4339	+ { 0x54009, 0xc8 },
	4340	+ { 0x5400b, 0x2 },
	4341	+ { 0x5400f, 0x100 },
	4342	+ { 0x54012, 0x310 },
	4343	+ { 0x54019, 0x2dd4 },
	4344	+ { 0x5401a, 0x33 },
	4345	+ { 0x5401b, 0x4866 },
	4346	+ { 0x5401c, 0x4800 },
	4347	+ { 0x5401e, 0x16 },
	4348	+ { 0x5401f, 0x2dd4 },
	4349	+ { 0x54020, 0x33 },
	4350	+ { 0x54021, 0x4866 },
	4351	+ { 0x54022, 0x4800 },
	4352	+ { 0x54024, 0x16 },
	4353	+ { 0x5402b, 0x1000 },
	4354	+ { 0x5402c, 0x3 },
	4355	+ { 0x54032, 0xd400 },
	4356	+ { 0x54033, 0x332d },
	4357	+ { 0x54034, 0x6600 },
	4358	+ { 0x54035, 0x48 },
	4359	+ { 0x54036, 0x48 },
	4360	+ { 0x54037, 0x1600 },
	4361	+ { 0x54038, 0xd400 },
	4362	+ { 0x54039, 0x332d },
	4363	+ { 0x5403a, 0x6600 },
	4364	+ { 0x5403b, 0x48 },
	4365	+ { 0x5403c, 0x48 },
	4366	+ { 0x5403d, 0x1600 },
	4367	+ { 0xd0000, 0x1 },
	4368	+};
	4369	+
	4370	+
	4371	+/* P1 message block paremeter for training firmware */
	4372	+struct dram_cfg_param ddr_fsp1_cfg[] = {
	4373	+ { 0xd0000, 0x0 },
	4374	+ { 0x54002, 0x101 },
	4375	+ { 0x54003, 0x190 },
	4376	+ { 0x54004, 0x2 },
	4377	+ { 0x54005, 0x2228 },
	4378	+ { 0x54006, 0x14 },
	4379	+ { 0x54008, 0x121f },
	4380	+ { 0x54009, 0xc8 },
	4381	+ { 0x5400b, 0x2 },
	4382	+ { 0x5400f, 0x100 },
	4383	+ { 0x54012, 0x310 },
	4384	+ { 0x54019, 0x84 },
	4385	+ { 0x5401a, 0x33 },
	4386	+ { 0x5401b, 0x4866 },
	4387	+ { 0x5401c, 0x4800 },
	4388	+ { 0x5401e, 0x16 },
	4389	+ { 0x5401f, 0x84 },
	4390	+ { 0x54020, 0x33 },
	4391	+ { 0x54021, 0x4866 },
	4392	+ { 0x54022, 0x4800 },
	4393	+ { 0x54024, 0x16 },
	4394	+ { 0x5402b, 0x1000 },
	4395	+ { 0x5402c, 0x3 },
	4396	+ { 0x54032, 0x8400 },
	4397	+ { 0x54033, 0x3300 },
	4398	+ { 0x54034, 0x6600 },
	4399	+ { 0x54035, 0x48 },
	4400	+ { 0x54036, 0x48 },
	4401	+ { 0x54037, 0x1600 },
	4402	+ { 0x54038, 0x8400 },
	4403	+ { 0x54039, 0x3300 },
	4404	+ { 0x5403a, 0x6600 },
	4405	+ { 0x5403b, 0x48 },
	4406	+ { 0x5403c, 0x48 },
	4407	+ { 0x5403d, 0x1600 },
	4408	+ { 0xd0000, 0x1 },
	4409	+};
	4410	+
	4411	+
	4412	+/* P2 message block paremeter for training firmware */
	4413	+struct dram_cfg_param ddr_fsp2_cfg[] = {
	4414	+ { 0xd0000, 0x0 },
	4415	+ { 0x54002, 0x102 },
	4416	+ { 0x54003, 0x64 },
	4417	+ { 0x54004, 0x2 },
	4418	+ { 0x54005, 0x2228 },
	4419	+ { 0x54006, 0x14 },
	4420	+ { 0x54008, 0x121f },
	4421	+ { 0x54009, 0xc8 },
	4422	+ { 0x5400b, 0x2 },
	4423	+ { 0x5400f, 0x100 },
	4424	+ { 0x54012, 0x310 },
	4425	+ { 0x54019, 0x84 },
	4426	+ { 0x5401a, 0x33 },
	4427	+ { 0x5401b, 0x4866 },
	4428	+ { 0x5401c, 0x4800 },
	4429	+ { 0x5401e, 0x16 },
	4430	+ { 0x5401f, 0x84 },
	4431	+ { 0x54020, 0x33 },
	4432	+ { 0x54021, 0x4866 },
	4433	+ { 0x54022, 0x4800 },
	4434	+ { 0x54024, 0x16 },
	4435	+ { 0x5402b, 0x1000 },
	4436	+ { 0x5402c, 0x3 },
	4437	+ { 0x54032, 0x8400 },
	4438	+ { 0x54033, 0x3300 },
	4439	+ { 0x54034, 0x6600 },
	4440	+ { 0x54035, 0x48 },
	4441	+ { 0x54036, 0x48 },
	4442	+ { 0x54037, 0x1600 },
	4443	+ { 0x54038, 0x8400 },
	4444	+ { 0x54039, 0x3300 },
	4445	+ { 0x5403a, 0x6600 },
	4446	+ { 0x5403b, 0x48 },
	4447	+ { 0x5403c, 0x48 },
	4448	+ { 0x5403d, 0x1600 },
	4449	+ { 0xd0000, 0x1 },
	4450	+};
	4451	+
	4452	+
	4453	+/* P0 2D message block paremeter for training firmware */
	4454	+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
	4455	+ { 0xd0000, 0x0 },
	4456	+ { 0x54003, 0xc80 },
	4457	+ { 0x54004, 0x2 },
	4458	+ { 0x54005, 0x2228 },
	4459	+ { 0x54006, 0x14 },
	4460	+ { 0x54008, 0x61 },
	4461	+ { 0x54009, 0xc8 },
	4462	+ { 0x5400b, 0x2 },
	4463	+ { 0x5400d, 0x100 },
	4464	+ { 0x5400f, 0x100 },
	4465	+ { 0x54010, 0x1f7f },
	4466	+ { 0x54012, 0x310 },
	4467	+ { 0x54019, 0x2dd4 },
	4468	+ { 0x5401a, 0x33 },
	4469	+ { 0x5401b, 0x4866 },
	4470	+ { 0x5401c, 0x4800 },
	4471	+ { 0x5401e, 0x16 },
	4472	+ { 0x5401f, 0x2dd4 },
	4473	+ { 0x54020, 0x33 },
	4474	+ { 0x54021, 0x4866 },
	4475	+ { 0x54022, 0x4800 },
	4476	+ { 0x54024, 0x16 },
	4477	+ { 0x5402b, 0x1000 },
	4478	+ { 0x5402c, 0x3 },
	4479	+ { 0x54032, 0xd400 },
	4480	+ { 0x54033, 0x332d },
	4481	+ { 0x54034, 0x6600 },
	4482	+ { 0x54035, 0x48 },
	4483	+ { 0x54036, 0x48 },
	4484	+ { 0x54037, 0x1600 },
	4485	+ { 0x54038, 0xd400 },
	4486	+ { 0x54039, 0x332d },
	4487	+ { 0x5403a, 0x6600 },
	4488	+ { 0x5403b, 0x48 },
	4489	+ { 0x5403c, 0x48 },
	4490	+ { 0x5403d, 0x1600 },
	4491	+ { 0xd0000, 0x1 },
	4492	+};
	4493	+
	4494	+/* DRAM PHY init engine image */
	4495	+struct dram_cfg_param ddr_phy_pie[] = {
	4496	+ { 0xd0000, 0x0 },
	4497	+ { 0x90000, 0x10 },
	4498	+ { 0x90001, 0x400 },
	4499	+ { 0x90002, 0x10e },
	4500	+ { 0x90003, 0x0 },
	4501	+ { 0x90004, 0x0 },
	4502	+ { 0x90005, 0x8 },
	4503	+ { 0x90029, 0xb },
	4504	+ { 0x9002a, 0x480 },
	4505	+ { 0x9002b, 0x109 },
	4506	+ { 0x9002c, 0x8 },
	4507	+ { 0x9002d, 0x448 },
	4508	+ { 0x9002e, 0x139 },
	4509	+ { 0x9002f, 0x8 },
	4510	+ { 0x90030, 0x478 },
	4511	+ { 0x90031, 0x109 },
	4512	+ { 0x90032, 0x0 },
	4513	+ { 0x90033, 0xe8 },
	4514	+ { 0x90034, 0x109 },
	4515	+ { 0x90035, 0x2 },
	4516	+ { 0x90036, 0x10 },
	4517	+ { 0x90037, 0x139 },
	4518	+ { 0x90038, 0xb },
	4519	+ { 0x90039, 0x7c0 },
	4520	+ { 0x9003a, 0x139 },
	4521	+ { 0x9003b, 0x44 },
	4522	+ { 0x9003c, 0x633 },
	4523	+ { 0x9003d, 0x159 },
	4524	+ { 0x9003e, 0x14f },
	4525	+ { 0x9003f, 0x630 },
	4526	+ { 0x90040, 0x159 },
	4527	+ { 0x90041, 0x47 },
	4528	+ { 0x90042, 0x633 },
	4529	+ { 0x90043, 0x149 },
	4530	+ { 0x90044, 0x4f },
	4531	+ { 0x90045, 0x633 },
	4532	+ { 0x90046, 0x179 },
	4533	+ { 0x90047, 0x8 },
	4534	+ { 0x90048, 0xe0 },
	4535	+ { 0x90049, 0x109 },
	4536	+ { 0x9004a, 0x0 },
	4537	+ { 0x9004b, 0x7c8 },
	4538	+ { 0x9004c, 0x109 },
	4539	+ { 0x9004d, 0x0 },
	4540	+ { 0x9004e, 0x1 },
	4541	+ { 0x9004f, 0x8 },
	4542	+ { 0x90050, 0x0 },
	4543	+ { 0x90051, 0x45a },
	4544	+ { 0x90052, 0x9 },
	4545	+ { 0x90053, 0x0 },
	4546	+ { 0x90054, 0x448 },
	4547	+ { 0x90055, 0x109 },
	4548	+ { 0x90056, 0x40 },
	4549	+ { 0x90057, 0x633 },
	4550	+ { 0x90058, 0x179 },
	4551	+ { 0x90059, 0x1 },
	4552	+ { 0x9005a, 0x618 },
	4553	+ { 0x9005b, 0x109 },
	4554	+ { 0x9005c, 0x40c0 },
	4555	+ { 0x9005d, 0x633 },
	4556	+ { 0x9005e, 0x149 },
	4557	+ { 0x9005f, 0x8 },
	4558	+ { 0x90060, 0x4 },
	4559	+ { 0x90061, 0x48 },
	4560	+ { 0x90062, 0x4040 },
	4561	+ { 0x90063, 0x633 },
	4562	+ { 0x90064, 0x149 },
	4563	+ { 0x90065, 0x0 },
	4564	+ { 0x90066, 0x4 },
	4565	+ { 0x90067, 0x48 },
	4566	+ { 0x90068, 0x40 },
	4567	+ { 0x90069, 0x633 },
	4568	+ { 0x9006a, 0x149 },
	4569	+ { 0x9006b, 0x10 },
	4570	+ { 0x9006c, 0x4 },
	4571	+ { 0x9006d, 0x18 },
	4572	+ { 0x9006e, 0x0 },
	4573	+ { 0x9006f, 0x4 },
	4574	+ { 0x90070, 0x78 },
	4575	+ { 0x90071, 0x549 },
	4576	+ { 0x90072, 0x633 },
	4577	+ { 0x90073, 0x159 },
	4578	+ { 0x90074, 0xd49 },
	4579	+ { 0x90075, 0x633 },
	4580	+ { 0x90076, 0x159 },
	4581	+ { 0x90077, 0x94a },
	4582	+ { 0x90078, 0x633 },
	4583	+ { 0x90079, 0x159 },
	4584	+ { 0x9007a, 0x441 },
	4585	+ { 0x9007b, 0x633 },
	4586	+ { 0x9007c, 0x149 },
	4587	+ { 0x9007d, 0x42 },
	4588	+ { 0x9007e, 0x633 },
	4589	+ { 0x9007f, 0x149 },
	4590	+ { 0x90080, 0x1 },
	4591	+ { 0x90081, 0x633 },
	4592	+ { 0x90082, 0x149 },
	4593	+ { 0x90083, 0x0 },
	4594	+ { 0x90084, 0xe0 },
	4595	+ { 0x90085, 0x109 },
	4596	+ { 0x90086, 0xa },
	4597	+ { 0x90087, 0x10 },
	4598	+ { 0x90088, 0x109 },
	4599	+ { 0x90089, 0x9 },
	4600	+ { 0x9008a, 0x3c0 },
	4601	+ { 0x9008b, 0x149 },
	4602	+ { 0x9008c, 0x9 },
	4603	+ { 0x9008d, 0x3c0 },
	4604	+ { 0x9008e, 0x159 },
	4605	+ { 0x9008f, 0x18 },
	4606	+ { 0x90090, 0x10 },
	4607	+ { 0x90091, 0x109 },
	4608	+ { 0x90092, 0x0 },
	4609	+ { 0x90093, 0x3c0 },
	4610	+ { 0x90094, 0x109 },
	4611	+ { 0x90095, 0x18 },
	4612	+ { 0x90096, 0x4 },
	4613	+ { 0x90097, 0x48 },
	4614	+ { 0x90098, 0x18 },
	4615	+ { 0x90099, 0x4 },
	4616	+ { 0x9009a, 0x58 },
	4617	+ { 0x9009b, 0xb },
	4618	+ { 0x9009c, 0x10 },
	4619	+ { 0x9009d, 0x109 },
	4620	+ { 0x9009e, 0x1 },
	4621	+ { 0x9009f, 0x10 },
	4622	+ { 0x900a0, 0x109 },
	4623	+ { 0x900a1, 0x5 },
	4624	+ { 0x900a2, 0x7c0 },
	4625	+ { 0x900a3, 0x109 },
	4626	+ { 0x40000, 0x811 },
	4627	+ { 0x40020, 0x880 },
	4628	+ { 0x40040, 0x0 },
	4629	+ { 0x40060, 0x0 },
	4630	+ { 0x40001, 0x4008 },
	4631	+ { 0x40021, 0x83 },
	4632	+ { 0x40041, 0x4f },
	4633	+ { 0x40061, 0x0 },
	4634	+ { 0x40002, 0x4040 },
	4635	+ { 0x40022, 0x83 },
	4636	+ { 0x40042, 0x51 },
	4637	+ { 0x40062, 0x0 },
	4638	+ { 0x40003, 0x811 },
	4639	+ { 0x40023, 0x880 },
	4640	+ { 0x40043, 0x0 },
	4641	+ { 0x40063, 0x0 },
	4642	+ { 0x40004, 0x720 },
	4643	+ { 0x40024, 0xf },
	4644	+ { 0x40044, 0x1740 },
	4645	+ { 0x40064, 0x0 },
	4646	+ { 0x40005, 0x16 },
	4647	+ { 0x40025, 0x83 },
	4648	+ { 0x40045, 0x4b },
	4649	+ { 0x40065, 0x0 },
	4650	+ { 0x40006, 0x716 },
	4651	+ { 0x40026, 0xf },
	4652	+ { 0x40046, 0x2001 },
	4653	+ { 0x40066, 0x0 },
	4654	+ { 0x40007, 0x716 },
	4655	+ { 0x40027, 0xf },
	4656	+ { 0x40047, 0x2800 },
	4657	+ { 0x40067, 0x0 },
	4658	+ { 0x40008, 0x716 },
	4659	+ { 0x40028, 0xf },
	4660	+ { 0x40048, 0xf00 },
	4661	+ { 0x40068, 0x0 },
	4662	+ { 0x40009, 0x720 },
	4663	+ { 0x40029, 0xf },
	4664	+ { 0x40049, 0x1400 },
	4665	+ { 0x40069, 0x0 },
	4666	+ { 0x4000a, 0xe08 },
	4667	+ { 0x4002a, 0xc15 },
	4668	+ { 0x4004a, 0x0 },
	4669	+ { 0x4006a, 0x0 },
	4670	+ { 0x4000b, 0x625 },
	4671	+ { 0x4002b, 0x15 },
	4672	+ { 0x4004b, 0x0 },
	4673	+ { 0x4006b, 0x0 },
	4674	+ { 0x4000c, 0x4028 },
	4675	+ { 0x4002c, 0x80 },
	4676	+ { 0x4004c, 0x0 },
	4677	+ { 0x4006c, 0x0 },
	4678	+ { 0x4000d, 0xe08 },
	4679	+ { 0x4002d, 0xc1a },
	4680	+ { 0x4004d, 0x0 },
	4681	+ { 0x4006d, 0x0 },
	4682	+ { 0x4000e, 0x625 },
	4683	+ { 0x4002e, 0x1a },
	4684	+ { 0x4004e, 0x0 },
	4685	+ { 0x4006e, 0x0 },
	4686	+ { 0x4000f, 0x4040 },
	4687	+ { 0x4002f, 0x80 },
	4688	+ { 0x4004f, 0x0 },
	4689	+ { 0x4006f, 0x0 },
	4690	+ { 0x40010, 0x2604 },
	4691	+ { 0x40030, 0x15 },
	4692	+ { 0x40050, 0x0 },
	4693	+ { 0x40070, 0x0 },
	4694	+ { 0x40011, 0x708 },
	4695	+ { 0x40031, 0x5 },
	4696	+ { 0x40051, 0x0 },
	4697	+ { 0x40071, 0x2002 },
	4698	+ { 0x40012, 0x8 },
	4699	+ { 0x40032, 0x80 },
	4700	+ { 0x40052, 0x0 },
	4701	+ { 0x40072, 0x0 },
	4702	+ { 0x40013, 0x2604 },
	4703	+ { 0x40033, 0x1a },
	4704	+ { 0x40053, 0x0 },
	4705	+ { 0x40073, 0x0 },
	4706	+ { 0x40014, 0x708 },
	4707	+ { 0x40034, 0xa },
	4708	+ { 0x40054, 0x0 },
	4709	+ { 0x40074, 0x2002 },
	4710	+ { 0x40015, 0x4040 },
	4711	+ { 0x40035, 0x80 },
	4712	+ { 0x40055, 0x0 },
	4713	+ { 0x40075, 0x0 },
	4714	+ { 0x40016, 0x60a },
	4715	+ { 0x40036, 0x15 },
	4716	+ { 0x40056, 0x1200 },
	4717	+ { 0x40076, 0x0 },
	4718	+ { 0x40017, 0x61a },
	4719	+ { 0x40037, 0x15 },
	4720	+ { 0x40057, 0x1300 },
	4721	+ { 0x40077, 0x0 },
	4722	+ { 0x40018, 0x60a },
	4723	+ { 0x40038, 0x1a },
	4724	+ { 0x40058, 0x1200 },
	4725	+ { 0x40078, 0x0 },
	4726	+ { 0x40019, 0x642 },
	4727	+ { 0x40039, 0x1a },
	4728	+ { 0x40059, 0x1300 },
	4729	+ { 0x40079, 0x0 },
	4730	+ { 0x4001a, 0x4808 },
	4731	+ { 0x4003a, 0x880 },
	4732	+ { 0x4005a, 0x0 },
	4733	+ { 0x4007a, 0x0 },
	4734	+ { 0x900a4, 0x0 },
	4735	+ { 0x900a5, 0x790 },
	4736	+ { 0x900a6, 0x11a },
	4737	+ { 0x900a7, 0x8 },
	4738	+ { 0x900a8, 0x7aa },
	4739	+ { 0x900a9, 0x2a },
	4740	+ { 0x900aa, 0x10 },
	4741	+ { 0x900ab, 0x7b2 },
	4742	+ { 0x900ac, 0x2a },
	4743	+ { 0x900ad, 0x0 },
	4744	+ { 0x900ae, 0x7c8 },
	4745	+ { 0x900af, 0x109 },
	4746	+ { 0x900b0, 0x10 },
	4747	+ { 0x900b1, 0x10 },
	4748	+ { 0x900b2, 0x109 },
	4749	+ { 0x900b3, 0x10 },
	4750	+ { 0x900b4, 0x2a8 },
	4751	+ { 0x900b5, 0x129 },
	4752	+ { 0x900b6, 0x8 },
	4753	+ { 0x900b7, 0x370 },
	4754	+ { 0x900b8, 0x129 },
	4755	+ { 0x900b9, 0xa },
	4756	+ { 0x900ba, 0x3c8 },
	4757	+ { 0x900bb, 0x1a9 },
	4758	+ { 0x900bc, 0xc },
	4759	+ { 0x900bd, 0x408 },
	4760	+ { 0x900be, 0x199 },
	4761	+ { 0x900bf, 0x14 },
	4762	+ { 0x900c0, 0x790 },
	4763	+ { 0x900c1, 0x11a },
	4764	+ { 0x900c2, 0x8 },
	4765	+ { 0x900c3, 0x4 },
	4766	+ { 0x900c4, 0x18 },
	4767	+ { 0x900c5, 0xe },
	4768	+ { 0x900c6, 0x408 },
	4769	+ { 0x900c7, 0x199 },
	4770	+ { 0x900c8, 0x8 },
	4771	+ { 0x900c9, 0x8568 },
	4772	+ { 0x900ca, 0x108 },
	4773	+ { 0x900cb, 0x18 },
	4774	+ { 0x900cc, 0x790 },
	4775	+ { 0x900cd, 0x16a },
	4776	+ { 0x900ce, 0x8 },
	4777	+ { 0x900cf, 0x1d8 },
	4778	+ { 0x900d0, 0x169 },
	4779	+ { 0x900d1, 0x10 },
	4780	+ { 0x900d2, 0x8558 },
	4781	+ { 0x900d3, 0x168 },
	4782	+ { 0x900d4, 0x70 },
	4783	+ { 0x900d5, 0x788 },
	4784	+ { 0x900d6, 0x16a },
	4785	+ { 0x900d7, 0x1ff8 },
	4786	+ { 0x900d8, 0x85a8 },
	4787	+ { 0x900d9, 0x1e8 },
	4788	+ { 0x900da, 0x50 },
	4789	+ { 0x900db, 0x798 },
	4790	+ { 0x900dc, 0x16a },
	4791	+ { 0x900dd, 0x60 },
	4792	+ { 0x900de, 0x7a0 },
	4793	+ { 0x900df, 0x16a },
	4794	+ { 0x900e0, 0x8 },
	4795	+ { 0x900e1, 0x8310 },
	4796	+ { 0x900e2, 0x168 },
	4797	+ { 0x900e3, 0x8 },
	4798	+ { 0x900e4, 0xa310 },
	4799	+ { 0x900e5, 0x168 },
	4800	+ { 0x900e6, 0xa },
	4801	+ { 0x900e7, 0x408 },
	4802	+ { 0x900e8, 0x169 },
	4803	+ { 0x900e9, 0x6e },
	4804	+ { 0x900ea, 0x0 },
	4805	+ { 0x900eb, 0x68 },
	4806	+ { 0x900ec, 0x0 },
	4807	+ { 0x900ed, 0x408 },
	4808	+ { 0x900ee, 0x169 },
	4809	+ { 0x900ef, 0x0 },
	4810	+ { 0x900f0, 0x8310 },
	4811	+ { 0x900f1, 0x168 },
	4812	+ { 0x900f2, 0x0 },
	4813	+ { 0x900f3, 0xa310 },
	4814	+ { 0x900f4, 0x168 },
	4815	+ { 0x900f5, 0x1ff8 },
	4816	+ { 0x900f6, 0x85a8 },
	4817	+ { 0x900f7, 0x1e8 },
	4818	+ { 0x900f8, 0x68 },
	4819	+ { 0x900f9, 0x798 },
	4820	+ { 0x900fa, 0x16a },
	4821	+ { 0x900fb, 0x78 },
	4822	+ { 0x900fc, 0x7a0 },
	4823	+ { 0x900fd, 0x16a },
	4824	+ { 0x900fe, 0x68 },
	4825	+ { 0x900ff, 0x790 },
	4826	+ { 0x90100, 0x16a },
	4827	+ { 0x90101, 0x8 },
	4828	+ { 0x90102, 0x8b10 },
	4829	+ { 0x90103, 0x168 },
	4830	+ { 0x90104, 0x8 },
	4831	+ { 0x90105, 0xab10 },
	4832	+ { 0x90106, 0x168 },
	4833	+ { 0x90107, 0xa },
	4834	+ { 0x90108, 0x408 },
	4835	+ { 0x90109, 0x169 },
	4836	+ { 0x9010a, 0x58 },
	4837	+ { 0x9010b, 0x0 },
	4838	+ { 0x9010c, 0x68 },
	4839	+ { 0x9010d, 0x0 },
	4840	+ { 0x9010e, 0x408 },
	4841	+ { 0x9010f, 0x169 },
	4842	+ { 0x90110, 0x0 },
	4843	+ { 0x90111, 0x8b10 },
	4844	+ { 0x90112, 0x168 },
	4845	+ { 0x90113, 0x1 },
	4846	+ { 0x90114, 0xab10 },
	4847	+ { 0x90115, 0x168 },
	4848	+ { 0x90116, 0x0 },
	4849	+ { 0x90117, 0x1d8 },
	4850	+ { 0x90118, 0x169 },
	4851	+ { 0x90119, 0x80 },
	4852	+ { 0x9011a, 0x790 },
	4853	+ { 0x9011b, 0x16a },
	4854	+ { 0x9011c, 0x18 },
	4855	+ { 0x9011d, 0x7aa },
	4856	+ { 0x9011e, 0x6a },
	4857	+ { 0x9011f, 0xa },
	4858	+ { 0x90120, 0x0 },
	4859	+ { 0x90121, 0x1e9 },
	4860	+ { 0x90122, 0x8 },
	4861	+ { 0x90123, 0x8080 },
	4862	+ { 0x90124, 0x108 },
	4863	+ { 0x90125, 0xf },
	4864	+ { 0x90126, 0x408 },
	4865	+ { 0x90127, 0x169 },
	4866	+ { 0x90128, 0xc },
	4867	+ { 0x90129, 0x0 },
	4868	+ { 0x9012a, 0x68 },
	4869	+ { 0x9012b, 0x9 },
	4870	+ { 0x9012c, 0x0 },
	4871	+ { 0x9012d, 0x1a9 },
	4872	+ { 0x9012e, 0x0 },
	4873	+ { 0x9012f, 0x408 },
	4874	+ { 0x90130, 0x169 },
	4875	+ { 0x90131, 0x0 },
	4876	+ { 0x90132, 0x8080 },
	4877	+ { 0x90133, 0x108 },
	4878	+ { 0x90134, 0x8 },
	4879	+ { 0x90135, 0x7aa },
	4880	+ { 0x90136, 0x6a },
	4881	+ { 0x90137, 0x0 },
	4882	+ { 0x90138, 0x8568 },
	4883	+ { 0x90139, 0x108 },
	4884	+ { 0x9013a, 0xb7 },
	4885	+ { 0x9013b, 0x790 },
	4886	+ { 0x9013c, 0x16a },
	4887	+ { 0x9013d, 0x1f },
	4888	+ { 0x9013e, 0x0 },
	4889	+ { 0x9013f, 0x68 },
	4890	+ { 0x90140, 0x8 },
	4891	+ { 0x90141, 0x8558 },
	4892	+ { 0x90142, 0x168 },
	4893	+ { 0x90143, 0xf },
	4894	+ { 0x90144, 0x408 },
	4895	+ { 0x90145, 0x169 },
	4896	+ { 0x90146, 0xd },
	4897	+ { 0x90147, 0x0 },
	4898	+ { 0x90148, 0x68 },
	4899	+ { 0x90149, 0x0 },
	4900	+ { 0x9014a, 0x408 },
	4901	+ { 0x9014b, 0x169 },
	4902	+ { 0x9014c, 0x0 },
	4903	+ { 0x9014d, 0x8558 },
	4904	+ { 0x9014e, 0x168 },
	4905	+ { 0x9014f, 0x8 },
	4906	+ { 0x90150, 0x3c8 },
	4907	+ { 0x90151, 0x1a9 },
	4908	+ { 0x90152, 0x3 },
	4909	+ { 0x90153, 0x370 },
	4910	+ { 0x90154, 0x129 },
	4911	+ { 0x90155, 0x20 },
	4912	+ { 0x90156, 0x2aa },
	4913	+ { 0x90157, 0x9 },
	4914	+ { 0x90158, 0x8 },
	4915	+ { 0x90159, 0xe8 },
	4916	+ { 0x9015a, 0x109 },
	4917	+ { 0x9015b, 0x0 },
	4918	+ { 0x9015c, 0x8140 },
	4919	+ { 0x9015d, 0x10c },
	4920	+ { 0x9015e, 0x10 },
	4921	+ { 0x9015f, 0x8138 },
	4922	+ { 0x90160, 0x104 },
	4923	+ { 0x90161, 0x8 },
	4924	+ { 0x90162, 0x448 },
	4925	+ { 0x90163, 0x109 },
	4926	+ { 0x90164, 0xf },
	4927	+ { 0x90165, 0x7c0 },
	4928	+ { 0x90166, 0x109 },
	4929	+ { 0x90167, 0x0 },
	4930	+ { 0x90168, 0xe8 },
	4931	+ { 0x90169, 0x109 },
	4932	+ { 0x9016a, 0x47 },
	4933	+ { 0x9016b, 0x630 },
	4934	+ { 0x9016c, 0x109 },
	4935	+ { 0x9016d, 0x8 },
	4936	+ { 0x9016e, 0x618 },
	4937	+ { 0x9016f, 0x109 },
	4938	+ { 0x90170, 0x8 },
	4939	+ { 0x90171, 0xe0 },
	4940	+ { 0x90172, 0x109 },
	4941	+ { 0x90173, 0x0 },
	4942	+ { 0x90174, 0x7c8 },
	4943	+ { 0x90175, 0x109 },
	4944	+ { 0x90176, 0x8 },
	4945	+ { 0x90177, 0x8140 },
	4946	+ { 0x90178, 0x10c },
	4947	+ { 0x90179, 0x0 },
	4948	+ { 0x9017a, 0x478 },
	4949	+ { 0x9017b, 0x109 },
	4950	+ { 0x9017c, 0x0 },
	4951	+ { 0x9017d, 0x1 },
	4952	+ { 0x9017e, 0x8 },
	4953	+ { 0x9017f, 0x8 },
	4954	+ { 0x90180, 0x4 },
	4955	+ { 0x90181, 0x0 },
	4956	+ { 0x90006, 0x8 },
	4957	+ { 0x90007, 0x7c8 },
	4958	+ { 0x90008, 0x109 },
	4959	+ { 0x90009, 0x0 },
	4960	+ { 0x9000a, 0x400 },
	4961	+ { 0x9000b, 0x106 },
	4962	+ { 0xd00e7, 0x400 },
	4963	+ { 0x90017, 0x0 },
	4964	+ { 0x9001f, 0x29 },
	4965	+ { 0x90026, 0x68 },
	4966	+ { 0x400d0, 0x0 },
	4967	+ { 0x400d1, 0x101 },
	4968	+ { 0x400d2, 0x105 },
	4969	+ { 0x400d3, 0x107 },
	4970	+ { 0x400d4, 0x10f },
	4971	+ { 0x400d5, 0x202 },
	4972	+ { 0x400d6, 0x20a },
	4973	+ { 0x400d7, 0x20b },
	4974	+ { 0x2003a, 0x2 },
	4975	+ { 0x200be, 0x3 },
	4976	+ { 0x2000b, 0x64 },
	4977	+ { 0x2000c, 0xc8 },
	4978	+ { 0x2000d, 0x7d0 },
	4979	+ { 0x2000e, 0x2c },
	4980	+ { 0x12000b, 0xc },
	4981	+ { 0x12000c, 0x19 },
	4982	+ { 0x12000d, 0xfa },
	4983	+ { 0x12000e, 0x10 },
	4984	+ { 0x22000b, 0x3 },
	4985	+ { 0x22000c, 0x6 },
	4986	+ { 0x22000d, 0x3e },
	4987	+ { 0x22000e, 0x10 },
	4988	+ { 0x9000c, 0x0 },
	4989	+ { 0x9000d, 0x173 },
	4990	+ { 0x9000e, 0x60 },
	4991	+ { 0x9000f, 0x6110 },
	4992	+ { 0x90010, 0x2152 },
	4993	+ { 0x90011, 0xdfbd },
	4994	+ { 0x90012, 0x2060 },
	4995	+ { 0x90013, 0x6152 },
	4996	+ { 0x20010, 0x5a },
	4997	+ { 0x20011, 0x3 },
	4998	+ { 0x40080, 0xe0 },
	4999	+ { 0x40081, 0x12 },
	5000	+ { 0x40082, 0xe0 },
	5001	+ { 0x40083, 0x12 },
	5002	+ { 0x40084, 0xe0 },
	5003	+ { 0x40085, 0x12 },
	5004	+ { 0x140080, 0xe0 },
	5005	+ { 0x140081, 0x12 },
	5006	+ { 0x140082, 0xe0 },
	5007	+ { 0x140083, 0x12 },
	5008	+ { 0x140084, 0xe0 },
	5009	+ { 0x140085, 0x12 },
	5010	+ { 0x240080, 0xe0 },
	5011	+ { 0x240081, 0x12 },
	5012	+ { 0x240082, 0xe0 },
	5013	+ { 0x240083, 0x12 },
	5014	+ { 0x240084, 0xe0 },
	5015	+ { 0x240085, 0x12 },
	5016	+ { 0x400fd, 0xf },
	5017	+ { 0x10011, 0x1 },
	5018	+ { 0x10012, 0x1 },
	5019	+ { 0x10013, 0x180 },
	5020	+ { 0x10018, 0x1 },
	5021	+ { 0x10002, 0x6209 },
	5022	+ { 0x100b2, 0x1 },
	5023	+ { 0x101b4, 0x1 },
	5024	+ { 0x102b4, 0x1 },
	5025	+ { 0x103b4, 0x1 },
	5026	+ { 0x104b4, 0x1 },
	5027	+ { 0x105b4, 0x1 },
	5028	+ { 0x106b4, 0x1 },
	5029	+ { 0x107b4, 0x1 },
	5030	+ { 0x108b4, 0x1 },
	5031	+ { 0x11011, 0x1 },
	5032	+ { 0x11012, 0x1 },
	5033	+ { 0x11013, 0x180 },
	5034	+ { 0x11018, 0x1 },
	5035	+ { 0x11002, 0x6209 },
	5036	+ { 0x110b2, 0x1 },
	5037	+ { 0x111b4, 0x1 },
	5038	+ { 0x112b4, 0x1 },
	5039	+ { 0x113b4, 0x1 },
	5040	+ { 0x114b4, 0x1 },
	5041	+ { 0x115b4, 0x1 },
	5042	+ { 0x116b4, 0x1 },
	5043	+ { 0x117b4, 0x1 },
	5044	+ { 0x118b4, 0x1 },
	5045	+ { 0x12011, 0x1 },
	5046	+ { 0x12012, 0x1 },
	5047	+ { 0x12013, 0x180 },
	5048	+ { 0x12018, 0x1 },
	5049	+ { 0x12002, 0x6209 },
	5050	+ { 0x120b2, 0x1 },
	5051	+ { 0x121b4, 0x1 },
	5052	+ { 0x122b4, 0x1 },
	5053	+ { 0x123b4, 0x1 },
	5054	+ { 0x124b4, 0x1 },
	5055	+ { 0x125b4, 0x1 },
	5056	+ { 0x126b4, 0x1 },
	5057	+ { 0x127b4, 0x1 },
	5058	+ { 0x128b4, 0x1 },
	5059	+ { 0x13011, 0x1 },
	5060	+ { 0x13012, 0x1 },
	5061	+ { 0x13013, 0x180 },
	5062	+ { 0x13018, 0x1 },
	5063	+ { 0x13002, 0x6209 },
	5064	+ { 0x130b2, 0x1 },
	5065	+ { 0x131b4, 0x1 },
	5066	+ { 0x132b4, 0x1 },
	5067	+ { 0x133b4, 0x1 },
	5068	+ { 0x134b4, 0x1 },
	5069	+ { 0x135b4, 0x1 },
	5070	+ { 0x136b4, 0x1 },
	5071	+ { 0x137b4, 0x1 },
	5072	+ { 0x138b4, 0x1 },
	5073	+ { 0x20089, 0x1 },
	5074	+ { 0x20088, 0x19 },
	5075	+ { 0xc0080, 0x2 },
	5076	+ { 0xd0000, 0x1 }
	5077	+};
	5078	+
	5079	+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
	5080	+ {
	5081	+ /* P0 3200mts 1D */
	5082	+ .drate = 3200,
	5083	+ .fw_type = FW_1D_IMAGE,
	5084	+ .fsp_cfg = ddr_fsp0_cfg,
	5085	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
	5086	+ },
	5087	+ {
	5088	+ /* P1 400mts 1D */
	5089	+ .drate = 400,
	5090	+ .fw_type = FW_1D_IMAGE,
	5091	+ .fsp_cfg = ddr_fsp1_cfg,
	5092	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
	5093	+ },
	5094	+ {
	5095	+ /* P2 100mts 1D */
	5096	+ .drate = 100,
	5097	+ .fw_type = FW_1D_IMAGE,
	5098	+ .fsp_cfg = ddr_fsp2_cfg,
	5099	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
	5100	+ },
	5101	+ {
	5102	+ /* P0 3200mts 2D */
	5103	+ .drate = 3200,
	5104	+ .fw_type = FW_2D_IMAGE,
	5105	+ .fsp_cfg = ddr_fsp0_2d_cfg,
	5106	+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
	5107	+ },
	5108	+};
	5109	+
	5110	+/* ddr timing config params */
	5111	+struct dram_timing_info dram_timing = {
	5112	+ .ddrc_cfg = ddr_ddrc_cfg,
	5113	+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
	5114	+ .ddrphy_cfg = ddr_ddrphy_cfg,
	5115	+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
	5116	+ .fsp_msg = ddr_dram_fsp_msg,
	5117	+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
	5118	+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
	5119	+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
	5120	+ .ddrphy_pie = ddr_phy_pie,
	5121	+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
	5122	+ .fsp_table = { 3200, 400, 100, },
	5123	+};
	5124	diff --git a/board/lingyun/igkboard-imx8mp/spl.c b/board/lingyun/igkboard-imx8mp/spl.c
	5125	new file mode 100644
	5126	index 00000000..362751e2
	5127	--- /dev/null
	5128	+++ b/board/lingyun/igkboard-imx8mp/spl.c
	5129	@@ -0,0 +1,179 @@
	5130	+// SPDX-License-Identifier: GPL-2.0-or-later
	5131	+/*
	5132	+ * Copyright 2018-2019, 2021 NXP
	5133	+ *
	5134	+ */
	5135	+
	5136	+#include <common.h>
	5137	+#include <hang.h>
	5138	+#include <init.h>
	5139	+#include <log.h>
	5140	+#include <spl.h>
	5141	+#include <asm/global_data.h>
	5142	+#include <asm/arch/imx8mp_pins.h>
	5143	+#include <asm/arch/sys_proto.h>
	5144	+#include <asm/mach-imx/boot_mode.h>
	5145	+#include <power/pmic.h>
	5146	+
	5147	+#include <power/pca9450.h>
	5148	+#include <asm/arch/clock.h>
	5149	+#include <dm/uclass.h>
	5150	+#include <dm/device.h>
	5151	+#include <dm/uclass-internal.h>
	5152	+#include <dm/device-internal.h>
	5153	+#include <asm/mach-imx/gpio.h>
	5154	+#include <asm/mach-imx/iomux-v3.h>
	5155	+#include <asm/mach-imx/mxc_i2c.h>
	5156	+#include <fsl_esdhc_imx.h>
	5157	+#include <mmc.h>
	5158	+#include <asm/arch/ddr.h>
	5159	+
	5160	+DECLARE_GLOBAL_DATA_PTR;
	5161	+
	5162	+int spl_board_boot_device(enum boot_device boot_dev_spl)
	5163	+{
	5164	+#ifdef CONFIG_SPL_BOOTROM_SUPPORT
	5165	+ return BOOT_DEVICE_BOOTROM;
	5166	+#else
	5167	+ switch (boot_dev_spl) {
	5168	+ case SD1_BOOT:
	5169	+ case MMC1_BOOT:
	5170	+ case SD2_BOOT:
	5171	+ case MMC2_BOOT:
	5172	+ return BOOT_DEVICE_MMC1;
	5173	+ case SD3_BOOT:
	5174	+ case MMC3_BOOT:
	5175	+ return BOOT_DEVICE_MMC2;
	5176	+ case QSPI_BOOT:
	5177	+ return BOOT_DEVICE_NOR;
	5178	+ case NAND_BOOT:
	5179	+ return BOOT_DEVICE_NAND;
	5180	+ case USB_BOOT:
	5181	+ return BOOT_DEVICE_BOARD;
	5182	+ default:
	5183	+ return BOOT_DEVICE_NONE;
	5184	+ }
	5185	+#endif
	5186	+}
	5187	+
	5188	+void spl_dram_init(void)
	5189	+{
	5190	+ ddr_init(&dram_timing);
	5191	+}
	5192	+
	5193	+void spl_board_init(void)
	5194	+{
	5195	+ arch_misc_init();
	5196	+
	5197	+ /*
	5198	+ * Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does
	5199	+ * not allow to change it. Should set the clock after PMIC
	5200	+ * setting done. Default is 400Mhz (system_pll1_800m with div = 2)
	5201	+ * set by ROM for ND VDD_SOC
	5202	+ */
	5203	+#if defined(CONFIG_IMX8M_LPDDR4) && !defined(CONFIG_IMX8M_VDD_SOC_850MV)
	5204	+ clock_enable(CCGR_GIC, 0);
	5205	+ clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON \| CLK_ROOT_SOURCE_SEL(5));
	5206	+ clock_enable(CCGR_GIC, 1);
	5207	+
	5208	+ puts("Normal Boot\n");
	5209	+#endif
	5210	+}
	5211	+
	5212	+#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
	5213	+int power_init_board(void)
	5214	+{
	5215	+ struct udevice *dev;
	5216	+ int ret;
	5217	+
	5218	+ ret = pmic_get("pmic@25", &dev);
	5219	+ if (ret == -ENODEV) {
	5220	+ puts("No pca9450@25\n");
	5221	+ return 0;
	5222	+ }
	5223	+ if (ret != 0)
	5224	+ return ret;
	5225	+
	5226	+ /* BUCKxOUT_DVS0/1 control BUCK123 output */
	5227	+ pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
	5228	+
	5229	+#ifdef CONFIG_IMX8M_LPDDR4
	5230	+ /*
	5231	+ * increase VDD_SOC to typical value 0.95V before first
	5232	+ * DRAM access, set DVS1 to 0.85v for suspend.
	5233	+ * Enable DVS control through PMIC_STBY_REQ and
	5234	+ * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
	5235	+ */
	5236	+#ifdef CONFIG_IMX8M_VDD_SOC_850MV
	5237	+ /* set DVS0 to 0.85v for special case*/
	5238	+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14);
	5239	+#else
	5240	+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
	5241	+#endif
	5242	+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
	5243	+ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
	5244	+
	5245	+ /* Kernel uses OD/OD freq for SOC */
	5246	+ /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */
	5247	+ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C);
	5248	+#elif defined(CONFIG_IMX8M_DDR4)
	5249	+ /* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */
	5250	+ pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
	5251	+
	5252	+ /* Set NVCC_DRAM to 1.2v for DDR4 */
	5253	+ pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x18);
	5254	+#endif
	5255	+
	5256	+ return 0;
	5257	+}
	5258	+#endif
	5259	+
	5260	+#ifdef CONFIG_SPL_LOAD_FIT
	5261	+int board_fit_config_name_match(const char *name)
	5262	+{
	5263	+ /* Just empty function now - can't decide what to choose */
	5264	+ debug("%s: %s\n", __func__, name);
	5265	+
	5266	+ return 0;
	5267	+}
	5268	+#endif
	5269	+
	5270	+void board_init_f(ulong dummy)
	5271	+{
	5272	+ struct udevice *dev;
	5273	+ int ret;
	5274	+
	5275	+ /* Clear the BSS. */
	5276	+ memset(__bss_start, 0, __bss_end - __bss_start);
	5277	+
	5278	+ arch_cpu_init();
	5279	+
	5280	+ board_early_init_f();
	5281	+
	5282	+ timer_init();
	5283	+
	5284	+ ret = spl_early_init();
	5285	+ if (ret) {
	5286	+ debug("spl_early_init() failed: %d\n", ret);
	5287	+ hang();
	5288	+ }
	5289	+
	5290	+ ret = uclass_get_device_by_name(UCLASS_CLK,
	5291	+ "clock-controller@30380000",
	5292	+ &dev);
	5293	+ if (ret < 0) {
	5294	+ printf("Failed to find clock node. Check device tree\n");
	5295	+ hang();
	5296	+ }
	5297	+
	5298	+ preloader_console_init();
	5299	+
	5300	+ enable_tzc380();
	5301	+
	5302	+ power_init_board();
	5303	+
	5304	+ /* DDR initialization */
	5305	+ spl_dram_init();
	5306	+
	5307	+ board_init_r(NULL, 0);
	5308	+}
	5309	diff --git a/configs/igkboard-imx8mp_defconfig b/configs/igkboard-imx8mp_defconfig
	5310	new file mode 100644
	5311	index 00000000..40c3b634
	5312	--- /dev/null
	5313	+++ b/configs/igkboard-imx8mp_defconfig
	5314	@@ -0,0 +1,199 @@
	5315	+CONFIG_ARM=y
	5316	+CONFIG_ARCH_IMX8M=y
	5317	+CONFIG_TEXT_BASE=0x40200000
	5318	+CONFIG_SYS_MALLOC_LEN=0x2000000
	5319	+CONFIG_SPL_GPIO=y
	5320	+CONFIG_SPL_LIBCOMMON_SUPPORT=y
	5321	+CONFIG_SPL_LIBGENERIC_SUPPORT=y
	5322	+CONFIG_IMX_BOOTAUX=y
	5323	+CONFIG_ENV_SIZE=0x4000
	5324	+CONFIG_ENV_OFFSET=0x700000
	5325	+CONFIG_ENV_SECT_SIZE=0x10000
	5326	+CONFIG_SYS_MEMTEST_START=0x60000000
	5327	+CONFIG_SYS_MEMTEST_END=0xC0000000
	5328	+CONFIG_SYS_I2C_MXC_I2C1=y
	5329	+CONFIG_SYS_I2C_MXC_I2C2=y
	5330	+CONFIG_SYS_I2C_MXC_I2C3=y
	5331	+CONFIG_DM_GPIO=y
	5332	+CONFIG_SPL_TEXT_BASE=0x920000
	5333	+CONFIG_TARGET_IGKBOARD_IMX8MP=y
	5334	+CONFIG_SYS_PROMPT="u-boot=> "
	5335	+CONFIG_SPL_SERIAL=y
	5336	+CONFIG_SPL_DRIVERS_MISC=y
	5337	+CONFIG_SPL=y
	5338	+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
	5339	+CONFIG_SYS_LOAD_ADDR=0x40400000
	5340	+CONFIG_DISTRO_DEFAULTS=y
	5341	+CONFIG_SYS_MONITOR_LEN=524288
	5342	+CONFIG_DEFAULT_DEVICE_TREE="igkboard-imx8mp"
	5343	+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
	5344	+CONFIG_FIT=y
	5345	+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
	5346	+CONFIG_SPL_LOAD_FIT=y
	5347	+# CONFIG_USE_SPL_FIT_GENERATOR is not set
	5348	+CONFIG_REMAKE_ELF=y
	5349	+CONFIG_OF_SYSTEM_SETUP=y
	5350	+CONFIG_DEFAULT_FDT_FILE="igkboard-imx8mp.dtb"
	5351	+CONFIG_ARCH_MISC_INIT=y
	5352	+CONFIG_BOARD_EARLY_INIT_F=y
	5353	+CONFIG_BOARD_LATE_INIT=y
	5354	+CONFIG_SPL_MAX_SIZE=0x26000
	5355	+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
	5356	+CONFIG_SPL_BSS_START_ADDR=0x96e000
	5357	+CONFIG_SPL_BSS_MAX_SIZE=0x2000
	5358	+CONFIG_SPL_BOARD_INIT=y
	5359	+CONFIG_SPL_BOOTROM_SUPPORT=y
	5360	+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
	5361	+CONFIG_SPL_STACK=0x96dff0
	5362	+CONFIG_SYS_SPL_MALLOC=y
	5363	+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
	5364	+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
	5365	+CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
	5366	+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
	5367	+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
	5368	+CONFIG_SPL_I2C=y
	5369	+CONFIG_SPL_POWER=y
	5370	+CONFIG_SPL_WATCHDOG=y
	5371	+CONFIG_SYS_MAXARGS=64
	5372	+CONFIG_SYS_CBSIZE=2048
	5373	+CONFIG_SYS_PBSIZE=2074
	5374	+CONFIG_SYS_BOOTM_LEN=0x2000000
	5375	+CONFIG_NR_DRAM_BANKS=3
	5376	+CONFIG_HUSH_PARSER=y
	5377	+# CONFIG_CMD_EXPORTENV is not set
	5378	+# CONFIG_CMD_IMPORTENV is not set
	5379	+CONFIG_CMD_ERASEENV=y
	5380	+CONFIG_CMD_CRC32=y
	5381	+CONFIG_CRC32_VERIFY=y
	5382	+# CONFIG_BOOTM_NETBSD is not set
	5383	+CONFIG_CMD_CLK=y
	5384	+CONFIG_CMD_FUSE=y
	5385	+CONFIG_CMD_GPIO=y
	5386	+CONFIG_CMD_I2C=y
	5387	+CONFIG_CMD_MMC=y
	5388	+CONFIG_CMD_CACHE=y
	5389	+CONFIG_CMD_REGULATOR=y
	5390	+CONFIG_CMD_MEMTEST=y
	5391	+CONFIG_CMD_EXT2=y
	5392	+CONFIG_CMD_EXT4=y
	5393	+CONFIG_CMD_EXT4_WRITE=y
	5394	+CONFIG_CMD_FAT=y
	5395	+CONFIG_CMD_LED=y
	5396	+CONFIG_CMD_FS_GENERIC=y
	5397	+CONFIG_CMD_USB=y
	5398	+CONFIG_CMD_USB_MASS_STORAGE=y
	5399	+CONFIG_OF_CONTROL=y
	5400	+CONFIG_SPL_OF_CONTROL=y
	5401	+CONFIG_ENV_OVERWRITE=y
	5402	+CONFIG_ENV_IS_NOWHERE=y
	5403	+CONFIG_ENV_IS_IN_MMC=y
	5404	+CONFIG_ENV_IS_IN_NAND=y
	5405	+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
	5406	+CONFIG_SYS_MMC_ENV_DEV=1
	5407	+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
	5408	+CONFIG_USE_ETHPRIME=y
	5409	+CONFIG_ETHPRIME="eth1"
	5410	+CONFIG_SPL_DM=y
	5411	+CONFIG_SPL_CLK_COMPOSITE_CCF=y
	5412	+CONFIG_CLK_COMPOSITE_CCF=y
	5413	+CONFIG_SPL_CLK_IMX8MP=y
	5414	+CONFIG_CLK_IMX8MP=y
	5415	+CONFIG_MXC_GPIO=y
	5416	+CONFIG_DM_PCA953X=y
	5417	+CONFIG_FASTBOOT=y
	5418	+CONFIG_USB_FUNCTION_FASTBOOT=y
	5419	+CONFIG_CMD_FASTBOOT=y
	5420	+CONFIG_ANDROID_BOOT_IMAGE=y
	5421	+CONFIG_FASTBOOT_UUU_SUPPORT=y
	5422	+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
	5423	+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
	5424	+CONFIG_FASTBOOT_FLASH=y
	5425	+CONFIG_DM_I2C=y
	5426	+CONFIG_SYS_I2C_MXC=y
	5427	+CONFIG_LED=y
	5428	+CONFIG_LED_GPIO=y
	5429	+CONFIG_DM_MMC=y
	5430	+CONFIG_EFI_PARTITION=y
	5431	+CONFIG_SUPPORT_EMMC_BOOT=y
	5432	+CONFIG_MMC_IO_VOLTAGE=y
	5433	+CONFIG_MMC_UHS_SUPPORT=y
	5434	+CONFIG_MMC_HS400_ES_SUPPORT=y
	5435	+CONFIG_MMC_HS400_SUPPORT=y
	5436	+CONFIG_FSL_USDHC=y
	5437	+CONFIG_PHY_REALTEK=y
	5438	+CONFIG_DM_ETH_PHY=y
	5439	+CONFIG_PHY_GIGE=y
	5440	+CONFIG_PHY=y
	5441	+CONFIG_PHY_IMX8MQ_USB=y
	5442	+CONFIG_DWC_ETH_QOS=y
	5443	+CONFIG_DWC_ETH_QOS_IMX=y
	5444	+CONFIG_FEC_MXC=y
	5445	+CONFIG_MII=y
	5446	+
	5447	+CONFIG_PINCTRL=y
	5448	+CONFIG_SPL_PINCTRL=y
	5449	+CONFIG_PINCTRL_IMX8M=y
	5450	+CONFIG_POWER_DOMAIN=y
	5451	+CONFIG_IMX8M_POWER_DOMAIN=y
	5452	+CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
	5453	+CONFIG_DM_PMIC=y
	5454	+CONFIG_SPL_DM_PMIC_PCA9450=y
	5455	+CONFIG_DM_REGULATOR=y
	5456	+CONFIG_DM_REGULATOR_FIXED=y
	5457	+CONFIG_DM_REGULATOR_GPIO=y
	5458	+CONFIG_DM_SERIAL=y
	5459	+CONFIG_MXC_UART=y
	5460	+CONFIG_SYSRESET=y
	5461	+CONFIG_SYSRESET_PSCI=y
	5462	+CONFIG_DM_THERMAL=y
	5463	+CONFIG_IMX_TMU=y
	5464	+CONFIG_USB_TCPC=n
	5465	+CONFIG_USB=y
	5466	+CONFIG_USB_GADGET=y
	5467	+CONFIG_USB_STORAGE=y
	5468	+CONFIG_DM_USB=y
	5469	+
	5470	+CONFIG_OF_LIBFDT_OVERLAY=y
	5471	+CONFIG_USB_GADGET_MANUFACTURER="FSL"
	5472	+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
	5473	+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
	5474	+CONFIG_USB_GADGET_DOWNLOAD=y
	5475	+CONFIG_USB_XHCI_HCD=y
	5476	+CONFIG_USB_XHCI_IMX8M=y
	5477	+CONFIG_USB_XHCI_DWC3=y
	5478	+CONFIG_USB_DWC3=y
	5479	+CONFIG_USB_DWC3_GADGET=y
	5480	+
	5481	+CONFIG_OF_BOARD_FIXUP=y
	5482	+CONFIG_OF_BOARD_SETUP=y
	5483	+
	5484	+CONFIG_IMX8M_BLK_CTRL=y
	5485	+CONFIG_VIDEO_IMX_LCDIFV3=y
	5486	+CONFIG_VIDEO_IMX_SEC_DSI=y
	5487	+CONFIG_VIDEO=y
	5488	+CONFIG_BMP_16BPP=y
	5489	+CONFIG_BMP_24BPP=y
	5490	+CONFIG_BMP_32BPP=y
	5491	+CONFIG_VIDEO_LOGO=y
	5492	+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
	5493	+CONFIG_VIDEO_ADV7535=y
	5494	+CONFIG_SYS_WHITE_ON_BLACK=y
	5495	+CONFIG_SPLASH_SCREEN=y
	5496	+CONFIG_SPLASH_SCREEN_ALIGN=y
	5497	+CONFIG_CMD_BMP=y
	5498	+
	5499	+CONFIG_CMD_NAND=y
	5500	+CONFIG_CMD_UBI=y
	5501	+CONFIG_CMD_NAND_TRIMFFS=y
	5502	+CONFIG_MTD_RAW_NAND=y
	5503	+CONFIG_MTD=y
	5504	+CONFIG_DM_MTD=y
	5505	+CONFIG_CMD_MTDPARTS=y
	5506	+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
	5507	+CONFIG_MTDPARTS_SKIP_INVALID=y
	5508	+CONFIG_NAND=y
	5509	+CONFIG_NAND_MXS=y
	5510	+CONFIG_NAND_MXS_DT=y
	5511	+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
	5512	+CONFIG_SYS_NAND_USE_FLASH_BBT=y
	5513	+CONFIG_SYS_NAND_ONFI_DETECTION=y
	5514	diff --git a/include/configs/igkboard-imx8mp.h b/include/configs/igkboard-imx8mp.h
	5515	new file mode 100644
	5516	index 00000000..bc2686b2
	5517	--- /dev/null
	5518	+++ b/include/configs/igkboard-imx8mp.h
	5519	@@ -0,0 +1,189 @@
	5520	+/* SPDX-License-Identifier: GPL-2.0+ */
	5521	+/*
	5522	+ * Copyright 2019 NXP
	5523	+ */
	5524	+
	5525	+#ifndef __IGKBOARD_IMX8MP_H
	5526	+#define __IGKBOARD_IMX8MP_H
	5527	+
	5528	+#include <linux/sizes.h>
	5529	+#include <linux/stringify.h>
	5530	+#include <asm/arch/imx-regs.h>
	5531	+#include "imx_env.h"
	5532	+
	5533	+#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
	5534	+
	5535	+#if defined(CONFIG_CMD_NET)
	5536	+#define CFG_FEC_MXC_PHYADDR 1
	5537	+
	5538	+#define PHY_ANEG_TIMEOUT 20000
	5539	+
	5540	+#endif
	5541	+
	5542	+#ifdef CONFIG_DISTRO_DEFAULTS
	5543	+#define BOOT_TARGET_DEVICES(func) \
	5544	+ func(USB, usb, 0) \
	5545	+ func(MMC, mmc, 1) \
	5546	+ func(MMC, mmc, 2)
	5547	+
	5548	+#include <config_distro_bootcmd.h>
	5549	+#else
	5550	+#define BOOTENV
	5551	+#endif
	5552	+
	5553	+#define JH_ROOT_DTB "imx8mp-evk-revb4-root.dtb"
	5554	+
	5555	+#define JAILHOUSE_ENV \
	5556	+ "jh_clk= \0 " \
	5557	+ "jh_root_dtb=" JH_ROOT_DTB "\0" \
	5558	+ "jh_mmcboot=setenv fdtfile ${jh_root_dtb};" \
	5559	+ "setenv jh_clk clk_ignore_unused mem=1920MB; " \
	5560	+ "if run loadimage; then " \
	5561	+ "run mmcboot; " \
	5562	+ "else run jh_netboot; fi; \0" \
	5563	+ "jh_netboot=setenv fdtfile ${jh_root_dtb}; setenv jh_clk clk_ignore_unused mem=1920MB; run netboot; \0 "
	5564	+
	5565	+#define SR_IR_V2_COMMAND \
	5566	+ "nodes=/busfreq /power-domains /soc@0/caam-sm@100000 /soc@0/bus@30000000/caam_secvio /soc@0/bus@30000000/caam-snvs@30370000 /soc@0/bus@30800000/flexspi_nand@30bb0000 /soc@0/bus@32c00000/mipi_dsi@32e60000 /soc@0/bus@32c00000/lcd-controller@32e80000 /soc@0/bus@32c00000/blk-ctl@32ec0000 /soc@0/bus@30800000/i2c@30a20000/pca9450@25 /soc@0/bus@30800000/i2c@30a30000/adv7535@3d /soc@0/bus@30800000/i2c@30a30000/tcpc@50 /wdt-reboot /mcu_rdc /soc@0/bus@30800000/ethernet@30bf0000 /dsi-host /rm67199_panel /cbtl04gp /binman /vpu_g1@38300000 /vpu_g2@38310000 /vpu_vc8000e@38320000 /vpu_v4l2 /gpu3d@38000000 /gpu2d@38008000 /vipsi@38500000 /mix_gpu_ml \0" \
	5567	+ "sr_ir_v2_cmd=cp.b ${fdtcontroladdr} ${fdt_addr_r} 0x10000;"\
	5568	+ "fdt addr ${fdt_addr_r};"\
	5569	+ "fdt set /soc@0/usb@32f10100/usb@38100000 compatible snps,dwc3;" \
	5570	+ "fdt set /soc@0/usb@32f10108/usb@38200000 compatible snps,dwc3;" \
	5571	+ "for i in ${nodes}; do fdt rm ${i}; done \0"
	5572	+
	5573	+#define CFG_MFG_ENV_SETTINGS \
	5574	+ CFG_MFG_ENV_SETTINGS_DEFAULT \
	5575	+ "initrd_addr=0x43800000\0" \
	5576	+ "initrd_high=0xffffffffffffffff\0" \
	5577	+ "emmc_dev=2\0"\
	5578	+ "sd_dev=1\0"
	5579	+
	5580	+
	5581	+#ifdef CONFIG_NAND_BOOT
	5582	+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)"
	5583	+#endif
	5584	+
	5585	+/* Initial environment variables */
	5586	+#if defined(CONFIG_NAND_BOOT)
	5587	+#define CFG_EXTRA_ENV_SETTINGS \
	5588	+ CFG_MFG_ENV_SETTINGS \
	5589	+ "splashimage=0x50000000\0" \
	5590	+ "fdt_addr_r=0x43000000\0" \
	5591	+ "fdt_addr=0x43000000\0" \
	5592	+ "fdt_high=0xffffffffffffffff\0" \
	5593	+ "mtdparts=" MFG_NAND_PARTITION "\0" \
	5594	+ "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
	5595	+ "bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=nandrootfs " \
	5596	+ "root=ubi0:nandrootfs rootfstype=ubifs " \
	5597	+ MFG_NAND_PARTITION \
	5598	+ "\0" \
	5599	+ "bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\
	5600	+ "nand read ${fdt_addr_r} 0x7000000 0x100000;"\
	5601	+ "booti ${loadaddr} - ${fdt_addr_r}"
	5602	+
	5603	+#else
	5604	+#define CFG_EXTRA_ENV_SETTINGS \
	5605	+ CFG_MFG_ENV_SETTINGS \
	5606	+ JAILHOUSE_ENV \
	5607	+ SR_IR_V2_COMMAND \
	5608	+ BOOTENV \
	5609	+ "prepare_mcore=setenv mcore_clk clk-imx8mp.mcore_booted;\0" \
	5610	+ "scriptaddr=0x43500000\0" \
	5611	+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
	5612	+ "bsp_script=boot.scr\0" \
	5613	+ "image=Image\0" \
	5614	+ "splashimage=0x50000000\0" \
	5615	+ "console=ttymxc1,115200\0" \
	5616	+ "fdt_addr_r=0x43000000\0" \
	5617	+ "fdt_addr=0x43000000\0" \
	5618	+ "boot_fdt=try\0" \
	5619	+ "fdt_high=0xffffffffffffffff\0" \
	5620	+ "boot_fit=no\0" \
	5621	+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
	5622	+ "bootm_size=0x10000000\0" \
	5623	+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
	5624	+ "mmcpart=1\0" \
	5625	+ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
	5626	+ "mmcautodetect=yes\0" \
	5627	+ "mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}\0 " \
	5628	+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \
	5629	+ "bootscript=echo Running bootscript from mmc ...; " \
	5630	+ "source\0" \
	5631	+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
	5632	+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
	5633	+ "mmcboot=echo Booting from mmc ...; " \
	5634	+ "run mmcargs; " \
	5635	+ "if test ${boot_fit} = yes \|\| test ${boot_fit} = try; then " \
	5636	+ "bootm ${loadaddr}; " \
	5637	+ "else " \
	5638	+ "if run loadfdt; then " \
	5639	+ "booti ${loadaddr} - ${fdt_addr_r}; " \
	5640	+ "else " \
	5641	+ "echo WARN: Cannot load the DT; " \
	5642	+ "fi; " \
	5643	+ "fi;\0" \
	5644	+ "netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} " \
	5645	+ "root=/dev/nfs " \
	5646	+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
	5647	+ "netboot=echo Booting from net ...; " \
	5648	+ "run netargs; " \
	5649	+ "if test ${ip_dyn} = yes; then " \
	5650	+ "setenv get_cmd dhcp; " \
	5651	+ "else " \
	5652	+ "setenv get_cmd tftp; " \
	5653	+ "fi; " \
	5654	+ "${get_cmd} ${loadaddr} ${image}; " \
	5655	+ "if test ${boot_fit} = yes \|\| test ${boot_fit} = try; then " \
	5656	+ "bootm ${loadaddr}; " \
	5657	+ "else " \
	5658	+ "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
	5659	+ "booti ${loadaddr} - ${fdt_addr_r}; " \
	5660	+ "else " \
	5661	+ "echo WARN: Cannot load the DT; " \
	5662	+ "fi; " \
	5663	+ "fi;\0" \
	5664	+ "bsp_bootcmd=echo Running BSP bootcmd ...; " \
	5665	+ "mmc dev ${mmcdev}; if mmc rescan; then " \
	5666	+ "if run loadbootscript; then " \
	5667	+ "run bootscript; " \
	5668	+ "else " \
	5669	+ "if run loadimage; then " \
	5670	+ "run mmcboot; " \
	5671	+ "else run netboot; " \
	5672	+ "fi; " \
	5673	+ "fi; " \
	5674	+ "fi;"
	5675	+#endif
	5676	+
	5677	+/* Link Definitions */
	5678	+
	5679	+#define CFG_SYS_INIT_RAM_ADDR 0x40000000
	5680	+#define CFG_SYS_INIT_RAM_SIZE 0x80000
	5681	+
	5682	+
	5683	+/* Totally 6GB DDR */
	5684	+#define CFG_SYS_SDRAM_BASE 0x40000000
	5685	+#define PHYS_SDRAM 0x40000000
	5686	+#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
	5687	+#define PHYS_SDRAM_2 0x100000000
	5688	+#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK
	5689	+#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */
	5690	+#else
	5691	+#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
	5692	+#endif
	5693	+
	5694	+#define CFG_MXC_UART_BASE UART2_BASE_ADDR
	5695	+
	5696	+#define CFG_SYS_NAND_BASE 0x20000000
	5697	+
	5698	+#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK
	5699	+#define CFG_SYS_FSL_USDHC_NUM 1
	5700	+#else
	5701	+#define CFG_SYS_FSL_USDHC_NUM 2
	5702	+#endif
	5703	+
	5704	+#ifdef CONFIG_ANDROID_SUPPORT
	5705	+#include "imx8mp_evk_android.h"
	5706	+#endif
	5707	+
	5708	+#endif