| commit | author | age | ||
| d3809d | 1 | diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile |
| G | 2 | index 8b65ac0b..a9828526 100644 |
| 3 | --- a/arch/arm/dts/Makefile | |
| 4 | +++ b/arch/arm/dts/Makefile | |
| 5 | @@ -936,6 +936,7 @@ dtb-$(CONFIG_MX6UL) += \ | |
| 6 | imx6ull-kontron-bl.dtb | |
| 7 | ||
| 8 | dtb-$(CONFIG_MX6ULL) += \ | |
| 9 | + igkboard-imx6ull.dtb \ | |
| 10 | imx6ull-14x14-ddr3-val.dtb \ | |
| 11 | imx6ull-14x14-ddr3-val-epdc.dtb \ | |
| 12 | imx6ull-14x14-ddr3-val-emmc.dtb \ | |
| 13 | diff --git a/arch/arm/dts/igkboard-imx6ull.dts b/arch/arm/dts/igkboard-imx6ull.dts | |
| 14 | new file mode 100644 | |
| 15 | index 00000000..b87e0155 | |
| 16 | --- /dev/null | |
| 17 | +++ b/arch/arm/dts/igkboard-imx6ull.dts | |
| 18 | @@ -0,0 +1,377 @@ | |
| 19 | +// SPDX-License-Identifier: (GPL-2.0 OR MIT) | |
| 20 | +// | |
| 21 | +// Copyright (C) 2023 LingYun IoT System Studio | |
| 22 | + | |
| 23 | +/dts-v1/; | |
| 24 | + | |
| 25 | +#include "imx6ull.dtsi" | |
| 26 | + | |
| 27 | +/ { | |
| 28 | + model = "LingYun IoT Gateway Kits Board based on i.MX6ULL"; | |
| 29 | + compatible = "lingyun,igkboard-imx6ull", "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; | |
| 30 | + | |
| 31 | + chosen { | |
| 32 | + stdout-path = &uart1; | |
| 33 | + }; | |
| 34 | + | |
| 35 | + memory@80000000 { | |
| 36 | + device_type = "memory"; | |
| 37 | + reg = <0x80000000 0x20000000>; | |
| 38 | + }; | |
| 39 | + | |
| 40 | + reg_sd1_vmmc: regulator-sd1-vmmc { | |
| 41 | + compatible = "regulator-fixed"; | |
| 42 | + regulator-name = "VSD_3V3"; | |
| 43 | + regulator-min-microvolt = <3300000>; | |
| 44 | + regulator-max-microvolt = <3300000>; | |
| 45 | + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; | |
| 46 | + off-on-delay-us = <20000>; | |
| 47 | + enable-active-high; | |
| 48 | + }; | |
| 49 | +}; | |
| 50 | + | |
| 51 | +&fec1 { | |
| 52 | + pinctrl-names = "default"; | |
| 53 | + pinctrl-0 = <&pinctrl_enet1>; | |
| 54 | + phy-mode = "rmii"; | |
| 55 | + phy-handle = <ðphy0>; | |
| 56 | + phy-reset-gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; | |
| 57 | + phy-reset-duration = <50>; | |
| 58 | + phy-reset-post-delay = <15>; | |
| 59 | + status = "okay"; | |
| 60 | +}; | |
| 61 | + | |
| 62 | +&fec2 { | |
| 63 | + pinctrl-names = "default"; | |
| 64 | + pinctrl-0 = <&pinctrl_enet2>; | |
| 65 | + phy-mode = "rmii"; | |
| 66 | + phy-handle = <ðphy1>; | |
| 67 | + phy-reset-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; | |
| 68 | + phy-reset-duration = <50>; | |
| 69 | + phy-reset-post-delay = <15>; | |
| 70 | + status = "okay"; | |
| 71 | + | |
| 72 | + mdio { | |
| 73 | + #address-cells = <1>; | |
| 74 | + #size-cells = <0>; | |
| 75 | + | |
| 76 | + ethphy0: ethernet-phy@0 { | |
| 77 | + reg = <0>; | |
| 78 | + micrel,led-mode = <1>; | |
| 79 | + clocks = <&clks IMX6UL_CLK_ENET_REF>; | |
| 80 | + clock-names = "rmii-ref"; | |
| 81 | + }; | |
| 82 | + | |
| 83 | + ethphy1: ethernet-phy@1 { | |
| 84 | + reg = <1>; | |
| 85 | + micrel,led-mode = <1>; | |
| 86 | + clocks = <&clks IMX6UL_CLK_ENET2_REF>; | |
| 87 | + clock-names = "rmii-ref"; | |
| 88 | + }; | |
| 89 | + }; | |
| 90 | +}; | |
| 91 | + | |
| 92 | +&lcdif { | |
| 93 | + pinctrl-names = "default"; | |
| 94 | + pinctrl-0 = <&pinctrl_lcdif_dat | |
| 95 | + &pinctrl_lcdif_ctrl>; | |
| 96 | + | |
| 97 | + display = <&display0>; | |
| 98 | + status = "okay"; | |
| 99 | + | |
| 100 | + display0: display@0 { | |
| 101 | + bits-per-pixel = <16>; | |
| 102 | + bus-width = <16>; | |
| 103 | + | |
| 104 | + display-timings { | |
| 105 | + native-mode = <&timing0>; | |
| 106 | + timing0: timing0 { | |
| 107 | + clock-frequency = <30000000>; | |
| 108 | + hactive = <800>; | |
| 109 | + vactive = <480>; | |
| 110 | + hfront-porch = <40>; | |
| 111 | + hback-porch = <88>; | |
| 112 | + hsync-len = <48>; | |
| 113 | + vback-porch = <32>; | |
| 114 | + vfront-porch = <13>; | |
| 115 | + vsync-len = <3>; | |
| 116 | + | |
| 117 | + hsync-active = <0>; | |
| 118 | + vsync-active = <0>; | |
| 119 | + de-active = <1>; | |
| 120 | + pixelclk-active = <0>; | |
| 121 | + }; | |
| 122 | + }; | |
| 123 | + }; | |
| 124 | +}; | |
| 125 | + | |
| 126 | +&snvs_poweroff { | |
| 127 | + status = "okay"; | |
| 128 | +}; | |
| 129 | + | |
| 130 | +&uart1 { | |
| 131 | + pinctrl-names = "default"; | |
| 132 | + pinctrl-0 = <&pinctrl_uart1>; | |
| 133 | + status = "okay"; | |
| 134 | +}; | |
| 135 | + | |
| 136 | +&usbotg1 { | |
| 137 | + dr_mode = "otg"; | |
| 138 | + pinctrl-names = "default"; | |
| 139 | + pinctrl-0 = <&pinctrl_usb_otg1>; | |
| 140 | + status = "okay"; | |
| 141 | +}; | |
| 142 | + | |
| 143 | +&usbotg2 { | |
| 144 | + dr_mode = "host"; | |
| 145 | + disable-over-current; | |
| 146 | + status = "okay"; | |
| 147 | +}; | |
| 148 | + | |
| 149 | +&usbphy1 { | |
| 150 | + fsl,tx-d-cal = <106>; | |
| 151 | +}; | |
| 152 | + | |
| 153 | +&usbphy2 { | |
| 154 | + fsl,tx-d-cal = <106>; | |
| 155 | +}; | |
| 156 | + | |
| 157 | +&usdhc1 { | |
| 158 | + pinctrl-names = "default", "state_100mhz", "state_200mhz"; | |
| 159 | + pinctrl-0 = <&pinctrl_usdhc1>; | |
| 160 | + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; | |
| 161 | + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; | |
| 162 | + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; | |
| 163 | + keep-power-in-suspend; | |
| 164 | + wakeup-source; | |
| 165 | + vmmc-supply = <®_sd1_vmmc>; | |
| 166 | + status = "okay"; | |
| 167 | +}; | |
| 168 | + | |
| 169 | +&usdhc2 { | |
| 170 | + pinctrl-names = "default"; | |
| 171 | + pinctrl-0 = <&pinctrl_usdhc2>; | |
| 172 | + no-1-8-v; | |
| 173 | + broken-cd; | |
| 174 | + keep-power-in-suspend; | |
| 175 | + wakeup-source; | |
| 176 | + status = "okay"; | |
| 177 | +}; | |
| 178 | + | |
| 179 | +&wdog1 { | |
| 180 | + pinctrl-names = "default"; | |
| 181 | + pinctrl-0 = <&pinctrl_wdog>; | |
| 182 | + fsl,ext-reset-output; | |
| 183 | +}; | |
| 184 | + | |
| 185 | +&iomuxc { | |
| 186 | + pinctrl-names = "default"; | |
| 187 | + pinctrl-0 = <&pinctrl_extgpio>; | |
| 188 | + | |
| 189 | + pinctrl_extgpio: extgpiogrp { | |
| 190 | + fsl,pins = < | |
| 191 | + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 /* 3# I2C1_SDA */ | |
| 192 | + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x17059 /* 5# I2C1_SCL */ | |
| 193 | + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 /* 7# GPIO */ | |
| 194 | + MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x17059 /* 11# UART3_TX */ | |
| 195 | + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x17059 /* 13# UART4_TX */ | |
| 196 | + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x17059 /* 15# UART4_RX */ | |
| 197 | + MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x17059 /* 19# SPI1_MOSI*/ | |
| 198 | + MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x17059 /* 21# SPI1_MISO*/ | |
| 199 | + MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x17059 /* 23# SPI1_SCLK*/ | |
| 200 | + MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x17059 /* 27# CAN1_TX */ | |
| 201 | + MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x17059 /* 29# CAN1_RX */ | |
| 202 | + MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x17059 /* 31# CAN2_TX */ | |
| 203 | + MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x17059 /* 33# CAN2_RX */ | |
| 204 | + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x17059 /* 35# GPIO */ | |
| 205 | + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059 /* 37# GPIO */ | |
| 206 | + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x17059 /* 8# UART2_TX */ | |
| 207 | + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x17059 /* 10# UART2_RX */ | |
| 208 | + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x17059 /* 12# UART3_RX */ | |
| 209 | + MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x17059 /* 16# UART7_TX */ | |
| 210 | + MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x17059 /* 18# UART7_RX */ | |
| 211 | + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x17059 /* 22# GPIO */ | |
| 212 | + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x17059 /* 24# SPI1_SS0 */ | |
| 213 | + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x17059 /* 26# GPIO */ | |
| 214 | + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* 28# PWM8 */ | |
| 215 | + MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x17059 /* 32# PWM7 */ | |
| 216 | + MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x17059 /* 36# GPIO */ | |
| 217 | + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x17059 /* 38# GPIO */ | |
| 218 | + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x17059 /* 40# GPIO */ | |
| 219 | + >; | |
| 220 | + }; | |
| 221 | + | |
| 222 | + pinctrl_enet1: enet1grp { | |
| 223 | + fsl,pins = < | |
| 224 | + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 | |
| 225 | + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 | |
| 226 | + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 | |
| 227 | + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 | |
| 228 | + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 | |
| 229 | + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 | |
| 230 | + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 | |
| 231 | + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 | |
| 232 | + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10B0 /* ENET1 RESET */ | |
| 233 | + >; | |
| 234 | + }; | |
| 235 | + | |
| 236 | + pinctrl_enet2: enet2grp { | |
| 237 | + fsl,pins = < | |
| 238 | + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 | |
| 239 | + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 | |
| 240 | + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 | |
| 241 | + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 | |
| 242 | + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 | |
| 243 | + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 | |
| 244 | + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 | |
| 245 | + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 | |
| 246 | + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 | |
| 247 | + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 | |
| 248 | + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x10B0 /* ENET2 RESET */ | |
| 249 | + >; | |
| 250 | + }; | |
| 251 | + | |
| 252 | + pinctrl_lcdif_dat: lcdifdatgrp { | |
| 253 | + fsl,pins = < | |
| 254 | + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 | |
| 255 | + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 | |
| 256 | + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 | |
| 257 | + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 | |
| 258 | + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 | |
| 259 | + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 | |
| 260 | + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 | |
| 261 | + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 | |
| 262 | + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 | |
| 263 | + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 | |
| 264 | + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 | |
| 265 | + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 | |
| 266 | + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 | |
| 267 | + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 | |
| 268 | + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 | |
| 269 | + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 | |
| 270 | + >; | |
| 271 | + }; | |
| 272 | + | |
| 273 | + pinctrl_lcdif_ctrl: lcdifctrlgrp { | |
| 274 | + fsl,pins = < | |
| 275 | + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 | |
| 276 | + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 | |
| 277 | + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 | |
| 278 | + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 | |
| 279 | + /* used for lcd reset */ | |
| 280 | + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 | |
| 281 | + >; | |
| 282 | + }; | |
| 283 | + | |
| 284 | + pinctrl_uart1: uart1grp { | |
| 285 | + fsl,pins = < | |
| 286 | + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 | |
| 287 | + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 | |
| 288 | + >; | |
| 289 | + }; | |
| 290 | + | |
| 291 | + pinctrl_usb_otg1: usbotg1grp { | |
| 292 | + fsl,pins = < | |
| 293 | + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 | |
| 294 | + >; | |
| 295 | + }; | |
| 296 | + | |
| 297 | + pinctrl_usdhc1: usdhc1grp { | |
| 298 | + fsl,pins = < | |
| 299 | + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 | |
| 300 | + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 | |
| 301 | + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 | |
| 302 | + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 | |
| 303 | + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 | |
| 304 | + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 | |
| 305 | + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ | |
| 306 | + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ | |
| 307 | + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ | |
| 308 | + >; | |
| 309 | + }; | |
| 310 | + | |
| 311 | + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { | |
| 312 | + fsl,pins = < | |
| 313 | + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 | |
| 314 | + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 | |
| 315 | + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 | |
| 316 | + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 | |
| 317 | + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 | |
| 318 | + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 | |
| 319 | + | |
| 320 | + >; | |
| 321 | + }; | |
| 322 | + | |
| 323 | + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { | |
| 324 | + fsl,pins = < | |
| 325 | + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 | |
| 326 | + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 | |
| 327 | + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 | |
| 328 | + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 | |
| 329 | + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 | |
| 330 | + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 | |
| 331 | + >; | |
| 332 | + }; | |
| 333 | + | |
| 334 | + pinctrl_usdhc2: usdhc2grp { | |
| 335 | + fsl,pins = < | |
| 336 | + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 | |
| 337 | + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 | |
| 338 | + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 | |
| 339 | + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 | |
| 340 | + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 | |
| 341 | + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 | |
| 342 | + >; | |
| 343 | + }; | |
| 344 | + | |
| 345 | + pinctrl_usdhc2_8bit: usdhc2grp_8bit { | |
| 346 | + fsl,pins = < | |
| 347 | + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 | |
| 348 | + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 | |
| 349 | + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 | |
| 350 | + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 | |
| 351 | + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 | |
| 352 | + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 | |
| 353 | + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 | |
| 354 | + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 | |
| 355 | + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 | |
| 356 | + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 | |
| 357 | + >; | |
| 358 | + }; | |
| 359 | + | |
| 360 | + pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { | |
| 361 | + fsl,pins = < | |
| 362 | + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 | |
| 363 | + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 | |
| 364 | + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 | |
| 365 | + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 | |
| 366 | + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 | |
| 367 | + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 | |
| 368 | + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 | |
| 369 | + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 | |
| 370 | + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 | |
| 371 | + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 | |
| 372 | + >; | |
| 373 | + }; | |
| 374 | + | |
| 375 | + pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { | |
| 376 | + fsl,pins = < | |
| 377 | + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 | |
| 378 | + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 | |
| 379 | + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 | |
| 380 | + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 | |
| 381 | + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 | |
| 382 | + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 | |
| 383 | + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 | |
| 384 | + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 | |
| 385 | + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 | |
| 386 | + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 | |
| 387 | + >; | |
| 388 | + }; | |
| 389 | + | |
| 390 | + pinctrl_wdog: wdoggrp { | |
| 391 | + fsl,pins = < | |
| 392 | + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 | |
| 393 | + >; | |
| 394 | + }; | |
| 395 | +}; | |
| 396 | diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig | |
| 397 | index a7a04350..40e21004 100644 | |
| 398 | --- a/arch/arm/mach-imx/mx6/Kconfig | |
| 399 | +++ b/arch/arm/mach-imx/mx6/Kconfig | |
| 400 | @@ -157,6 +157,16 @@ choice | |
| 401 | prompt "MX6 board select" | |
| 402 | optional | |
| 403 | ||
| 404 | +config TARGET_LINGYUN_IGKBOARD_IMX6ULL | |
| 405 | + bool "LingYun i.MX6ULL IoT Gateway Kits Board(igkboard-imx6ull)" | |
| 406 | + depends on MX6ULL | |
| 407 | + select BOARD_LATE_INIT | |
| 408 | + select DM | |
| 409 | + select DM_THERMAL | |
| 410 | + select IMX_MODULE_FUSE | |
| 411 | + select OF_SYSTEM_SETUP | |
| 412 | + imply CMD_DM | |
| 413 | + | |
| 414 | config TARGET_APALIS_IMX6 | |
| 415 | bool "Toradex Apalis iMX6 board" | |
| 416 | depends on MX6Q | |
| 417 | @@ -901,5 +911,6 @@ source "board/udoo/neo/Kconfig" | |
| 418 | source "board/wandboard/Kconfig" | |
| 419 | source "board/BuR/brppt2/Kconfig" | |
| 420 | source "board/out4/o4-imx6ull-nano/Kconfig" | |
| 421 | +source "board/lingyun/igkboard-imx6ull/Kconfig" | |
| 422 | ||
| 423 | endif | |
| 424 | diff --git a/board/lingyun/igkboard-imx6ull/Kconfig b/board/lingyun/igkboard-imx6ull/Kconfig | |
| 425 | new file mode 100644 | |
| 426 | index 00000000..3d2a41bd | |
| 427 | --- /dev/null | |
| 428 | +++ b/board/lingyun/igkboard-imx6ull/Kconfig | |
| 429 | @@ -0,0 +1,14 @@ | |
| 430 | +if TARGET_LINGYUN_IGKBOARD_IMX6ULL | |
| 431 | + | |
| 432 | +config SYS_BOARD | |
| 433 | + default "igkboard-imx6ull" | |
| 434 | + | |
| 435 | +config SYS_VENDOR | |
| 436 | + default "lingyun" | |
| 437 | + | |
| 438 | +config SYS_CONFIG_NAME | |
| 439 | + default "igkboard-imx6ull" | |
| 440 | + | |
| 441 | +config TEXT_BASE | |
| 442 | + default 0x87800000 | |
| 443 | +endif | |
| 444 | diff --git a/board/lingyun/igkboard-imx6ull/MAINTAINERS b/board/lingyun/igkboard-imx6ull/MAINTAINERS | |
| 445 | new file mode 100644 | |
| 446 | index 00000000..90a4eecb | |
| 447 | --- /dev/null | |
| 448 | +++ b/board/lingyun/igkboard-imx6ull/MAINTAINERS | |
| 449 | @@ -0,0 +1,7 @@ | |
| 450 | +LingYun i.MX6ULL IoT Gateway Board(igkboard-imx6ull) | |
| 451 | +M: Guo Wenxue <guowenxue@gmail.com> | |
| 452 | +S: Maintained | |
| 453 | +F: board/lingyun/igkboard-imx6ull/ | |
| 454 | +F: include/configs/igkboard-imx6ull.h | |
| 455 | +F: configs/igkboard-imx6ull_defconfig | |
| 456 | + | |
| 457 | diff --git a/board/lingyun/igkboard-imx6ull/Makefile b/board/lingyun/igkboard-imx6ull/Makefile | |
| 458 | new file mode 100644 | |
| 459 | index 00000000..dcc09891 | |
| 460 | --- /dev/null | |
| 461 | +++ b/board/lingyun/igkboard-imx6ull/Makefile | |
| 462 | @@ -0,0 +1,5 @@ | |
| 463 | +# SPDX-License-Identifier: GPL-2.0+ | |
| 464 | +# (C) Copyright 2016 Freescale Semiconductor, Inc. | |
| 465 | + | |
| 466 | +obj-y := igkboard-imx6ull.o | |
| 467 | +obj-y += ../../freescale/common/mmc.o | |
| 468 | diff --git a/board/lingyun/igkboard-imx6ull/igkboard-imx6ull.c b/board/lingyun/igkboard-imx6ull/igkboard-imx6ull.c | |
| 469 | new file mode 100644 | |
| 470 | index 00000000..3134b61f | |
| 471 | --- /dev/null | |
| 472 | +++ b/board/lingyun/igkboard-imx6ull/igkboard-imx6ull.c | |
| 473 | @@ -0,0 +1,362 @@ | |
| 474 | +// SPDX-License-Identifier: GPL-2.0+ | |
| 475 | +/* | |
| 476 | + * Copyright (C) 2016 Freescale Semiconductor, Inc. | |
| 477 | + * Copyright 2017 NXP | |
| 478 | + */ | |
| 479 | + | |
| 480 | +#include <init.h> | |
| 481 | +#include <asm/arch/clock.h> | |
| 482 | +#include <asm/arch/iomux.h> | |
| 483 | +#include <asm/arch/imx-regs.h> | |
| 484 | +#include <asm/arch/crm_regs.h> | |
| 485 | +#include <asm/arch/mx6-pins.h> | |
| 486 | +#include <asm/arch/sys_proto.h> | |
| 487 | +#include <asm/global_data.h> | |
| 488 | +#include <asm/gpio.h> | |
| 489 | +#include <asm/mach-imx/iomux-v3.h> | |
| 490 | +#include <asm/mach-imx/boot_mode.h> | |
| 491 | +#include <asm/mach-imx/mxc_i2c.h> | |
| 492 | +#include <asm/io.h> | |
| 493 | +#include <common.h> | |
| 494 | +#include <env.h> | |
| 495 | +#include <fsl_esdhc_imx.h> | |
| 496 | +#include <i2c.h> | |
| 497 | +#include <miiphy.h> | |
| 498 | +#include <linux/sizes.h> | |
| 499 | +#include <linux/delay.h> | |
| 500 | +#include <mmc.h> | |
| 501 | +#include <miiphy.h> | |
| 502 | +#include <power/pmic.h> | |
| 503 | +#include <power/pfuze3000_pmic.h> | |
| 504 | +#include "../../freescale/common/pfuze.h" | |
| 505 | + | |
| 506 | +DECLARE_GLOBAL_DATA_PTR; | |
| 507 | + | |
| 508 | +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | |
| 509 | + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ | |
| 510 | + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
| 511 | + | |
| 512 | +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | |
| 513 | + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ | |
| 514 | + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ | |
| 515 | + PAD_CTL_ODE) | |
| 516 | + | |
| 517 | +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ | |
| 518 | + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) | |
| 519 | + | |
| 520 | +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) | |
| 521 | +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ | |
| 522 | + PAD_CTL_SRE_FAST) | |
| 523 | +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) | |
| 524 | + | |
| 525 | + | |
| 526 | +#ifdef CONFIG_DM_PMIC | |
| 527 | +int power_init_board(void) | |
| 528 | +{ | |
| 529 | + struct udevice *dev; | |
| 530 | + int ret, dev_id, rev_id; | |
| 531 | + unsigned int reg; | |
| 532 | + | |
| 533 | + ret = pmic_get("pfuze3000@8", &dev); | |
| 534 | + if (ret == -ENODEV) | |
| 535 | + return 0; | |
| 536 | + if (ret != 0) | |
| 537 | + return ret; | |
| 538 | + | |
| 539 | + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); | |
| 540 | + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); | |
| 541 | + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); | |
| 542 | + | |
| 543 | + /* disable Low Power Mode during standby mode */ | |
| 544 | + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); | |
| 545 | + reg |= 0x1; | |
| 546 | + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); | |
| 547 | + | |
| 548 | + /* SW1B step ramp up time from 2us to 4us/25mV */ | |
| 549 | + pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40); | |
| 550 | + | |
| 551 | + /* SW1B mode to APS/PFM */ | |
| 552 | + pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc); | |
| 553 | + | |
| 554 | + /* SW1B standby voltage set to 0.975V */ | |
| 555 | + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb); | |
| 556 | + | |
| 557 | + return 0; | |
| 558 | +} | |
| 559 | + | |
| 560 | +#ifdef CONFIG_LDO_BYPASS_CHECK | |
| 561 | +void ldo_mode_set(int ldo_bypass) | |
| 562 | +{ | |
| 563 | + unsigned int value; | |
| 564 | + u32 vddarm; | |
| 565 | + struct udevice *dev; | |
| 566 | + int ret; | |
| 567 | + | |
| 568 | + ret = pmic_get("pfuze3000@8", &dev); | |
| 569 | + if (ret == -ENODEV) { | |
| 570 | + printf("No PMIC found!\n"); | |
| 571 | + return; | |
| 572 | + } | |
| 573 | + | |
| 574 | + /* switch to ldo_bypass mode */ | |
| 575 | + if (ldo_bypass) { | |
| 576 | + prep_anatop_bypass(); | |
| 577 | + /* decrease VDDARM to 1.275V */ | |
| 578 | + value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); | |
| 579 | + value &= ~0x1f; | |
| 580 | + value |= PFUZE3000_SW1AB_SETP(12750); | |
| 581 | + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value); | |
| 582 | + | |
| 583 | + set_anatop_bypass(1); | |
| 584 | + vddarm = PFUZE3000_SW1AB_SETP(11750); | |
| 585 | + | |
| 586 | + value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); | |
| 587 | + value &= ~0x1f; | |
| 588 | + value |= vddarm; | |
| 589 | + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value); | |
| 590 | + | |
| 591 | + finish_anatop_bypass(); | |
| 592 | + | |
| 593 | + printf("switch to ldo_bypass mode!\n"); | |
| 594 | + } | |
| 595 | +} | |
| 596 | +#endif | |
| 597 | +#endif | |
| 598 | + | |
| 599 | +int dram_init(void) | |
| 600 | +{ | |
| 601 | + gd->ram_size = imx_ddr_size(); | |
| 602 | + | |
| 603 | + return 0; | |
| 604 | +} | |
| 605 | + | |
| 606 | +static iomux_v3_cfg_t const uart1_pads[] = { | |
| 607 | + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | |
| 608 | + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | |
| 609 | +}; | |
| 610 | + | |
| 611 | +static void setup_iomux_uart(void) | |
| 612 | +{ | |
| 613 | + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); | |
| 614 | +} | |
| 615 | + | |
| 616 | +#ifdef CONFIG_FSL_QSPI | |
| 617 | + | |
| 618 | +#ifndef CONFIG_DM_SPI | |
| 619 | +#define QSPI_PAD_CTRL1 \ | |
| 620 | + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ | |
| 621 | + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) | |
| 622 | + | |
| 623 | +static iomux_v3_cfg_t const quadspi_pads[] = { | |
| 624 | + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
| 625 | + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
| 626 | + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
| 627 | + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
| 628 | + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
| 629 | + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), | |
| 630 | +}; | |
| 631 | +#endif | |
| 632 | + | |
| 633 | +static int board_qspi_init(void) | |
| 634 | +{ | |
| 635 | +#ifndef CONFIG_DM_SPI | |
| 636 | + /* Set the iomux */ | |
| 637 | + imx_iomux_v3_setup_multiple_pads(quadspi_pads, | |
| 638 | + ARRAY_SIZE(quadspi_pads)); | |
| 639 | +#endif | |
| 640 | + /* Set the clock */ | |
| 641 | + enable_qspi_clk(0); | |
| 642 | + | |
| 643 | + return 0; | |
| 644 | +} | |
| 645 | +#endif | |
| 646 | + | |
| 647 | +#ifdef CONFIG_NAND_MXS | |
| 648 | +static iomux_v3_cfg_t const nand_pads[] = { | |
| 649 | + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 650 | + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 651 | + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 652 | + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 653 | + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 654 | + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 655 | + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 656 | + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 657 | + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 658 | + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 659 | + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 660 | + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 661 | + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 662 | + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 663 | + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 664 | + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 665 | + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), | |
| 666 | +}; | |
| 667 | + | |
| 668 | +static void setup_gpmi_nand(void) | |
| 669 | +{ | |
| 670 | + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
| 671 | + | |
| 672 | + /* config gpmi nand iomux */ | |
| 673 | + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); | |
| 674 | + | |
| 675 | + setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | | |
| 676 | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | | |
| 677 | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); | |
| 678 | + | |
| 679 | + /* enable apbh clock gating */ | |
| 680 | + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); | |
| 681 | +} | |
| 682 | +#endif | |
| 683 | + | |
| 684 | +#ifdef CONFIG_FEC_MXC | |
| 685 | +static int setup_fec(void) | |
| 686 | +{ | |
| 687 | + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; | |
| 688 | + int ret; | |
| 689 | + | |
| 690 | + /* | |
| 691 | + * Use 50M anatop loopback REF_CLK1 for ENET1, | |
| 692 | + * clear gpr1[13], set gpr1[17]. | |
| 693 | + */ | |
| 694 | + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, | |
| 695 | + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); | |
| 696 | + /* | |
| 697 | + * Use 50M anatop loopback REF_CLK2 for ENET2, | |
| 698 | + * clear gpr1[14], set gpr1[18]. | |
| 699 | + */ | |
| 700 | + if (!check_module_fused(MODULE_ENET2)) { | |
| 701 | + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, | |
| 702 | + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); | |
| 703 | + } | |
| 704 | + | |
| 705 | + ret = enable_fec_anatop_clock(0, ENET_50MHZ); | |
| 706 | + if (ret) | |
| 707 | + return ret; | |
| 708 | + | |
| 709 | + if (!check_module_fused(MODULE_ENET2)) { | |
| 710 | + ret = enable_fec_anatop_clock(1, ENET_50MHZ); | |
| 711 | + if (ret) | |
| 712 | + return ret; | |
| 713 | + } | |
| 714 | + | |
| 715 | + enable_enet_clk(1); | |
| 716 | + | |
| 717 | + return 0; | |
| 718 | +} | |
| 719 | + | |
| 720 | +int board_phy_config(struct phy_device *phydev) | |
| 721 | +{ | |
| 722 | + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); | |
| 723 | + | |
| 724 | + if (phydev->drv->config) | |
| 725 | + phydev->drv->config(phydev); | |
| 726 | + | |
| 727 | + return 0; | |
| 728 | +} | |
| 729 | +#endif | |
| 730 | + | |
| 731 | +#ifdef CONFIG_DM_VIDEO | |
| 732 | +static iomux_v3_cfg_t const lcd_pads[] = { | |
| 733 | + /* Use GPIO for Brightness adjustment, duty cycle = period. */ | |
| 734 | + MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
| 735 | +}; | |
| 736 | + | |
| 737 | +static int setup_lcd(void) | |
| 738 | +{ | |
| 739 | + enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); | |
| 740 | + | |
| 741 | + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); | |
| 742 | + | |
| 743 | + /* Reset the LCD */ | |
| 744 | + gpio_request(IMX_GPIO_NR(5, 9), "lcd reset"); | |
| 745 | + gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); | |
| 746 | + udelay(500); | |
| 747 | + gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); | |
| 748 | + | |
| 749 | + /* Set Brightness to high */ | |
| 750 | + gpio_request(IMX_GPIO_NR(1, 8), "backlight"); | |
| 751 | + gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); | |
| 752 | + | |
| 753 | + return 0; | |
| 754 | +} | |
| 755 | +#else | |
| 756 | +static inline int setup_lcd(void) { return 0; } | |
| 757 | +#endif | |
| 758 | + | |
| 759 | +int board_early_init_f(void) | |
| 760 | +{ | |
| 761 | + setup_iomux_uart(); | |
| 762 | + | |
| 763 | + return 0; | |
| 764 | +} | |
| 765 | + | |
| 766 | +int board_init(void) | |
| 767 | +{ | |
| 768 | + /* Address of boot parameters */ | |
| 769 | + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; | |
| 770 | + | |
| 771 | +#ifdef CONFIG_FEC_MXC | |
| 772 | + setup_fec(); | |
| 773 | +#endif | |
| 774 | + | |
| 775 | +#ifdef CONFIG_FSL_QSPI | |
| 776 | + board_qspi_init(); | |
| 777 | +#endif | |
| 778 | + | |
| 779 | +#ifdef CONFIG_NAND_MXS | |
| 780 | + setup_gpmi_nand(); | |
| 781 | +#endif | |
| 782 | + | |
| 783 | + return 0; | |
| 784 | +} | |
| 785 | + | |
| 786 | +#ifdef CONFIG_CMD_BMODE | |
| 787 | +static const struct boot_mode board_boot_modes[] = { | |
| 788 | + /* 4 bit bus width */ | |
| 789 | + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, | |
| 790 | + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, | |
| 791 | + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, | |
| 792 | + {NULL, 0}, | |
| 793 | +}; | |
| 794 | +#endif | |
| 795 | + | |
| 796 | +int board_late_init(void) | |
| 797 | +{ | |
| 798 | +#ifdef CONFIG_CMD_BMODE | |
| 799 | + add_board_boot_modes(board_boot_modes); | |
| 800 | +#endif | |
| 801 | + | |
| 802 | + env_set("tee", "no"); | |
| 803 | +#ifdef CONFIG_IMX_OPTEE | |
| 804 | + env_set("tee", "yes"); | |
| 805 | +#endif | |
| 806 | + | |
| 807 | + setup_lcd(); | |
| 808 | + | |
| 809 | +#ifdef CONFIG_ENV_IS_IN_MMC | |
| 810 | + board_late_mmc_env_init(); | |
| 811 | +#endif | |
| 812 | + | |
| 813 | + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); | |
| 814 | + | |
| 815 | + return 0; | |
| 816 | +} | |
| 817 | + | |
| 818 | +int checkboard(void) | |
| 819 | +{ | |
| 820 | + if (is_mx6ull_9x9_evk()) | |
| 821 | + puts("Board: MX6ULL 9x9 EVK\n"); | |
| 822 | + else if (is_cpu_type(MXC_CPU_MX6ULZ)) | |
| 823 | + puts("Board: MX6ULZ 14x14 EVK\n"); | |
| 824 | + else | |
| 825 | + puts("Board: igkboard-imx6ull\n\n"); | |
| 826 | + | |
| 827 | + return 0; | |
| 828 | +} | |
| 829 | + | |
| 830 | +void board_quiesce_devices(void) | |
| 831 | +{ | |
| 832 | +#if defined(CONFIG_VIDEO_MXS) | |
| 833 | + enable_lcdif_clock(LCDIF1_BASE_ADDR, 0); | |
| 834 | +#endif | |
| 835 | +} | |
| 836 | diff --git a/board/lingyun/igkboard-imx6ull/imximage.cfg b/board/lingyun/igkboard-imx6ull/imximage.cfg | |
| 837 | new file mode 100644 | |
| 838 | index 00000000..6e8a9187 | |
| 839 | --- /dev/null | |
| 840 | +++ b/board/lingyun/igkboard-imx6ull/imximage.cfg | |
| 841 | @@ -0,0 +1,120 @@ | |
| 842 | +/* SPDX-License-Identifier: GPL-2.0+ */ | |
| 843 | +/* | |
| 844 | + * Copyright (C) 2016 Freescale Semiconductor, Inc. | |
| 845 | + * Copyright 2017 NXP | |
| 846 | + * | |
| 847 | + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure | |
| 848 | + * and create imximage boot image | |
| 849 | + * | |
| 850 | + * The syntax is taken as close as possible with the kwbimage | |
| 851 | + */ | |
| 852 | + | |
| 853 | +#include <config.h> | |
| 854 | + | |
| 855 | +/* image version */ | |
| 856 | + | |
| 857 | +IMAGE_VERSION 2 | |
| 858 | + | |
| 859 | +/* | |
| 860 | + * Boot Device : one of | |
| 861 | + * spi/sd/nand/onenand, qspi/nor | |
| 862 | + */ | |
| 863 | + | |
| 864 | +#ifdef CONFIG_QSPI_BOOT | |
| 865 | +BOOT_FROM qspi | |
| 866 | +#elif defined(CONFIG_NOR_BOOT) | |
| 867 | +BOOT_FROM nor | |
| 868 | +#else | |
| 869 | +BOOT_FROM sd | |
| 870 | +#endif | |
| 871 | + | |
| 872 | +#ifdef CONFIG_USE_IMXIMG_PLUGIN | |
| 873 | +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ | |
| 874 | +PLUGIN board/freescale/mx6ullevk/plugin.bin 0x00907000 | |
| 875 | +#else | |
| 876 | + | |
| 877 | +#ifdef CONFIG_IMX_HAB | |
| 878 | +CSF CONFIG_CSF_SIZE | |
| 879 | +#endif | |
| 880 | + | |
| 881 | +/* | |
| 882 | + * Device Configuration Data (DCD) | |
| 883 | + * | |
| 884 | + * Each entry must have the format: | |
| 885 | + * Addr-type Address Value | |
| 886 | + * | |
| 887 | + * where: | |
| 888 | + * Addr-type register length (1,2 or 4 bytes) | |
| 889 | + * Address absolute address of the register | |
| 890 | + * value value to be stored in the register | |
| 891 | + */ | |
| 892 | + | |
| 893 | +/* Enable all clocks */ | |
| 894 | +DATA 4 0x020c4068 0xffffffff | |
| 895 | +DATA 4 0x020c406c 0xffffffff | |
| 896 | +DATA 4 0x020c4070 0xffffffff | |
| 897 | +DATA 4 0x020c4074 0xffffffff | |
| 898 | +DATA 4 0x020c4078 0xffffffff | |
| 899 | +DATA 4 0x020c407c 0xffffffff | |
| 900 | +DATA 4 0x020c4080 0xffffffff | |
| 901 | + | |
| 902 | +#ifdef CONFIG_IMX_OPTEE | |
| 903 | +DATA 4 0x20e4024 0x00000001 | |
| 904 | +CHECK_BITS_SET 4 0x20e4024 0x1 | |
| 905 | +#endif | |
| 906 | + | |
| 907 | +DATA 4 0x020E04B4 0x000C0000 | |
| 908 | +DATA 4 0x020E04AC 0x00000000 | |
| 909 | +DATA 4 0x020E027C 0x00000030 | |
| 910 | +DATA 4 0x020E0250 0x00000030 | |
| 911 | +DATA 4 0x020E024C 0x00000030 | |
| 912 | +DATA 4 0x020E0490 0x00000030 | |
| 913 | +DATA 4 0x020E0288 0x000C0030 | |
| 914 | +DATA 4 0x020E0270 0x00000000 | |
| 915 | +DATA 4 0x020E0260 0x00000030 | |
| 916 | +DATA 4 0x020E0264 0x00000030 | |
| 917 | +DATA 4 0x020E04A0 0x00000030 | |
| 918 | +DATA 4 0x020E0494 0x00020000 | |
| 919 | +DATA 4 0x020E0280 0x00000030 | |
| 920 | +DATA 4 0x020E0284 0x00000030 | |
| 921 | +DATA 4 0x020E04B0 0x00020000 | |
| 922 | +DATA 4 0x020E0498 0x00000030 | |
| 923 | +DATA 4 0x020E04A4 0x00000030 | |
| 924 | +DATA 4 0x020E0244 0x00000030 | |
| 925 | +DATA 4 0x020E0248 0x00000030 | |
| 926 | +DATA 4 0x021B001C 0x00008000 | |
| 927 | +DATA 4 0x021B0800 0xA1390003 | |
| 928 | +DATA 4 0x021B080C 0x00000004 | |
| 929 | +DATA 4 0x021B083C 0x41640158 | |
| 930 | +DATA 4 0x021B0848 0x40403237 | |
| 931 | +DATA 4 0x021B0850 0x40403C33 | |
| 932 | +DATA 4 0x021B081C 0x33333333 | |
| 933 | +DATA 4 0x021B0820 0x33333333 | |
| 934 | +DATA 4 0x021B082C 0xf3333333 | |
| 935 | +DATA 4 0x021B0830 0xf3333333 | |
| 936 | +DATA 4 0x021B08C0 0x00944009 | |
| 937 | +DATA 4 0x021B08b8 0x00000800 | |
| 938 | +DATA 4 0x021B0004 0x0002002D | |
| 939 | +DATA 4 0x021B0008 0x1B333030 | |
| 940 | +DATA 4 0x021B000C 0x676B52F3 | |
| 941 | +DATA 4 0x021B0010 0xB66D0B63 | |
| 942 | +DATA 4 0x021B0014 0x01FF00DB | |
| 943 | +DATA 4 0x021B0018 0x00201740 | |
| 944 | +DATA 4 0x021B001C 0x00008000 | |
| 945 | +DATA 4 0x021B002C 0x000026D2 | |
| 946 | +DATA 4 0x021B0030 0x006B1023 | |
| 947 | +DATA 4 0x021B0040 0x0000004F | |
| 948 | +DATA 4 0x021B0000 0x84180000 | |
| 949 | +DATA 4 0x021B0890 0x00400000 | |
| 950 | +DATA 4 0x021B001C 0x02008032 | |
| 951 | +DATA 4 0x021B001C 0x00008033 | |
| 952 | +DATA 4 0x021B001C 0x00048031 | |
| 953 | +DATA 4 0x021B001C 0x15208030 | |
| 954 | +DATA 4 0x021B001C 0x04008040 | |
| 955 | +DATA 4 0x021B0020 0x00000800 | |
| 956 | +DATA 4 0x021B0818 0x00000227 | |
| 957 | +DATA 4 0x021B0004 0x0002552D | |
| 958 | +DATA 4 0x021B0404 0x00011006 | |
| 959 | +DATA 4 0x021B001C 0x00000000 | |
| 960 | + | |
| 961 | +#endif | |
| 962 | diff --git a/board/lingyun/igkboard-imx6ull/imximage_lpddr2.cfg b/board/lingyun/igkboard-imx6ull/imximage_lpddr2.cfg | |
| 963 | new file mode 100644 | |
| 964 | index 00000000..c6141e9c | |
| 965 | --- /dev/null | |
| 966 | +++ b/board/lingyun/igkboard-imx6ull/imximage_lpddr2.cfg | |
| 967 | @@ -0,0 +1,125 @@ | |
| 968 | +/* | |
| 969 | + * Copyright (C) 2016 Freescale Semiconductor, Inc. | |
| 970 | + * Copyright 2017 NXP | |
| 971 | + * | |
| 972 | + * SPDX-License-Identifier: GPL-2.0+ | |
| 973 | + * | |
| 974 | + * Refer docs/README.imxmage for more details about how-to configure | |
| 975 | + * and create imximage boot image | |
| 976 | + * | |
| 977 | + * The syntax is taken as close as possible with the kwbimage | |
| 978 | + */ | |
| 979 | + | |
| 980 | +#include <config.h> | |
| 981 | + | |
| 982 | +/* image version */ | |
| 983 | + | |
| 984 | +IMAGE_VERSION 2 | |
| 985 | + | |
| 986 | +/* | |
| 987 | + * Boot Device : one of | |
| 988 | + * spi/sd/nand/onenand, qspi/nor | |
| 989 | + */ | |
| 990 | + | |
| 991 | +#ifdef CONFIG_QSPI_BOOT | |
| 992 | +BOOT_FROM qspi | |
| 993 | +#elif defined(CONFIG_NOR_BOOT) | |
| 994 | +BOOT_FROM nor | |
| 995 | +#else | |
| 996 | +BOOT_FROM sd | |
| 997 | +#endif | |
| 998 | + | |
| 999 | +#ifdef CONFIG_USE_IMXIMG_PLUGIN | |
| 1000 | +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ | |
| 1001 | +PLUGIN board/lingyun/igkboard-imx6ull/plugin.bin 0x00907000 | |
| 1002 | +#else | |
| 1003 | + | |
| 1004 | +#ifdef CONFIG_IMX_HAB | |
| 1005 | +CSF CONFIG_CSF_SIZE | |
| 1006 | +#endif | |
| 1007 | + | |
| 1008 | +/* | |
| 1009 | + * Device Configuration Data (DCD) | |
| 1010 | + * | |
| 1011 | + * Each entry must have the format: | |
| 1012 | + * Addr-type Address Value | |
| 1013 | + * | |
| 1014 | + * where: | |
| 1015 | + * Addr-type register length (1,2 or 4 bytes) | |
| 1016 | + * Address absolute address of the register | |
| 1017 | + * value value to be stored in the register | |
| 1018 | + */ | |
| 1019 | + | |
| 1020 | +DATA 4 0x020c4068 0xffffffff | |
| 1021 | +DATA 4 0x020c406c 0xffffffff | |
| 1022 | +DATA 4 0x020c4070 0xffffffff | |
| 1023 | +DATA 4 0x020c4074 0xffffffff | |
| 1024 | +DATA 4 0x020c4078 0xffffffff | |
| 1025 | +DATA 4 0x020c407c 0xffffffff | |
| 1026 | +DATA 4 0x020c4080 0xffffffff | |
| 1027 | + | |
| 1028 | +#ifdef CONFIG_IMX_OPTEE | |
| 1029 | +DATA 4 0x20e4024 0x00000001 | |
| 1030 | +CHECK_BITS_SET 4 0x20e4024 0x1 | |
| 1031 | +#endif | |
| 1032 | + | |
| 1033 | +DATA 4 0x020E04B4 0x00080000 | |
| 1034 | +DATA 4 0x020E04AC 0x00000000 | |
| 1035 | +DATA 4 0x020E027C 0x00000030 | |
| 1036 | +DATA 4 0x020E0250 0x00000030 | |
| 1037 | +DATA 4 0x020E024C 0x00000030 | |
| 1038 | +DATA 4 0x020E0490 0x00000030 | |
| 1039 | +DATA 4 0x020E0288 0x00000030 | |
| 1040 | +DATA 4 0x020E0270 0x00000000 | |
| 1041 | +DATA 4 0x020E0260 0x00000000 | |
| 1042 | +DATA 4 0x020E0264 0x00000000 | |
| 1043 | +DATA 4 0x020E04A0 0x00000030 | |
| 1044 | +DATA 4 0x020E0494 0x00020000 | |
| 1045 | +DATA 4 0x020E0280 0x00003030 | |
| 1046 | +DATA 4 0x020E0284 0x00003030 | |
| 1047 | +DATA 4 0x020E04B0 0x00020000 | |
| 1048 | +DATA 4 0x020E0498 0x00000030 | |
| 1049 | +DATA 4 0x020E04A4 0x00000030 | |
| 1050 | +DATA 4 0x020E0244 0x00000030 | |
| 1051 | +DATA 4 0x020E0248 0x00000030 | |
| 1052 | + | |
| 1053 | +DATA 4 0x021B001C 0x00008000 | |
| 1054 | +DATA 4 0x021B085C 0x1b4700c7 | |
| 1055 | +DATA 4 0x021B0800 0xA1390003 | |
| 1056 | +DATA 4 0x021B0890 0x23400A38 | |
| 1057 | +DATA 4 0x021B08b8 0x00000800 | |
| 1058 | + | |
| 1059 | +DATA 4 0x021B081C 0x33333333 | |
| 1060 | +DATA 4 0x021B0820 0x33333333 | |
| 1061 | +DATA 4 0x021B082C 0xf3333333 | |
| 1062 | +DATA 4 0x021B0830 0xf3333333 | |
| 1063 | +DATA 4 0x021B083C 0x20000000 | |
| 1064 | +DATA 4 0x021B0848 0x40403439 | |
| 1065 | +DATA 4 0x021B0850 0x4040342D | |
| 1066 | +DATA 4 0x021B08C0 0x00921012 | |
| 1067 | +DATA 4 0x021B08b8 0x00000800 | |
| 1068 | + | |
| 1069 | +DATA 4 0x021B0004 0x00020052 | |
| 1070 | +DATA 4 0x021B0008 0x00000000 | |
| 1071 | +DATA 4 0x021B000C 0x33374133 | |
| 1072 | +DATA 4 0x021B0010 0x00100A82 | |
| 1073 | +DATA 4 0x021B0038 0x00170557 | |
| 1074 | +DATA 4 0x021B0014 0x00000093 | |
| 1075 | +DATA 4 0x021B0018 0x00201748 | |
| 1076 | +DATA 4 0x021B002C 0x0F9F26D2 | |
| 1077 | +DATA 4 0x021B0030 0x009F0010 | |
| 1078 | +DATA 4 0x021B0040 0x00000047 | |
| 1079 | +DATA 4 0x021B0000 0x83100000 | |
| 1080 | +DATA 4 0x021B001C 0x00008010 | |
| 1081 | +DATA 4 0x021B001C 0x003F8030 | |
| 1082 | +DATA 4 0x021B001C 0xFF0A8030 | |
| 1083 | +DATA 4 0x021B001C 0x82018030 | |
| 1084 | +DATA 4 0x021B001C 0x04028030 | |
| 1085 | +DATA 4 0x021B001C 0x01038030 | |
| 1086 | +DATA 4 0x021B0020 0x00001800 | |
| 1087 | +DATA 4 0x021B0818 0x00000000 | |
| 1088 | +DATA 4 0x021B0800 0xA1310003 | |
| 1089 | +DATA 4 0x021B0004 0x00025552 | |
| 1090 | +DATA 4 0x021B0404 0x00011006 | |
| 1091 | +DATA 4 0x021B001C 0x00000000 | |
| 1092 | +#endif | |
| 1093 | diff --git a/board/lingyun/igkboard-imx6ull/plugin.S b/board/lingyun/igkboard-imx6ull/plugin.S | |
| 1094 | new file mode 100644 | |
| 1095 | index 00000000..812088d1 | |
| 1096 | --- /dev/null | |
| 1097 | +++ b/board/lingyun/igkboard-imx6ull/plugin.S | |
| 1098 | @@ -0,0 +1,263 @@ | |
| 1099 | +/* SPDX-License-Identifier: GPL-2.0+ */ | |
| 1100 | +/* | |
| 1101 | + * Copyright (C) 2016 Freescale Semiconductor, Inc. | |
| 1102 | + * Copyright 2017 NXP | |
| 1103 | + */ | |
| 1104 | + | |
| 1105 | +#include <config.h> | |
| 1106 | + | |
| 1107 | +/* DDR script */ | |
| 1108 | +.macro imx6ull_ddr3_evk_setting | |
| 1109 | + ldr r0, =IOMUXC_BASE_ADDR | |
| 1110 | + ldr r1, =0x000C0000 | |
| 1111 | + str r1, [r0, #0x4B4] | |
| 1112 | + ldr r1, =0x00000000 | |
| 1113 | + str r1, [r0, #0x4AC] | |
| 1114 | + ldr r1, =0x00000030 | |
| 1115 | + str r1, [r0, #0x27C] | |
| 1116 | + ldr r1, =0x00000030 | |
| 1117 | + str r1, [r0, #0x250] | |
| 1118 | + str r1, [r0, #0x24C] | |
| 1119 | + str r1, [r0, #0x490] | |
| 1120 | + ldr r1, =0x000C0030 | |
| 1121 | + str r1, [r0, #0x288] | |
| 1122 | + | |
| 1123 | + ldr r1, =0x00000000 | |
| 1124 | + str r1, [r0, #0x270] | |
| 1125 | + | |
| 1126 | + ldr r1, =0x00000030 | |
| 1127 | + str r1, [r0, #0x260] | |
| 1128 | + str r1, [r0, #0x264] | |
| 1129 | + str r1, [r0, #0x4A0] | |
| 1130 | + | |
| 1131 | + ldr r1, =0x00020000 | |
| 1132 | + str r1, [r0, #0x494] | |
| 1133 | + | |
| 1134 | + ldr r1, =0x00000030 | |
| 1135 | + str r1, [r0, #0x280] | |
| 1136 | + ldr r1, =0x00000030 | |
| 1137 | + str r1, [r0, #0x284] | |
| 1138 | + | |
| 1139 | + ldr r1, =0x00020000 | |
| 1140 | + str r1, [r0, #0x4B0] | |
| 1141 | + | |
| 1142 | + ldr r1, =0x00000030 | |
| 1143 | + str r1, [r0, #0x498] | |
| 1144 | + str r1, [r0, #0x4A4] | |
| 1145 | + str r1, [r0, #0x244] | |
| 1146 | + str r1, [r0, #0x248] | |
| 1147 | + | |
| 1148 | + ldr r0, =MMDC_P0_BASE_ADDR | |
| 1149 | + ldr r1, =0x00008000 | |
| 1150 | + str r1, [r0, #0x1C] | |
| 1151 | + ldr r1, =0xA1390003 | |
| 1152 | + str r1, [r0, #0x800] | |
| 1153 | + ldr r1, =0x00000004 | |
| 1154 | + str r1, [r0, #0x80C] | |
| 1155 | + ldr r1, =0x41640158 | |
| 1156 | + str r1, [r0, #0x83C] | |
| 1157 | + ldr r1, =0x40403237 | |
| 1158 | + str r1, [r0, #0x848] | |
| 1159 | + ldr r1, =0x40403C33 | |
| 1160 | + str r1, [r0, #0x850] | |
| 1161 | + ldr r1, =0x33333333 | |
| 1162 | + str r1, [r0, #0x81C] | |
| 1163 | + str r1, [r0, #0x820] | |
| 1164 | + ldr r1, =0xF3333333 | |
| 1165 | + str r1, [r0, #0x82C] | |
| 1166 | + str r1, [r0, #0x830] | |
| 1167 | + ldr r1, =0x00944009 | |
| 1168 | + str r1, [r0, #0x8C0] | |
| 1169 | + ldr r1, =0x00000800 | |
| 1170 | + str r1, [r0, #0x8B8] | |
| 1171 | + ldr r1, =0x0002002D | |
| 1172 | + str r1, [r0, #0x004] | |
| 1173 | + ldr r1, =0x1B333030 | |
| 1174 | + str r1, [r0, #0x008] | |
| 1175 | + ldr r1, =0x676B52F3 | |
| 1176 | + str r1, [r0, #0x00C] | |
| 1177 | + ldr r1, =0xB66D0B63 | |
| 1178 | + str r1, [r0, #0x010] | |
| 1179 | + ldr r1, =0x01FF00DB | |
| 1180 | + str r1, [r0, #0x014] | |
| 1181 | + ldr r1, =0x00201740 | |
| 1182 | + str r1, [r0, #0x018] | |
| 1183 | + ldr r1, =0x00008000 | |
| 1184 | + str r1, [r0, #0x01C] | |
| 1185 | + ldr r1, =0x000026D2 | |
| 1186 | + str r1, [r0, #0x02C] | |
| 1187 | + ldr r1, =0x006B1023 | |
| 1188 | + str r1, [r0, #0x030] | |
| 1189 | + ldr r1, =0x0000004F | |
| 1190 | + str r1, [r0, #0x040] | |
| 1191 | + ldr r1, =0x84180000 | |
| 1192 | + str r1, [r0, #0x000] | |
| 1193 | + ldr r1, =0x00400000 | |
| 1194 | + str r1, [r0, #0x890] | |
| 1195 | + ldr r1, =0x02008032 | |
| 1196 | + str r1, [r0, #0x01C] | |
| 1197 | + ldr r1, =0x00008033 | |
| 1198 | + str r1, [r0, #0x01C] | |
| 1199 | + ldr r1, =0x00048031 | |
| 1200 | + str r1, [r0, #0x01C] | |
| 1201 | + ldr r1, =0x15208030 | |
| 1202 | + str r1, [r0, #0x01C] | |
| 1203 | + ldr r1, =0x04008040 | |
| 1204 | + str r1, [r0, #0x01C] | |
| 1205 | + ldr r1, =0x00000800 | |
| 1206 | + str r1, [r0, #0x020] | |
| 1207 | + ldr r1, =0x00000227 | |
| 1208 | + str r1, [r0, #0x818] | |
| 1209 | + ldr r1, =0x0002552D | |
| 1210 | + str r1, [r0, #0x004] | |
| 1211 | + ldr r1, =0x00011006 | |
| 1212 | + str r1, [r0, #0x404] | |
| 1213 | + ldr r1, =0x00000000 | |
| 1214 | + str r1, [r0, #0x01C] | |
| 1215 | +.endm | |
| 1216 | + | |
| 1217 | +.macro imx6ull_lpddr2_evk_setting | |
| 1218 | + ldr r0, =IOMUXC_BASE_ADDR | |
| 1219 | + ldr r1, =0x00080000 | |
| 1220 | + str r1, [r0, #0x4B4] | |
| 1221 | + ldr r1, =0x00000000 | |
| 1222 | + str r1, [r0, #0x4AC] | |
| 1223 | + ldr r1, =0x00000030 | |
| 1224 | + str r1, [r0, #0x27C] | |
| 1225 | + str r1, [r0, #0x250] | |
| 1226 | + str r1, [r0, #0x24C] | |
| 1227 | + str r1, [r0, #0x490] | |
| 1228 | + str r1, [r0, #0x288] | |
| 1229 | + | |
| 1230 | + ldr r1, =0x00000000 | |
| 1231 | + str r1, [r0, #0x270] | |
| 1232 | + str r1, [r0, #0x260] | |
| 1233 | + str r1, [r0, #0x264] | |
| 1234 | + | |
| 1235 | + ldr r1, =0x00000030 | |
| 1236 | + str r1, [r0, #0x4A0] | |
| 1237 | + | |
| 1238 | + ldr r1, =0x00020000 | |
| 1239 | + str r1, [r0, #0x494] | |
| 1240 | + | |
| 1241 | + ldr r1, =0x00003030 | |
| 1242 | + str r1, [r0, #0x280] | |
| 1243 | + ldr r1, =0x00003030 | |
| 1244 | + str r1, [r0, #0x284] | |
| 1245 | + | |
| 1246 | + ldr r1, =0x00020000 | |
| 1247 | + str r1, [r0, #0x4B0] | |
| 1248 | + | |
| 1249 | + ldr r1, =0x00000030 | |
| 1250 | + str r1, [r0, #0x498] | |
| 1251 | + str r1, [r0, #0x4A4] | |
| 1252 | + str r1, [r0, #0x244] | |
| 1253 | + str r1, [r0, #0x248] | |
| 1254 | + | |
| 1255 | + ldr r0, =MMDC_P0_BASE_ADDR | |
| 1256 | + ldr r1, =0x00008000 | |
| 1257 | + str r1, [r0, #0x1C] | |
| 1258 | + ldr r1, =0x1b4700c7 | |
| 1259 | + str r1, [r0, #0x85c] | |
| 1260 | + ldr r1, =0xA1390003 | |
| 1261 | + str r1, [r0, #0x800] | |
| 1262 | + ldr r1, =0x23400A38 | |
| 1263 | + str r1, [r0, #0x890] | |
| 1264 | + ldr r1, =0x00000800 | |
| 1265 | + str r1, [r0, #0x8b8] | |
| 1266 | + ldr r1, =0x33333333 | |
| 1267 | + str r1, [r0, #0x81C] | |
| 1268 | + str r1, [r0, #0x820] | |
| 1269 | + ldr r1, =0xF3333333 | |
| 1270 | + str r1, [r0, #0x82C] | |
| 1271 | + str r1, [r0, #0x830] | |
| 1272 | + ldr r1, =0x20000000 | |
| 1273 | + str r1, [r0, #0x83C] | |
| 1274 | + ldr r1, =0x40403439 | |
| 1275 | + str r1, [r0, #0x848] | |
| 1276 | + ldr r1, =0x4040342D | |
| 1277 | + str r1, [r0, #0x850] | |
| 1278 | + ldr r1, =0x00921012 | |
| 1279 | + str r1, [r0, #0x8C0] | |
| 1280 | + ldr r1, =0x00000800 | |
| 1281 | + str r1, [r0, #0x8B8] | |
| 1282 | + | |
| 1283 | + ldr r1, =0x00020052 | |
| 1284 | + str r1, [r0, #0x004] | |
| 1285 | + ldr r1, =0x00000000 | |
| 1286 | + str r1, [r0, #0x008] | |
| 1287 | + ldr r1, =0x33374133 | |
| 1288 | + str r1, [r0, #0x00C] | |
| 1289 | + ldr r1, =0x00100A82 | |
| 1290 | + str r1, [r0, #0x010] | |
| 1291 | + ldr r1, =0x00170557 | |
| 1292 | + str r1, [r0, #0x038] | |
| 1293 | + ldr r1, =0x00000093 | |
| 1294 | + str r1, [r0, #0x014] | |
| 1295 | + ldr r1, =0x00201748 | |
| 1296 | + str r1, [r0, #0x018] | |
| 1297 | + ldr r1, =0x0F9F26D2 | |
| 1298 | + str r1, [r0, #0x02C] | |
| 1299 | + ldr r1, =0x009F0010 | |
| 1300 | + str r1, [r0, #0x030] | |
| 1301 | + ldr r1, =0x00000047 | |
| 1302 | + str r1, [r0, #0x040] | |
| 1303 | + ldr r1, =0x83100000 | |
| 1304 | + str r1, [r0, #0x000] | |
| 1305 | + ldr r1, =0x00008010 | |
| 1306 | + str r1, [r0, #0x01C] | |
| 1307 | + ldr r1, =0x003F8030 | |
| 1308 | + str r1, [r0, #0x01C] | |
| 1309 | + ldr r1, =0xFF0A8030 | |
| 1310 | + str r1, [r0, #0x01C] | |
| 1311 | + ldr r1, =0x82018030 | |
| 1312 | + str r1, [r0, #0x01C] | |
| 1313 | + ldr r1, =0x04028030 | |
| 1314 | + str r1, [r0, #0x01C] | |
| 1315 | + ldr r1, =0x01038030 | |
| 1316 | + str r1, [r0, #0x01C] | |
| 1317 | + ldr r1, =0x00001800 | |
| 1318 | + str r1, [r0, #0x020] | |
| 1319 | + ldr r1, =0x00000000 | |
| 1320 | + str r1, [r0, #0x818] | |
| 1321 | + ldr r1, =0xA1310003 | |
| 1322 | + str r1, [r0, #0x800] | |
| 1323 | + ldr r1, =0x00025552 | |
| 1324 | + str r1, [r0, #0x004] | |
| 1325 | + ldr r1, =0x00011006 | |
| 1326 | + str r1, [r0, #0x404] | |
| 1327 | + ldr r1, =0x00000000 | |
| 1328 | + str r1, [r0, #0x01C] | |
| 1329 | +.endm | |
| 1330 | + | |
| 1331 | +.macro imx6_clock_gating | |
| 1332 | + ldr r0, =CCM_BASE_ADDR | |
| 1333 | + ldr r1, =0xFFFFFFFF | |
| 1334 | + str r1, [r0, #0x68] | |
| 1335 | + str r1, [r0, #0x6C] | |
| 1336 | + str r1, [r0, #0x70] | |
| 1337 | + str r1, [r0, #0x74] | |
| 1338 | + str r1, [r0, #0x78] | |
| 1339 | + str r1, [r0, #0x7C] | |
| 1340 | + str r1, [r0, #0x80] | |
| 1341 | + | |
| 1342 | +#ifdef CONFIG_IMX_OPTEE | |
| 1343 | + ldr r0, =0x20e4024 | |
| 1344 | + ldr r1, =0x1 | |
| 1345 | + str r1, [r0] | |
| 1346 | +#endif | |
| 1347 | +.endm | |
| 1348 | + | |
| 1349 | +.macro imx6_qos_setting | |
| 1350 | +.endm | |
| 1351 | + | |
| 1352 | +.macro imx6_ddr_setting | |
| 1353 | +#if defined (CONFIG_TARGET_MX6ULL_9X9_EVK) | |
| 1354 | + imx6ull_lpddr2_evk_setting | |
| 1355 | +#else | |
| 1356 | + imx6ull_ddr3_evk_setting | |
| 1357 | +#endif | |
| 1358 | +.endm | |
| 1359 | + | |
| 1360 | +/* include the common plugin code here */ | |
| 1361 | +#include <asm/arch/mx6_plugin.S> | |
| 1362 | diff --git a/configs/igkboard-imx6ull_defconfig b/configs/igkboard-imx6ull_defconfig | |
| 1363 | new file mode 100644 | |
| 1364 | index 00000000..22359130 | |
| 1365 | --- /dev/null | |
| 1366 | +++ b/configs/igkboard-imx6ull_defconfig | |
| 1367 | @@ -0,0 +1,86 @@ | |
| 1368 | +CONFIG_ARM=y | |
| 1369 | +CONFIG_ARCH_MX6=y | |
| 1370 | +CONFIG_SYS_MALLOC_LEN=0x1000000 | |
| 1371 | +CONFIG_NR_DRAM_BANKS=1 | |
| 1372 | +CONFIG_ENV_SIZE=0x2000 | |
| 1373 | +CONFIG_ENV_OFFSET=0xE0000 | |
| 1374 | +CONFIG_IMX_CONFIG="board/lingyun/igkboard-imx6ull/imximage.cfg" | |
| 1375 | +CONFIG_MX6ULL=y | |
| 1376 | +CONFIG_TARGET_LINGYUN_IGKBOARD_IMX6ULL=y | |
| 1377 | +CONFIG_DM_GPIO=y | |
| 1378 | +CONFIG_DEFAULT_DEVICE_TREE="igkboard-imx6ull" | |
| 1379 | +CONFIG_SYS_PROMPT="[u-boot@igkboard]# " | |
| 1380 | +CONFIG_SYS_MEMTEST_START=0x80000000 | |
| 1381 | +CONFIG_SYS_MEMTEST_END=0x88000000 | |
| 1382 | +CONFIG_SUPPORT_RAW_INITRD=y | |
| 1383 | +CONFIG_BOOTDELAY=3 | |
| 1384 | +CONFIG_USE_BOOTCOMMAND=y | |
| 1385 | +CONFIG_ARCH_MISC_INIT=y | |
| 1386 | +CONFIG_BOARD_EARLY_INIT_F=y | |
| 1387 | +CONFIG_HUSH_PARSER=y | |
| 1388 | +CONFIG_CMD_BOOTZ=y | |
| 1389 | +CONFIG_CRC32_VERIFY=y | |
| 1390 | +CONFIG_CMD_MEMTEST=y | |
| 1391 | +CONFIG_CMD_GPIO=y | |
| 1392 | +CONFIG_CMD_I2C=y | |
| 1393 | +CONFIG_CMD_MMC=y | |
| 1394 | +CONFIG_CMD_USB=y | |
| 1395 | +CONFIG_CMD_USB_MASS_STORAGE=y | |
| 1396 | +CONFIG_CMD_DHCP=y | |
| 1397 | +CONFIG_CMD_PING=y | |
| 1398 | +CONFIG_CMD_CACHE=y | |
| 1399 | +CONFIG_CMD_RNG=y | |
| 1400 | +CONFIG_CMD_EXT2=y | |
| 1401 | +CONFIG_CMD_EXT4=y | |
| 1402 | +CONFIG_CMD_EXT4_WRITE=y | |
| 1403 | +CONFIG_CMD_FAT=y | |
| 1404 | +CONFIG_CMD_FS_GENERIC=y | |
| 1405 | +CONFIG_OF_CONTROL=y | |
| 1406 | +CONFIG_ENV_OVERWRITE=y | |
| 1407 | +CONFIG_ENV_IS_IN_MMC=y | |
| 1408 | +CONFIG_SYS_RELOC_GD_ENV_ADDR=y | |
| 1409 | +CONFIG_SYS_MMC_ENV_DEV=1 | |
| 1410 | +CONFIG_NET_RANDOM_ETHADDR=y | |
| 1411 | +CONFIG_BOUNCE_BUFFER=y | |
| 1412 | +CONFIG_FSL_DCP_RNG=y | |
| 1413 | +CONFIG_USB_FUNCTION_FASTBOOT=y | |
| 1414 | +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 | |
| 1415 | +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | |
| 1416 | +CONFIG_FASTBOOT_FLASH=y | |
| 1417 | +CONFIG_DM_74X164=y | |
| 1418 | +CONFIG_DM_I2C=y | |
| 1419 | +CONFIG_SYS_I2C_MXC=y | |
| 1420 | +CONFIG_FSL_USDHC=y | |
| 1421 | +CONFIG_MTD=y | |
| 1422 | +CONFIG_DM_SPI_FLASH=y | |
| 1423 | +CONFIG_SF_DEFAULT_SPEED=40000000 | |
| 1424 | +CONFIG_SPI_FLASH_STMICRO=y | |
| 1425 | +CONFIG_PHYLIB=y | |
| 1426 | +CONFIG_PHY_MICREL=y | |
| 1427 | +CONFIG_PHY_MICREL_KSZ8XXX=y | |
| 1428 | +CONFIG_DM_ETH_PHY=y | |
| 1429 | +CONFIG_FEC_MXC=y | |
| 1430 | +CONFIG_MII=y | |
| 1431 | +CONFIG_PINCTRL=y | |
| 1432 | +CONFIG_PINCTRL_IMX6=y | |
| 1433 | +CONFIG_DM_REGULATOR=y | |
| 1434 | +CONFIG_DM_REGULATOR_FIXED=y | |
| 1435 | +CONFIG_DM_REGULATOR_GPIO=y | |
| 1436 | +CONFIG_DM_RNG=y | |
| 1437 | +CONFIG_DM_SERIAL=y | |
| 1438 | +CONFIG_MXC_UART=y | |
| 1439 | +CONFIG_SPI=y | |
| 1440 | +CONFIG_DM_SPI=y | |
| 1441 | +CONFIG_FSL_QSPI=y | |
| 1442 | +CONFIG_SOFT_SPI=y | |
| 1443 | +CONFIG_IMX_THERMAL=y | |
| 1444 | +CONFIG_USB=y | |
| 1445 | +CONFIG_USB_STORAGE=y | |
| 1446 | +CONFIG_USB_HOST_ETHER=y | |
| 1447 | +CONFIG_USB_ETHER_ASIX=y | |
| 1448 | +CONFIG_USB_GADGET=y | |
| 1449 | +CONFIG_USB_GADGET_MANUFACTURER="FSL" | |
| 1450 | +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | |
| 1451 | +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | |
| 1452 | +CONFIG_CI_UDC=y | |
| 1453 | +CONFIG_OF_LIBFDT_OVERLAY=y | |
| 1454 | diff --git a/drivers/fastboot/fb_fsl/fb_fsl_partitions.c b/drivers/fastboot/fb_fsl/fb_fsl_partitions.c | |
| 1455 | index a43c70db..50f89f9b 100644 | |
| 1456 | --- a/drivers/fastboot/fb_fsl/fb_fsl_partitions.c | |
| 1457 | +++ b/drivers/fastboot/fb_fsl/fb_fsl_partitions.c | |
| 1458 | @@ -188,6 +188,12 @@ static int _fastboot_parts_load_from_ptable(void) | |
| 1459 | user_partition = FASTBOOT_MMC_USER_PARTITION_ID; | |
| 1460 | boot_loader_psize = mmc->capacity_boot; | |
| 1461 | } | |
| 1462 | + | |
| 1463 | + /* add by guowenxue to export mmc_no env */ | |
| 1464 | + env_set_ulong("mmc_no", mmc_no); | |
| 1465 | + env_set_ulong("mmcdev", mmc_no); | |
| 1466 | + env_set_ulong("emmc_dev", mmc_no); | |
| 1467 | + env_set_ulong("emmc_ack", mmc_no); | |
| 1468 | } else { | |
| 1469 | printf("Can't setup partition table on this device %d\n", | |
| 1470 | fastboot_devinfo.type); | |
| 1471 | diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c | |
| 1472 | index 50e15cd3..17f4d06d 100644 | |
| 1473 | --- a/drivers/net/phy/phy.c | |
| 1474 | +++ b/drivers/net/phy/phy.c | |
| 1475 | @@ -182,6 +182,8 @@ int genphy_config_aneg(struct phy_device *phydev) | |
| 1476 | { | |
| 1477 | int result; | |
| 1478 | ||
| 1479 | + phy_reset(phydev); /* Add by guowenxue to reset the ethernet phy */ | |
| 1480 | + | |
| 1481 | if (phydev->autoneg != AUTONEG_ENABLE) | |
| 1482 | return genphy_setup_forced(phydev); | |
| 1483 | ||
| 1484 | diff --git a/include/configs/igkboard-dtoverlay.h b/include/configs/igkboard-dtoverlay.h | |
| 1485 | new file mode 100644 | |
| 1486 | index 00000000..e4d68e9f | |
| 1487 | --- /dev/null | |
| 1488 | +++ b/include/configs/igkboard-dtoverlay.h | |
| 1489 | @@ -0,0 +1,60 @@ | |
| 1490 | +/* SPDX-License-Identifier: GPL-2.0+ */ | |
| 1491 | +/* | |
| 1492 | + * Copyright (C) 2023 LingYun IoT System Studio | |
| 1493 | + * | |
| 1494 | + */ | |
| 1495 | +#ifndef __IGKBOARD_DTOVERLAY_H | |
| 1496 | +#define __IGKBOARD_DTOVERLAY_H | |
| 1497 | + | |
| 1498 | +#define IGKBOARD_DTOVERLAY_SUPPORT | |
| 1499 | + | |
| 1500 | +#define FDT_APPLY_OVERLAY() \ | |
| 1501 | + "echo Applying DT overlay => ${dtbo_file}; " \ | |
| 1502 | + "fatload mmc ${mmcdev}:${mmcpart} ${dtbo_addr} ${dtbo_dir}/${dtbo_file}; " \ | |
| 1503 | + "fdt addr ${fdt_addr}; " \ | |
| 1504 | + "fdt resize ${fdt_size}; " \ | |
| 1505 | + "fdt apply ${dtbo_addr}; " | |
| 1506 | + | |
| 1507 | +#define CHECK_APPLY_OVERLAY( name ) \ | |
| 1508 | + "if env exists dtoverlay_" name " && test ${dtoverlay_" name "} = 1 -o ${dtoverlay_" name "} = yes ; then " \ | |
| 1509 | + "setenv dtbo_file " name ".dtbo; " \ | |
| 1510 | + FDT_APPLY_OVERLAY() \ | |
| 1511 | + "fi; " | |
| 1512 | + | |
| 1513 | +#define CHECK_APPLY_OVERLAYS_IDX( name ) \ | |
| 1514 | + "if env exists dtoverlay_" name "; then " \ | |
| 1515 | + "for i in ${dtoverlay_" name "}; do " \ | |
| 1516 | + "setenv dtbo_file " name "$i.dtbo; " \ | |
| 1517 | + FDT_APPLY_OVERLAY() \ | |
| 1518 | + " done;" \ | |
| 1519 | + "fi; " | |
| 1520 | + | |
| 1521 | +#define CHECK_APPLY_OVERLAYS_DTBO( name ) \ | |
| 1522 | + "if env exists dtoverlay_" name "; then " \ | |
| 1523 | + "for f in ${dtoverlay_" name "}; do " \ | |
| 1524 | + "setenv dtbo_file $f.dtbo; " \ | |
| 1525 | + FDT_APPLY_OVERLAY() \ | |
| 1526 | + " done;" \ | |
| 1527 | + "fi; " | |
| 1528 | + | |
| 1529 | +#define FDT_ENTRY_DEF_SETTINGS \ | |
| 1530 | + CHECK_APPLY_OVERLAY("lcd") \ | |
| 1531 | + CHECK_APPLY_OVERLAY("cam") \ | |
| 1532 | + CHECK_APPLY_OVERLAY("w1") \ | |
| 1533 | + CHECK_APPLY_OVERLAY("adc") \ | |
| 1534 | + CHECK_APPLY_OVERLAYS_IDX("i2c") \ | |
| 1535 | + CHECK_APPLY_OVERLAYS_IDX("spi") \ | |
| 1536 | + CHECK_APPLY_OVERLAYS_IDX("uart") \ | |
| 1537 | + CHECK_APPLY_OVERLAYS_IDX("can") \ | |
| 1538 | + CHECK_APPLY_OVERLAYS_IDX("pwm") \ | |
| 1539 | + CHECK_APPLY_OVERLAYS_DTBO("extra") \ | |
| 1540 | + | |
| 1541 | + | |
| 1542 | +#define MMC_BOOT_WITH_FDT_OVERLAY \ | |
| 1543 | + "mmc dev ${mmcdev};" \ | |
| 1544 | + "run mmcargs; run loadenvconf;" \ | |
| 1545 | + "run loadimage; run loadfdt; " \ | |
| 1546 | + FDT_ENTRY_DEF_SETTINGS \ | |
| 1547 | + "run bootos; " \ | |
| 1548 | + | |
| 1549 | +#endif /* __IGKBOARD_DTOVERLAY_H */ | |
| 1550 | diff --git a/include/configs/igkboard-imx6ull.h b/include/configs/igkboard-imx6ull.h | |
| 1551 | new file mode 100644 | |
| 1552 | index 00000000..11c871ee | |
| 1553 | --- /dev/null | |
| 1554 | +++ b/include/configs/igkboard-imx6ull.h | |
| 1555 | @@ -0,0 +1,111 @@ | |
| 1556 | +/* SPDX-License-Identifier: GPL-2.0+ */ | |
| 1557 | +/* | |
| 1558 | + * Copyright (C) 2023 LingYun IoT System Studio | |
| 1559 | + * | |
| 1560 | + * Configuration settings for LingYun IGKBoard(IoT Gateway Kits Board) based on i.MX6ULL | |
| 1561 | + */ | |
| 1562 | +#ifndef __IGKBOARD_6ULL_CONFIG_H | |
| 1563 | +#define __IGKBOARD_6ULL_CONFIG_H | |
| 1564 | + | |
| 1565 | +#include <asm/arch/imx-regs.h> | |
| 1566 | +#include <linux/sizes.h> | |
| 1567 | +#include <linux/stringify.h> | |
| 1568 | +#include "mx6_common.h" | |
| 1569 | +#include <asm/mach-imx/gpio.h> | |
| 1570 | +#include "imx_env.h" | |
| 1571 | +#include "igkboard-dtoverlay.h" | |
| 1572 | + | |
| 1573 | +#define is_mx6ull_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6ULL_9X9_EVK) | |
| 1574 | + | |
| 1575 | +#ifdef CONFIG_TARGET_MX6ULL_9X9_EVK | |
| 1576 | +#define PHYS_SDRAM_SIZE SZ_256M | |
| 1577 | +#define BOOTARGS_CMA_SIZE "cma=96M " | |
| 1578 | +#else | |
| 1579 | +#define PHYS_SDRAM_SIZE SZ_512M | |
| 1580 | +#define BOOTARGS_CMA_SIZE "" | |
| 1581 | +/* DCDC used on 14x14 EVK, no PMIC */ | |
| 1582 | +#undef CONFIG_LDO_BYPASS_CHECK | |
| 1583 | +#endif | |
| 1584 | + | |
| 1585 | +#define CFG_MXC_UART_BASE UART1_BASE | |
| 1586 | + | |
| 1587 | +/* MMC Configs */ | |
| 1588 | +#ifdef CONFIG_FSL_USDHC | |
| 1589 | +#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR | |
| 1590 | + | |
| 1591 | +/* NAND pin conflicts with usdhc2 */ | |
| 1592 | +#ifdef CONFIG_NAND_MXS | |
| 1593 | +#define CONFIG_SYS_FSL_USDHC_NUM 1 | |
| 1594 | +#else | |
| 1595 | +#define CONFIG_SYS_FSL_USDHC_NUM 2 | |
| 1596 | +#endif | |
| 1597 | + | |
| 1598 | +#endif | |
| 1599 | + | |
| 1600 | + | |
| 1601 | +#ifdef CONFIG_NAND_BOOT | |
| 1602 | +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs)" | |
| 1603 | +#else | |
| 1604 | +#define MFG_NAND_PARTITION "" | |
| 1605 | +#endif | |
| 1606 | + | |
| 1607 | +#define CFG_MFG_ENV_SETTINGS \ | |
| 1608 | + CFG_MFG_ENV_SETTINGS_DEFAULT \ | |
| 1609 | + "initrd_addr=0x86800000\0" \ | |
| 1610 | + "initrd_high=0xffffffff\0" \ | |
| 1611 | + "emmc_dev=1\0"\ | |
| 1612 | + "emmc_ack=1\0"\ | |
| 1613 | + "sd_dev=1\0" \ | |
| 1614 | + "mtdparts=" MFG_NAND_PARTITION \ | |
| 1615 | + "\0"\ | |
| 1616 | + | |
| 1617 | +#define CFG_EXTRA_ENV_SETTINGS \ | |
| 1618 | + "console=ttymxc0\0" \ | |
| 1619 | + "upmode=fastboot 0\0" \ | |
| 1620 | + "envconf=config.txt\0" \ | |
| 1621 | + "image=zImage\0" \ | |
| 1622 | + "board=igkboard-imx6ull\0" \ | |
| 1623 | + "fdt_file=igkboard-imx6ull.dtb\0" \ | |
| 1624 | + "fdt_size=0x10000\0" \ | |
| 1625 | + "fdt_addr=0x83000000\0" \ | |
| 1626 | + "dtbo_addr=0x83010000\0" \ | |
| 1627 | + "dtbo_dir=overlays\0" \ | |
| 1628 | + "splashimage=0x8c000000\0" \ | |
| 1629 | + "ipaddr=192.168.2.22\0" \ | |
| 1630 | + "serverip=192.168.2.2\0" \ | |
| 1631 | + "mmcpart=1\0" \ | |
| 1632 | + "mmcargs=setenv bootargs console=${console},${baudrate} root=/dev/mmcblk${mmc_no}p2 rootwait rw net.ifnames=0\0" \ | |
| 1633 | + "loadenvconf=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${envconf};env import -t ${loadaddr} ${filesize}\0" \ | |
| 1634 | + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ | |
| 1635 | + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ | |
| 1636 | + "bootos=bootz ${loadaddr} - ${fdt_addr}\0" \ | |
| 1637 | + "mmcboot=mmc dev ${mmcdev};run mmcargs;run loadimage;run loadfdt;run bootos\0" \ | |
| 1638 | + "netboot=tftp $loadaddr $image; tftp $fdt_addr ${fdt_file}; run mmcargs; run bootos\0" \ | |
| 1639 | + "bbl=tftp ${loadaddr} u-boot-${board}.imx && mmc dev ${mmcdev} 1 && mmc write ${loadaddr} 2 0x800\0" \ | |
| 1640 | + "bdtb=tftp $fdt_addr $fdt_file && fatwrite mmc 1:1 $fdt_addr $fdt_file $filesize\0" \ | |
| 1641 | + "bker=tftp $loadaddr $image&& fatwrite mmc 1:1 $loadaddr $image $filesize\0" \ | |
| 1642 | + "bsys=run bdtb && run bker\0" | |
| 1643 | + | |
| 1644 | +#ifdef IGKBOARD_DTOVERLAY_SUPPORT | |
| 1645 | +#undef CONFIG_BOOTCOMMAND | |
| 1646 | +#define CONFIG_BOOTCOMMAND MMC_BOOT_WITH_FDT_OVERLAY | |
| 1647 | +#endif | |
| 1648 | + | |
| 1649 | +/* Miscellaneous configurable options */ | |
| 1650 | + | |
| 1651 | +/* Physical Memory Map */ | |
| 1652 | +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR | |
| 1653 | + | |
| 1654 | +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM | |
| 1655 | +#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
| 1656 | +#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
| 1657 | + | |
| 1658 | +#define CONFIG_ETHPRIME "eth1" | |
| 1659 | + | |
| 1660 | +#ifndef CONFIG_SPL_BUILD | |
| 1661 | +#if defined(CONFIG_DM_VIDEO) | |
| 1662 | +#define CONFIG_VIDEO_LINK | |
| 1663 | +#endif | |
| 1664 | +#endif | |
| 1665 | + | |
| 1666 | +#endif | |
