diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
|
index 7b1a129e6..1d5c6e770 100644
|
--- a/arch/arm64/boot/dts/freescale/Makefile
|
+++ b/arch/arm64/boot/dts/freescale/Makefile
|
@@ -412,3 +412,5 @@ dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb \
|
s32v234-sbc.dtb
|
dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-sof-cs42888.dtb imx8qm-mek-sof-wm8960.dtb \
|
imx8qm-mek-revd-sof-wm8962.dtb imx8qm-mek-sof.dtb
|
+
|
+dtb-$(CONFIG_ARCH_MXC) += igkboard-imx8mp.dtb
|
diff --git a/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts b/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts
|
new file mode 100644
|
index 000000000..ce38a5b4a
|
--- /dev/null
|
+++ b/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts
|
@@ -0,0 +1,782 @@
|
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
+/*
|
+ * Device Tree Source for LingYun IGKBoard(IoT Gateway Kits Board) - imx8mp
|
+ * Copyright 2023 LingYun IoT System Studio.
|
+ */
|
+
|
+/dts-v1/;
|
+
|
+#include <dt-bindings/usb/pd.h>
|
+#include "imx8mp.dtsi"
|
+
|
+/*+------------------------+
|
+ | root node |
|
+ +------------------------+*/
|
+/ {
|
+ model = "LingYun IoT Gateway Kits Board based on i.MX8MP";
|
+ compatible = "lingyun,igkboard-imx8mp", "fsl,imx8mp";
|
+
|
+ /* console */
|
+ chosen {
|
+ stdout-path = &uart2;
|
+ };
|
+
|
+ /* MT53D512M32D2DS-053 WT:D, 2GB LPDDR4 */
|
+ memory@80000000 {
|
+ device_type = "memory";
|
+ reg = <0x0 0x80000000 0 0x40000000>;
|
+ };
|
+
|
+ leds {
|
+ compatible = "gpio-leds";
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_leds>;
|
+ status = "okay";
|
+
|
+ sysled {
|
+ label = "sysled";
|
+ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
|
+ default-state = "on";
|
+ linux,default-trigger = "heartbeat";
|
+ };
|
+
|
+ ledred {
|
+ label = "redled";
|
+ gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
|
+ default-state = "off";
|
+ };
|
+
|
+ ledgreen {
|
+ label = "greenled";
|
+ gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
|
+ default-state = "off";
|
+ };
|
+
|
+ ledblue {
|
+ label = "blueled";
|
+ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
|
+ default-state = "on";
|
+ linux,default-trigger = "timer";
|
+ };
|
+ };
|
+
|
+ keys {
|
+ compatible = "gpio-keys";
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_keys>;
|
+ status = "okay";
|
+
|
+ key1 {
|
+ label = "K1";
|
+ gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
|
+ linux,code = <BTN_1>;
|
+ };
|
+
|
+ key2 {
|
+ label = "K2";
|
+ gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
|
+ linux,code = <BTN_2>;
|
+ };
|
+
|
+ key3 {
|
+ label = "K3";
|
+ gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
|
+ linux,code = <BTN_3>;
|
+ };
|
+
|
+ key4 {
|
+ label = "K4";
|
+ gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
|
+ linux,code = <BTN_4>;
|
+ };
|
+ };
|
+
|
+ sound-wm8960 {
|
+ compatible = "fsl,imx-audio-wm8960";
|
+ model = "wm8960-audio";
|
+ audio-cpu = <&sai3>;
|
+ audio-codec = <&codec>;
|
+ audio-asrc = <&easrc>;
|
+ //hp-det-gpio = <&gpio4 29 0>;
|
+ audio-routing =
|
+ "Headphone Jack", "HP_L",
|
+ "Headphone Jack", "HP_R",
|
+ "Ext Spk", "SPK_LP",
|
+ "Ext Spk", "SPK_LN",
|
+ "Ext Spk", "SPK_RP",
|
+ "Ext Spk", "SPK_RN",
|
+ "LINPUT1", "Mic Jack",
|
+ "LINPUT3", "Mic Jack",
|
+ "Mic Jack", "MICB";
|
+ };
|
+};
|
+
|
+/*+------------------------+
|
+ | power key & reset |
|
+ +------------------------+*/
|
+
|
+&snvs_pwrkey {
|
+ status = "okay";
|
+};
|
+
|
+&wdog1 {
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_wdog>;
|
+ fsl,ext-reset-output;
|
+ status = "okay";
|
+};
|
+
|
+/*+------------------------+
|
+ | console usart2 |
|
+ +------------------------+*/
|
+&uart2 {
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_uart2>;
|
+ status = "okay";
|
+};
|
+
|
+/*+------------------------+
|
+ | 8GB eMMC on SD3 |
|
+ +------------------------+*/
|
+
|
+/* KLM8G1GETF-B041 8GB eMMC */
|
+&usdhc3 {
|
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
+ pinctrl-0 = <&pinctrl_usdhc3>;
|
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
+ bus-width = <8>;
|
+ non-removable;
|
+ status = "okay";
|
+};
|
+
|
+/*+------------------------+
|
+ | TF Card on SD2 |
|
+ +------------------------+*/
|
+
|
+&usdhc2 {
|
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
+ bus-width = <4>;
|
+ no-1-8-v;
|
+ status = "okay";
|
+};
|
+
|
+/*+------------------------+
|
+ | Typec USB for download |
|
+ +------------------------+*/
|
+
|
+&usb3_phy0 {
|
+ fsl,phy-tx-vref-tune = <6>;
|
+ fsl,phy-tx-rise-tune = <0>;
|
+ fsl,phy-tx-preemp-amp-tune = <3>;
|
+ fsl,phy-comp-dis-tune = <7>;
|
+ fsl,pcs-tx-deemph-3p5db = <0x21>;
|
+ fsl,phy-pcs-tx-swing-full = <0x7f>;
|
+ status = "okay";
|
+};
|
+
|
+&usb3_0 {
|
+ status = "okay";
|
+};
|
+
|
+&usb_dwc3_0 {
|
+ dr_mode = "peripheral";
|
+ hnp-disable;
|
+ srp-disable;
|
+ adp-disable;
|
+ status = "okay";
|
+};
|
+
|
+/*+------------------------+
|
+ | 2xUSB Host on USB Hub |
|
+ +------------------------+*/
|
+
|
+/* Renesas USB 3.0 Hub uPD720210 */
|
+&usb3_phy1 {
|
+ fsl,phy-tx-preemp-amp-tune = <2>;
|
+ status = "okay";
|
+};
|
+
|
+&usb3_1 {
|
+ status = "okay";
|
+};
|
+
|
+&usb_dwc3_1 {
|
+ dr_mode = "host";
|
+ status = "okay";
|
+};
|
+
|
+/*+------------------------+
|
+ | Ethernet |
|
+ +------------------------+*/
|
+
|
+/* First 1000Mbps Ethernet For TSN on ENET */
|
+&eqos {
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_eqos>;
|
+ phy-mode = "rgmii-id";
|
+ phy-handle = <ðphy0>;
|
+ status = "okay";
|
+
|
+ mdio {
|
+ compatible = "snps,dwmac-mdio";
|
+ #address-cells = <1>;
|
+ #size-cells = <0>;
|
+ clock-frequency = <5000000>;
|
+
|
+ ethphy0: ethernet-phy@0 { /* YT8521SH-CA */
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
+ reg = <0>;
|
+ eee-broken-1000t;
|
+ };
|
+ };
|
+};
|
+
|
+/* Second 1000Mbps Ethernet on ENET1, test okay */
|
+&fec {
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_fec>;
|
+ phy-mode = "rgmii-id";
|
+ phy-handle = <ðphy1>;
|
+ fsl,magic-packet;
|
+ status = "okay";
|
+
|
+ mdio {
|
+ #address-cells = <1>;
|
+ #size-cells = <0>;
|
+ clock-frequency = <5000000>;
|
+
|
+ ethphy1: ethernet-phy@0 { /* YT8521SH-CA */
|
+ compatible = "ethernet-phy-ieee802.3-c22";
|
+ reg = <0>;
|
+ eee-broken-1000t;
|
+ };
|
+ };
|
+};
|
+
|
+/*+------------------------+
|
+ | Misc Devices |
|
+ +------------------------+*/
|
+
|
+/* Buzzer */
|
+&pwm1 {
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_pwm1>;
|
+ status = "okay";
|
+};
|
+
|
+&i2c2 {
|
+ clock-frequency = <100000>;
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_i2c2>;
|
+ status = "okay";
|
+
|
+ codec: wm8960@1a {
|
+ compatible = "wlf,wm8960";
|
+ reg = <0x1a>;
|
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>;
|
+ clock-names = "mclk";
|
+ wlf,shared-lrclk;
|
+ };
|
+
|
+ ms1112@4a {
|
+ compatible = "ms,ms1112";
|
+ reg = <0x4a>;
|
+ status = "okay";
|
+ #address-cells = <1>;
|
+ #size-cells = <0>;
|
+
|
+ channel@2 {
|
+ reg = <2>;
|
+ ti,gain = <0>;
|
+ ti,datarate = <3>;
|
+ ti,mode = <1>;
|
+ };
|
+
|
+ channel@3{
|
+ reg = <3>;
|
+ ti,gain = <0>;
|
+ ti,datarate = <3>;
|
+ ti,mode = <1>;
|
+ };
|
+ };
|
+
|
+ rtc1208@6f {
|
+ compatible = "isil,isl1208";
|
+ reg = <0x6f>;
|
+ status = "okay";
|
+ };
|
+};
|
+
|
+/*+------------------------+
|
+ | WM8960 Audio Codec |
|
+ +------------------------+*/
|
+
|
+&sai3 {
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_sai3>;
|
+ assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
|
+ assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
|
+ assigned-clock-rates = <12288000>;
|
+ clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG>, <&clk IMX8MP_CLK_DUMMY>,
|
+ <&audio_blk_ctrl IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1>, <&clk IMX8MP_CLK_DUMMY>,
|
+ <&clk IMX8MP_CLK_DUMMY>;
|
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
|
+ fsl,sai-mclk-direction-output;
|
+ status = "okay";
|
+};
|
+
|
+&easrc {
|
+ fsl,asrc-rate = <48000>;
|
+ status = "okay";
|
+};
|
+
|
+&xcvr {
|
+ #sound-dai-cells = <0>;
|
+ status = "okay";
|
+};
|
+
|
+&sdma2 {
|
+ status = "okay";
|
+};
|
+
|
+/*+------------------------+
|
+ | CAN/RS485 interface |
|
+ +------------------------+*/
|
+/* RS485 */
|
+&uart3 {
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_uart3>;
|
+ status = "okay";
|
+};
|
+
|
+/* CAN */
|
+&flexcan1 {
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_flexcan1>;
|
+ status = "okay";
|
+};
|
+
|
+&flexcan2 {
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_flexcan2>;
|
+ status = "okay";
|
+};
|
+
|
+/*+------------------------+
|
+ | MikroBUS interface |
|
+ +------------------------+*/
|
+
|
+/* Same as RPi 40Pin extend interface: #32 */
|
+&pwm3 {
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_pwm3>;
|
+ status = "okay";
|
+};
|
+
|
+/* Same as RPi 40Pin extend interface: #19, #21, #23, #24 */
|
+&uart1 {
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_uart1>;
|
+ assigned-clocks = <&clk IMX8MP_CLK_UART1>;
|
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
|
+ status = "okay";
|
+};
|
+
|
+/* Same as RPi 40Pin extend interface */
|
+&ecspi2 {
|
+ #address-cells = <1>;
|
+ #size-cells = <0>;
|
+ fsl,spi-num-chipselects = <1>;
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_ecspi2>;
|
+ cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
|
+ status = "okay";
|
+
|
+ spidev@0 {
|
+ compatible = "fsl,spidev", "semtech,sx1301";
|
+ reg = <0>;
|
+ spi-max-frequency = <2000000>;
|
+ };
|
+};
|
+
|
+/* Same as RPi 40Pin extend interface: #3, #5 */
|
+&i2c5 {
|
+ clock-frequency = <100000>;
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_i2c5>;
|
+ status = "okay";
|
+
|
+ hdc1080@40 {
|
+ compatible = "ti,hdc1080";
|
+ reg = <0x40>;
|
+ status = "okay";
|
+ };
|
+
|
+ eeprom@50 {
|
+ compatible = "microchip,24c32", "atmel,24c32";
|
+ reg = <0x50>;
|
+ pagesize = <32>;
|
+ num-addresses = <8>;
|
+ };
|
+};
|
+
|
+/*+------------------------+
|
+ | PCA9450CHN PMIC |
|
+ +------------------------+*/
|
+
|
+&i2c1 {
|
+ clock-frequency = <400000>;
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_i2c1>;
|
+ status = "okay";
|
+
|
+ pmic@25 {
|
+ compatible = "nxp,pca9450c";
|
+ reg = <0x25>;
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_pmic>;
|
+ interrupt-parent = <&gpio1>;
|
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
+
|
+ regulators {
|
+ buck1: BUCK1 {
|
+ regulator-name = "BUCK1";
|
+ regulator-min-microvolt = <600000>;
|
+ regulator-max-microvolt = <2187500>;
|
+ regulator-boot-on;
|
+ regulator-always-on;
|
+ regulator-ramp-delay = <3125>;
|
+ };
|
+
|
+ buck2: BUCK2 {
|
+ regulator-name = "BUCK2";
|
+ regulator-min-microvolt = <600000>;
|
+ regulator-max-microvolt = <2187500>;
|
+ regulator-boot-on;
|
+ regulator-always-on;
|
+ regulator-ramp-delay = <3125>;
|
+ nxp,dvs-run-voltage = <950000>;
|
+ nxp,dvs-standby-voltage = <850000>;
|
+ };
|
+
|
+ buck4: BUCK4{
|
+ regulator-name = "BUCK4";
|
+ regulator-min-microvolt = <600000>;
|
+ regulator-max-microvolt = <3400000>;
|
+ regulator-boot-on;
|
+ regulator-always-on;
|
+ };
|
+
|
+ buck5: BUCK5{
|
+ regulator-name = "BUCK5";
|
+ regulator-min-microvolt = <600000>;
|
+ regulator-max-microvolt = <3400000>;
|
+ regulator-boot-on;
|
+ regulator-always-on;
|
+ };
|
+
|
+ buck6: BUCK6 {
|
+ regulator-name = "BUCK6";
|
+ regulator-min-microvolt = <600000>;
|
+ regulator-max-microvolt = <3400000>;
|
+ regulator-boot-on;
|
+ regulator-always-on;
|
+ };
|
+
|
+ ldo1: LDO1 {
|
+ regulator-name = "LDO1";
|
+ regulator-min-microvolt = <1600000>;
|
+ regulator-max-microvolt = <3300000>;
|
+ regulator-boot-on;
|
+ regulator-always-on;
|
+ };
|
+
|
+ ldo2: LDO2 {
|
+ regulator-name = "LDO2";
|
+ regulator-min-microvolt = <800000>;
|
+ regulator-max-microvolt = <1150000>;
|
+ regulator-boot-on;
|
+ regulator-always-on;
|
+ };
|
+
|
+ ldo3: LDO3 {
|
+ regulator-name = "LDO3";
|
+ regulator-min-microvolt = <800000>;
|
+ regulator-max-microvolt = <3300000>;
|
+ regulator-boot-on;
|
+ regulator-always-on;
|
+ };
|
+
|
+ ldo4: LDO4 {
|
+ regulator-name = "LDO4";
|
+ regulator-min-microvolt = <800000>;
|
+ regulator-max-microvolt = <3300000>;
|
+ regulator-boot-on;
|
+ regulator-always-on;
|
+ };
|
+
|
+ ldo5: LDO5 {
|
+ regulator-name = "LDO5";
|
+ regulator-min-microvolt = <1800000>;
|
+ regulator-max-microvolt = <3300000>;
|
+ regulator-boot-on;
|
+ regulator-always-on;
|
+ };
|
+ };
|
+ };
|
+};
|
+
|
+&iomuxc {
|
+ pinctrl-names = "default";
|
+
|
+ pinctrl_wdog: wdoggrp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
|
+ >;
|
+ };
|
+
|
+ pinctrl_leds: ledsgrp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
|
+ MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x140
|
+ MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x140
|
+ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140
|
+ >;
|
+ };
|
+
|
+ pinctrl_keys: keysgrp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x140
|
+ MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140
|
+ MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x140
|
+ MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x140
|
+ >;
|
+ };
|
+
|
+ pinctrl_pwm1: pwm1grp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT 0x116
|
+ >;
|
+ };
|
+
|
+ pinctrl_pwm3: pwm3grp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x116
|
+ >;
|
+ };
|
+
|
+ pinctrl_uart1: uart1grp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
|
+ MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
|
+ >;
|
+ };
|
+
|
+ pinctrl_uart2: uart2grp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
|
+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
|
+ >;
|
+ };
|
+
|
+ pinctrl_uart3: uart3grp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x82
|
+ MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x82
|
+ >;
|
+ };
|
+
|
+ pinctrl_flexcan1: flexcan1grp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
|
+ MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
|
+ >;
|
+ };
|
+
|
+ pinctrl_flexcan2: flexcan2grp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
|
+ MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
|
+ >;
|
+ };
|
+
|
+ pinctrl_ecspi2: ecspi2grp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
|
+ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
|
+ MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
|
+ MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40000
|
+ >;
|
+ };
|
+
|
+ pinctrl_i2c1: i2c1grp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
|
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
|
+ >;
|
+ };
|
+
|
+ pinctrl_i2c2: i2c2grp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
|
+ MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
|
+ >;
|
+ };
|
+
|
+ pinctrl_i2c5: i2c5grp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_SD1_CMD__I2C5_SDA 0x400001c2
|
+ MX8MP_IOMUXC_SD1_CLK__I2C5_SCL 0x400001c2
|
+ >;
|
+ };
|
+
|
+ pinctrl_sai3: sai3grp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6
|
+ MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6
|
+ MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6
|
+ MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6
|
+ MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6
|
+ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6
|
+ >;
|
+ };
|
+
|
+ pinctrl_pmic: pmicirq {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
|
+ >;
|
+ };
|
+
|
+ pinctrl_usdhc2_gpio: usdhc2grp-gpio {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
|
+ >;
|
+ };
|
+
|
+ pinctrl_usdhc2: usdhc2grp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
|
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
|
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
|
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
|
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
|
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
|
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
+ >;
|
+ };
|
+
|
+ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
|
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
|
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
|
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
|
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
|
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
|
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
+ >;
|
+ };
|
+
|
+ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
|
+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
|
+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
|
+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
|
+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
|
+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
|
+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
+ >;
|
+ };
|
+
|
+ pinctrl_usdhc3: usdhc3grp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
|
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
|
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
|
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
|
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
|
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
|
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
|
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
|
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
|
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
|
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
|
+ >;
|
+ };
|
+
|
+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
|
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
|
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
|
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
|
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
|
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
|
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
|
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
|
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
|
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
|
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
|
+ >;
|
+ };
|
+
|
+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
|
+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
|
+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
|
+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
|
+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
|
+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
|
+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
|
+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
|
+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
|
+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
|
+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
|
+ >;
|
+ };
|
+
|
+ pinctrl_eqos: eqosgrp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
|
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
|
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
|
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
|
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
|
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
|
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
|
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
|
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
|
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
|
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
|
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
|
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
|
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
|
+ >;
|
+ };
|
+
|
+ pinctrl_fec: fecgrp {
|
+ fsl,pins = <
|
+ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
|
+ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
|
+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
|
+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
|
+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
|
+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
|
+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
|
+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
|
+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
|
+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
|
+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
|
+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
|
+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
|
+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
|
+ >;
|
+ };
|
+};
|
diff --git a/arch/arm64/configs/igkboard-imx8mp_defconfig b/arch/arm64/configs/igkboard-imx8mp_defconfig
|
new file mode 100644
|
index 000000000..b0f923742
|
--- /dev/null
|
+++ b/arch/arm64/configs/igkboard-imx8mp_defconfig
|
@@ -0,0 +1,1103 @@
|
+CONFIG_SYSVIPC=y
|
+CONFIG_POSIX_MQUEUE=y
|
+CONFIG_AUDIT=y
|
+CONFIG_NO_HZ_IDLE=y
|
+CONFIG_HIGH_RES_TIMERS=y
|
+CONFIG_BPF_SYSCALL=y
|
+CONFIG_BPF_JIT=y
|
+CONFIG_PREEMPT=y
|
+CONFIG_IRQ_TIME_ACCOUNTING=y
|
+CONFIG_BSD_PROCESS_ACCT=y
|
+CONFIG_BSD_PROCESS_ACCT_V3=y
|
+CONFIG_TASKSTATS=y
|
+CONFIG_TASK_XACCT=y
|
+CONFIG_TASK_IO_ACCOUNTING=y
|
+CONFIG_IKCONFIG=y
|
+CONFIG_IKCONFIG_PROC=y
|
+CONFIG_NUMA_BALANCING=y
|
+CONFIG_MEMCG=y
|
+CONFIG_BLK_CGROUP=y
|
+CONFIG_CGROUP_PIDS=y
|
+CONFIG_CGROUP_FREEZER=y
|
+CONFIG_CGROUP_HUGETLB=y
|
+CONFIG_CPUSETS=y
|
+CONFIG_CGROUP_DEVICE=y
|
+CONFIG_CGROUP_CPUACCT=y
|
+CONFIG_CGROUP_PERF=y
|
+CONFIG_CGROUP_BPF=y
|
+CONFIG_NAMESPACES=y
|
+CONFIG_USER_NS=y
|
+CONFIG_SCHED_AUTOGROUP=y
|
+CONFIG_RELAY=y
|
+CONFIG_BLK_DEV_INITRD=y
|
+CONFIG_EXPERT=y
|
+CONFIG_KALLSYMS_ALL=y
|
+CONFIG_PROFILING=y
|
+CONFIG_ARCH_KEEMBAY=y
|
+CONFIG_ARCH_NXP=y
|
+CONFIG_ARCH_LAYERSCAPE=y
|
+CONFIG_ARCH_MXC=y
|
+CONFIG_ARCH_S32=y
|
+CONFIG_SOC_S32V234=y
|
+CONFIG_ARM64_VA_BITS_48=y
|
+CONFIG_SCHED_MC=y
|
+CONFIG_SCHED_SMT=y
|
+CONFIG_NUMA=y
|
+CONFIG_KEXEC=y
|
+CONFIG_KEXEC_FILE=y
|
+CONFIG_CRASH_DUMP=y
|
+CONFIG_XEN=y
|
+CONFIG_ARCH_FORCE_MAX_ORDER=14
|
+CONFIG_COMPAT=y
|
+CONFIG_RANDOMIZE_BASE=y
|
+CONFIG_PM_DEBUG=y
|
+CONFIG_PM_TEST_SUSPEND=y
|
+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
|
+CONFIG_ENERGY_MODEL=y
|
+CONFIG_ARM_PSCI_CPUIDLE=y
|
+CONFIG_CPU_FREQ=y
|
+CONFIG_CPU_FREQ_STAT=y
|
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
|
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
|
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
|
+CONFIG_CPUFREQ_DT=y
|
+CONFIG_ACPI_CPPC_CPUFREQ=m
|
+CONFIG_ARM_SCPI_CPUFREQ=y
|
+CONFIG_ARM_IMX_CPUFREQ_DT=y
|
+CONFIG_ARM_SCMI_CPUFREQ=y
|
+CONFIG_QORIQ_CPUFREQ=y
|
+CONFIG_ACPI=y
|
+CONFIG_ACPI_APEI=y
|
+CONFIG_ACPI_APEI_GHES=y
|
+CONFIG_ACPI_APEI_MEMORY_FAILURE=y
|
+CONFIG_ACPI_APEI_EINJ=y
|
+CONFIG_VIRTUALIZATION=y
|
+CONFIG_KVM=y
|
+CONFIG_JUMP_LABEL=y
|
+CONFIG_MODULES=y
|
+CONFIG_MODULE_UNLOAD=y
|
+CONFIG_MODVERSIONS=y
|
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
+# CONFIG_COMPAT_BRK is not set
|
+CONFIG_KSM=y
|
+CONFIG_MEMORY_FAILURE=y
|
+CONFIG_TRANSPARENT_HUGEPAGE=y
|
+CONFIG_NET=y
|
+CONFIG_PACKET=y
|
+CONFIG_UNIX=y
|
+CONFIG_TLS=y
|
+CONFIG_TLS_DEVICE=y
|
+CONFIG_INET=y
|
+CONFIG_IP_MULTICAST=y
|
+CONFIG_IP_PNP=y
|
+CONFIG_IP_PNP_DHCP=y
|
+CONFIG_IP_PNP_BOOTP=y
|
+CONFIG_IPV6_SIT=m
|
+CONFIG_NETFILTER=y
|
+CONFIG_BRIDGE_NETFILTER=m
|
+CONFIG_NETFILTER_NETLINK_OSF=m
|
+CONFIG_NF_CONNTRACK=m
|
+CONFIG_NF_CONNTRACK_EVENTS=y
|
+CONFIG_NF_TABLES=y
|
+CONFIG_NF_TABLES_INET=y
|
+CONFIG_NF_TABLES_NETDEV=y
|
+CONFIG_NFT_CT=m
|
+CONFIG_NFT_MASQ=m
|
+CONFIG_NFT_NAT=m
|
+CONFIG_NFT_COMPAT=m
|
+CONFIG_NFT_DUP_NETDEV=m
|
+CONFIG_NFT_FWD_NETDEV=m
|
+CONFIG_NF_FLOW_TABLE=m
|
+CONFIG_NETFILTER_XT_MARK=m
|
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
|
+CONFIG_NETFILTER_XT_TARGET_LOG=m
|
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
|
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
|
+CONFIG_NETFILTER_XT_MATCH_IPVS=m
|
+CONFIG_IP_VS=m
|
+CONFIG_NF_SOCKET_IPV4=m
|
+CONFIG_NF_TPROXY_IPV4=m
|
+CONFIG_IP_NF_IPTABLES=m
|
+CONFIG_IP_NF_FILTER=m
|
+CONFIG_IP_NF_TARGET_REJECT=m
|
+CONFIG_IP_NF_NAT=m
|
+CONFIG_IP_NF_TARGET_MASQUERADE=m
|
+CONFIG_IP_NF_MANGLE=m
|
+CONFIG_NF_SOCKET_IPV6=m
|
+CONFIG_NF_TPROXY_IPV6=m
|
+CONFIG_IP6_NF_IPTABLES=m
|
+CONFIG_IP6_NF_FILTER=m
|
+CONFIG_IP6_NF_TARGET_REJECT=m
|
+CONFIG_IP6_NF_MANGLE=m
|
+CONFIG_IP6_NF_NAT=m
|
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
|
+CONFIG_NF_TABLES_BRIDGE=m
|
+CONFIG_BRIDGE_NF_EBTABLES=m
|
+CONFIG_BRIDGE=y
|
+CONFIG_BRIDGE_VLAN_FILTERING=y
|
+CONFIG_NET_DSA=m
|
+CONFIG_VLAN_8021Q_GVRP=y
|
+CONFIG_VLAN_8021Q_MVRP=y
|
+CONFIG_LLC2=y
|
+CONFIG_NET_SCHED=y
|
+CONFIG_NET_SCH_MULTIQ=m
|
+CONFIG_NET_SCH_CBS=m
|
+CONFIG_NET_SCH_ETF=m
|
+CONFIG_NET_SCH_TAPRIO=m
|
+CONFIG_NET_SCH_MQPRIO=m
|
+CONFIG_NET_SCH_INGRESS=m
|
+CONFIG_NET_CLS_BASIC=m
|
+CONFIG_NET_CLS_U32=m
|
+CONFIG_NET_CLS_FLOWER=m
|
+CONFIG_NET_CLS_ACT=y
|
+CONFIG_NET_ACT_GACT=m
|
+CONFIG_NET_ACT_MIRRED=m
|
+CONFIG_NET_ACT_SKBEDIT=m
|
+CONFIG_NET_ACT_GATE=m
|
+CONFIG_TSN=y
|
+CONFIG_QRTR=m
|
+CONFIG_QRTR_SMD=m
|
+CONFIG_QRTR_TUN=m
|
+CONFIG_NET_PKTGEN=m
|
+CONFIG_CAN=y
|
+CONFIG_CAN_ISOTP=y
|
+CONFIG_BT=y
|
+CONFIG_BT_RFCOMM=y
|
+CONFIG_BT_RFCOMM_TTY=y
|
+CONFIG_BT_BNEP=y
|
+CONFIG_BT_BNEP_MC_FILTER=y
|
+CONFIG_BT_BNEP_PROTO_FILTER=y
|
+CONFIG_BT_HIDP=y
|
+CONFIG_BT_LEDS=y
|
+# CONFIG_BT_DEBUGFS is not set
|
+CONFIG_BT_HCIBTUSB=m
|
+CONFIG_BT_HCIUART=y
|
+CONFIG_BT_HCIUART_BCSP=y
|
+CONFIG_BT_HCIUART_ATH3K=y
|
+CONFIG_BT_HCIUART_LL=y
|
+CONFIG_BT_HCIUART_3WIRE=y
|
+CONFIG_BT_HCIUART_BCM=y
|
+CONFIG_BT_HCIUART_QCA=y
|
+CONFIG_BT_HCIVHCI=y
|
+CONFIG_BT_NXPUART=m
|
+CONFIG_CFG80211=y
|
+CONFIG_NL80211_TESTMODE=y
|
+CONFIG_CFG80211_WEXT=y
|
+CONFIG_MAC80211=y
|
+CONFIG_MAC80211_LEDS=y
|
+CONFIG_NFC=m
|
+CONFIG_NFC_NCI=m
|
+CONFIG_NFC_S3FWRN5_I2C=m
|
+CONFIG_PCI=y
|
+CONFIG_PCIEPORTBUS=y
|
+CONFIG_PCI_IOV=y
|
+CONFIG_PCI_PASID=y
|
+CONFIG_HOTPLUG_PCI=y
|
+CONFIG_HOTPLUG_PCI_ACPI=y
|
+CONFIG_PCI_HOST_GENERIC=y
|
+CONFIG_PCI_XGENE=y
|
+CONFIG_PCIE_ALTERA=y
|
+CONFIG_PCIE_ALTERA_MSI=y
|
+CONFIG_PCI_HOST_THUNDER_PEM=y
|
+CONFIG_PCI_HOST_THUNDER_ECAM=y
|
+CONFIG_PCI_IMX6_HOST=y
|
+CONFIG_PCI_IMX6_EP=y
|
+CONFIG_PCI_LAYERSCAPE=y
|
+CONFIG_PCI_HISI=y
|
+CONFIG_PCIE_KIRIN=y
|
+CONFIG_PCI_MESON=m
|
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
|
+CONFIG_PCI_ENDPOINT=y
|
+CONFIG_PCI_ENDPOINT_CONFIGFS=y
|
+CONFIG_PCI_EPF_TEST=y
|
+CONFIG_DEVTMPFS=y
|
+CONFIG_DEVTMPFS_MOUNT=y
|
+CONFIG_FW_LOADER_USER_HELPER=y
|
+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
|
+CONFIG_BRCMSTB_GISB_ARB=y
|
+CONFIG_VEXPRESS_CONFIG=y
|
+CONFIG_FSL_MC_UAPI_SUPPORT=y
|
+CONFIG_ARM_SCMI_PROTOCOL=y
|
+CONFIG_ARM_SCPI_PROTOCOL=y
|
+CONFIG_EFI_CAPSULE_LOADER=y
|
+CONFIG_IMX_DSP=y
|
+CONFIG_IMX_SCU=y
|
+CONFIG_IMX_SCU_PD=y
|
+CONFIG_IMX_EL_ENCLAVE=y
|
+CONFIG_GNSS=m
|
+CONFIG_GNSS_MTK_SERIAL=m
|
+CONFIG_MTD=y
|
+CONFIG_MTD_CMDLINE_PARTS=y
|
+CONFIG_MTD_BLOCK=y
|
+CONFIG_MTD_CFI=y
|
+CONFIG_MTD_CFI_ADV_OPTIONS=y
|
+CONFIG_MTD_CFI_INTELEXT=y
|
+CONFIG_MTD_CFI_AMDSTD=y
|
+CONFIG_MTD_CFI_STAA=y
|
+CONFIG_MTD_PHYSMAP=y
|
+CONFIG_MTD_PHYSMAP_OF=y
|
+CONFIG_MTD_DATAFLASH=y
|
+CONFIG_MTD_SST25L=y
|
+CONFIG_MTD_RAW_NAND=y
|
+CONFIG_MTD_NAND_DENALI_DT=y
|
+CONFIG_MTD_NAND_GPMI_NAND=y
|
+CONFIG_MTD_NAND_FSL_IFC=y
|
+CONFIG_MTD_SPI_NAND=y
|
+CONFIG_MTD_SPI_NOR=y
|
+# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
|
+CONFIG_MTD_UBI=y
|
+CONFIG_BLK_DEV_LOOP=y
|
+CONFIG_BLK_DEV_NBD=m
|
+CONFIG_XEN_BLKDEV_BACKEND=m
|
+CONFIG_VIRTIO_BLK=y
|
+CONFIG_BLK_DEV_NVME=y
|
+CONFIG_SRAM=y
|
+CONFIG_PCI_ENDPOINT_TEST=y
|
+CONFIG_EEPROM_AT24=y
|
+CONFIG_UACCE=m
|
+# CONFIG_SCSI_PROC_FS is not set
|
+CONFIG_BLK_DEV_SD=y
|
+CONFIG_SCSI_SAS_ATA=y
|
+CONFIG_SCSI_HISI_SAS=y
|
+CONFIG_SCSI_HISI_SAS_PCI=y
|
+CONFIG_MEGARAID_SAS=y
|
+CONFIG_SCSI_MPT3SAS=m
|
+CONFIG_ATA=y
|
+CONFIG_SATA_AHCI=y
|
+CONFIG_SATA_AHCI_PLATFORM=y
|
+CONFIG_AHCI_IMX=y
|
+CONFIG_AHCI_CEVA=y
|
+CONFIG_AHCI_XGENE=y
|
+CONFIG_AHCI_QORIQ=y
|
+CONFIG_SATA_SIL24=y
|
+CONFIG_PATA_OF_PLATFORM=y
|
+CONFIG_MD=y
|
+CONFIG_BLK_DEV_MD=m
|
+CONFIG_BLK_DEV_DM=m
|
+CONFIG_DM_CRYPT=m
|
+CONFIG_DM_MIRROR=m
|
+CONFIG_DM_ZERO=m
|
+CONFIG_NETDEVICES=y
|
+CONFIG_MACVLAN=m
|
+CONFIG_MACVTAP=m
|
+CONFIG_TUN=y
|
+CONFIG_VETH=m
|
+CONFIG_VIRTIO_NET=y
|
+CONFIG_NET_DSA_MSCC_FELIX=m
|
+CONFIG_NET_DSA_SJA1105=m
|
+CONFIG_NET_DSA_SJA1105_PTP=y
|
+CONFIG_NET_DSA_SJA1105_TAS=y
|
+CONFIG_NET_DSA_SJA1105_VL=y
|
+CONFIG_AMD_XGBE=y
|
+CONFIG_ATL1C=m
|
+CONFIG_BCMGENET=m
|
+CONFIG_BNX2X=m
|
+CONFIG_SYSTEMPORT=m
|
+CONFIG_MACB=y
|
+CONFIG_THUNDER_NIC_PF=y
|
+CONFIG_FEC=y
|
+CONFIG_FEC_UIO=y
|
+CONFIG_FSL_FMAN=y
|
+CONFIG_FSL_DPAA_ETH=y
|
+CONFIG_FSL_DPAA2_ETH=y
|
+CONFIG_FSL_DPAA2_MAC=y
|
+CONFIG_FSL_DPAA2_SWITCH=y
|
+CONFIG_FSL_ENETC=y
|
+CONFIG_FSL_ENETC_VF=y
|
+CONFIG_FSL_ENETC_QOS=y
|
+CONFIG_ENETC_TSN=y
|
+CONFIG_HIX5HD2_GMAC=y
|
+CONFIG_HNS_DSAF=y
|
+CONFIG_HNS_ENET=y
|
+CONFIG_HNS3=y
|
+CONFIG_HNS3_HCLGE=y
|
+CONFIG_HNS3_ENET=y
|
+CONFIG_E1000=y
|
+CONFIG_E1000E=y
|
+CONFIG_IGB=y
|
+CONFIG_IGBVF=y
|
+CONFIG_MVMDIO=y
|
+CONFIG_SKY2=y
|
+CONFIG_MLX4_EN=m
|
+CONFIG_MLX5_CORE=m
|
+CONFIG_MLX5_CORE_EN=y
|
+CONFIG_MSCC_OCELOT_SWITCH=y
|
+CONFIG_QCOM_EMAC=m
|
+CONFIG_RMNET=m
|
+CONFIG_SMC91X=y
|
+CONFIG_SMSC911X=y
|
+CONFIG_STMMAC_ETH=y
|
+CONFIG_DWMAC_GENERIC=m
|
+CONFIG_AQUANTIA_PHY=y
|
+CONFIG_BROADCOM_PHY=m
|
+CONFIG_BCM54140_PHY=m
|
+CONFIG_MARVELL_PHY=m
|
+CONFIG_MARVELL_10G_PHY=m
|
+CONFIG_MICREL_PHY=y
|
+CONFIG_MICROSEMI_PHY=y
|
+CONFIG_NXP_C45_TJA11XX_PHY=y
|
+CONFIG_NXP_TJA11XX_PHY=y
|
+CONFIG_AT803X_PHY=y
|
+CONFIG_REALTEK_PHY=y
|
+CONFIG_ROCKCHIP_PHY=y
|
+CONFIG_VITESSE_PHY=y
|
+CONFIG_CAN_FLEXCAN=y
|
+CONFIG_MDIO_BITBANG=y
|
+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
|
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
|
+CONFIG_USB_PEGASUS=m
|
+CONFIG_USB_RTL8150=m
|
+CONFIG_USB_RTL8152=y
|
+CONFIG_USB_LAN78XX=m
|
+CONFIG_USB_USBNET=y
|
+CONFIG_USB_NET_AX8817X=m
|
+CONFIG_USB_NET_AX88179_178A=m
|
+CONFIG_USB_NET_CDCETHER=m
|
+CONFIG_USB_NET_CDC_NCM=m
|
+CONFIG_USB_NET_DM9601=m
|
+CONFIG_USB_NET_SR9800=m
|
+CONFIG_USB_NET_SMSC75XX=m
|
+CONFIG_USB_NET_SMSC95XX=m
|
+CONFIG_USB_NET_NET1080=m
|
+CONFIG_USB_NET_PLUSB=m
|
+CONFIG_USB_NET_MCS7830=m
|
+CONFIG_USB_NET_CDC_SUBSET=m
|
+CONFIG_USB_NET_ZAURUS=m
|
+CONFIG_HOSTAP=y
|
+CONFIG_WL18XX=m
|
+CONFIG_WLCORE_SDIO=m
|
+CONFIG_XEN_NETDEV_BACKEND=m
|
+CONFIG_IVSHMEM_NET=y
|
+CONFIG_INPUT_EVDEV=y
|
+CONFIG_KEYBOARD_ADC=m
|
+CONFIG_KEYBOARD_GPIO=y
|
+CONFIG_KEYBOARD_RPMSG=y
|
+CONFIG_KEYBOARD_SNVS_PWRKEY=y
|
+CONFIG_KEYBOARD_BBNSM_PWRKEY=y
|
+CONFIG_KEYBOARD_IMX_SC_KEY=y
|
+CONFIG_KEYBOARD_CROS_EC=y
|
+CONFIG_INPUT_TOUCHSCREEN=y
|
+CONFIG_TOUCHSCREEN_ATMEL_MXT=m
|
+CONFIG_TOUCHSCREEN_EXC3000=m
|
+CONFIG_TOUCHSCREEN_GOODIX=m
|
+CONFIG_TOUCHSCREEN_EDT_FT5X06=m
|
+CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=m
|
+CONFIG_INPUT_MISC=y
|
+CONFIG_INPUT_PWM_BEEPER=m
|
+CONFIG_INPUT_PWM_VIBRA=m
|
+# CONFIG_SERIO_SERPORT is not set
|
+CONFIG_SERIO_AMBAKMI=y
|
+CONFIG_LEGACY_PTY_COUNT=16
|
+CONFIG_SERIAL_8250=y
|
+CONFIG_SERIAL_8250_CONSOLE=y
|
+CONFIG_SERIAL_8250_EXTENDED=y
|
+CONFIG_SERIAL_8250_SHARE_IRQ=y
|
+CONFIG_SERIAL_8250_DW=y
|
+CONFIG_SERIAL_OF_PLATFORM=y
|
+CONFIG_SERIAL_AMBA_PL011=y
|
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
+CONFIG_SERIAL_IMX=y
|
+CONFIG_SERIAL_IMX_CONSOLE=y
|
+CONFIG_SERIAL_XILINX_PS_UART=y
|
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
|
+CONFIG_SERIAL_FSL_LPUART=y
|
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
|
+CONFIG_SERIAL_FSL_LINFLEXUART=y
|
+CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
|
+CONFIG_SERIAL_DEV_BUS=y
|
+CONFIG_VIRTIO_CONSOLE=y
|
+CONFIG_IPMI_HANDLER=m
|
+CONFIG_IPMI_DEVICE_INTERFACE=m
|
+CONFIG_IPMI_SI=m
|
+CONFIG_TCG_TPM=y
|
+CONFIG_TCG_TIS_I2C_INFINEON=y
|
+CONFIG_I2C_CHARDEV=y
|
+CONFIG_I2C_MUX=y
|
+CONFIG_I2C_MUX_GPIO=y
|
+CONFIG_I2C_MUX_PCA954x=y
|
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
+CONFIG_I2C_GPIO=m
|
+CONFIG_I2C_IMX=y
|
+CONFIG_I2C_IMX_LPI2C=y
|
+CONFIG_I2C_RK3X=y
|
+CONFIG_I2C_RPBUS=y
|
+CONFIG_I2C_CROS_EC_TUNNEL=y
|
+CONFIG_I2C_SLAVE_EEPROM=y
|
+CONFIG_I3C=y
|
+CONFIG_SVC_I3C_MASTER=y
|
+CONFIG_SPI=y
|
+CONFIG_SPI_CADENCE_QUADSPI=y
|
+CONFIG_SPI_DESIGNWARE=m
|
+CONFIG_SPI_DW_DMA=y
|
+CONFIG_SPI_DW_MMIO=m
|
+CONFIG_SPI_FSL_LPSPI=y
|
+CONFIG_SPI_FSL_QUADSPI=y
|
+CONFIG_SPI_NXP_FLEXSPI=y
|
+CONFIG_SPI_IMX=y
|
+CONFIG_SPI_FSL_DSPI=y
|
+CONFIG_SPI_PL022=y
|
+CONFIG_SPI_ROCKCHIP=y
|
+CONFIG_SPI_SPIDEV=y
|
+CONFIG_SPI_SLAVE=y
|
+CONFIG_SPI_SLAVE_TIME=y
|
+CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y
|
+CONFIG_SPMI=y
|
+CONFIG_PPS_CLIENT_GPIO=y
|
+CONFIG_PINCTRL_MAX77620=y
|
+CONFIG_PINCTRL_SINGLE=y
|
+CONFIG_PINCTRL_IMX8MM=y
|
+CONFIG_PINCTRL_IMX8MN=y
|
+CONFIG_PINCTRL_IMX8MP=y
|
+CONFIG_PINCTRL_IMX8MQ=y
|
+CONFIG_PINCTRL_IMX8QM=y
|
+CONFIG_PINCTRL_IMX8QXP=y
|
+CONFIG_PINCTRL_IMX8DXL=y
|
+CONFIG_PINCTRL_IMX8ULP=y
|
+CONFIG_PINCTRL_IMX93=y
|
+CONFIG_PINCTRL_S32V234=y
|
+CONFIG_GPIO_SYSFS=y
|
+CONFIG_GPIO_MXC=y
|
+CONFIG_POWER_RESET_BRCMSTB=y
|
+CONFIG_POWER_RESET_XGENE=y
|
+CONFIG_POWER_RESET_SYSCON=y
|
+CONFIG_SYSCON_REBOOT_MODE=y
|
+CONFIG_BATTERY_SBS=m
|
+CONFIG_BATTERY_BQ27XXX=y
|
+CONFIG_BATTERY_MAX17042=m
|
+CONFIG_CHARGER_BQ25890=m
|
+CONFIG_CHARGER_BQ25980=m
|
+CONFIG_SENSORS_ARM_SCMI=y
|
+CONFIG_SENSORS_ARM_SCPI=y
|
+CONFIG_SENSORS_FP9931=y
|
+CONFIG_SENSORS_LM90=m
|
+CONFIG_SENSORS_PWM_FAN=m
|
+CONFIG_SENSORS_SL28CPLD=m
|
+CONFIG_SENSORS_INA2XX=m
|
+CONFIG_SENSORS_INA3221=m
|
+CONFIG_THERMAL_WRITABLE_TRIPS=y
|
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
|
+CONFIG_CPU_THERMAL=y
|
+CONFIG_THERMAL_EMULATION=y
|
+CONFIG_IMX_SC_THERMAL=y
|
+CONFIG_IMX8MM_THERMAL=y
|
+CONFIG_DEVICE_THERMAL=y
|
+CONFIG_QORIQ_THERMAL=y
|
+CONFIG_WATCHDOG=y
|
+CONFIG_SL28CPLD_WATCHDOG=m
|
+CONFIG_ARM_SP805_WATCHDOG=y
|
+CONFIG_ARM_SBSA_WATCHDOG=y
|
+CONFIG_DW_WATCHDOG=y
|
+CONFIG_IMX2_WDT=y
|
+CONFIG_IMX_SC_WDT=y
|
+CONFIG_IMX7ULP_WDT=y
|
+CONFIG_ARM_SMC_WATCHDOG=y
|
+CONFIG_XEN_WDT=y
|
+CONFIG_MFD_ADP5585=y
|
+CONFIG_MFD_BD9571MWV=y
|
+CONFIG_MFD_AXP20X_I2C=y
|
+CONFIG_MFD_IMX_FLEXIO=y
|
+CONFIG_MFD_HI6421_PMIC=y
|
+CONFIG_MFD_FP9931=y
|
+CONFIG_MFD_MAX77620=y
|
+CONFIG_MFD_MT6397=y
|
+CONFIG_MFD_RK808=y
|
+CONFIG_MFD_SEC_CORE=y
|
+CONFIG_MFD_SL28CPLD=y
|
+CONFIG_MFD_ROHM_BD718XX=y
|
+CONFIG_MFD_WCD934X=m
|
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
+CONFIG_REGULATOR_AXP20X=y
|
+CONFIG_REGULATOR_BD718XX=y
|
+CONFIG_REGULATOR_BD9571MWV=y
|
+CONFIG_REGULATOR_FAN53555=y
|
+CONFIG_REGULATOR_GPIO=y
|
+CONFIG_REGULATOR_HI6421V530=y
|
+CONFIG_REGULATOR_MAX77620=y
|
+CONFIG_REGULATOR_MAX8973=y
|
+CONFIG_REGULATOR_FP9931=y
|
+CONFIG_REGULATOR_MP8859=y
|
+CONFIG_REGULATOR_MT6358=y
|
+CONFIG_REGULATOR_MT6397=y
|
+CONFIG_REGULATOR_PCA9450=y
|
+CONFIG_REGULATOR_PF8X00=y
|
+CONFIG_REGULATOR_PFUZE100=y
|
+CONFIG_REGULATOR_PWM=y
|
+CONFIG_REGULATOR_QCOM_SPMI=y
|
+CONFIG_REGULATOR_RK808=y
|
+CONFIG_REGULATOR_S2MPS11=y
|
+CONFIG_REGULATOR_TPS65132=m
|
+CONFIG_REGULATOR_VCTRL=m
|
+CONFIG_RC_CORE=m
|
+CONFIG_RC_DECODERS=y
|
+CONFIG_IR_IMON_DECODER=m
|
+CONFIG_IR_JVC_DECODER=m
|
+CONFIG_IR_MCE_KBD_DECODER=m
|
+CONFIG_IR_NEC_DECODER=m
|
+CONFIG_IR_RC5_DECODER=m
|
+CONFIG_IR_RC6_DECODER=m
|
+CONFIG_IR_RCMM_DECODER=m
|
+CONFIG_IR_SANYO_DECODER=m
|
+CONFIG_IR_SHARP_DECODER=m
|
+CONFIG_IR_SONY_DECODER=m
|
+CONFIG_IR_XMP_DECODER=m
|
+CONFIG_RC_DEVICES=y
|
+CONFIG_IR_GPIO_CIR=m
|
+CONFIG_MEDIA_SUPPORT=y
|
+CONFIG_MEDIA_SUPPORT_FILTER=y
|
+CONFIG_MEDIA_CAMERA_SUPPORT=y
|
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
|
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
|
+CONFIG_MEDIA_SDR_SUPPORT=y
|
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
|
+# CONFIG_DVB_NET is not set
|
+CONFIG_MEDIA_USB_SUPPORT=y
|
+CONFIG_USB_VIDEO_CLASS=m
|
+CONFIG_V4L_PLATFORM_DRIVERS=y
|
+CONFIG_SDR_PLATFORM_DRIVERS=y
|
+CONFIG_V4L_MEM2MEM_DRIVERS=y
|
+CONFIG_VIDEO_MX8_CAPTURE=y
|
+CONFIG_VIDEO_MXC_CAPTURE=y
|
+CONFIG_VIDEO_MXC_CSI_CAMERA=y
|
+CONFIG_MXC_MIPI_CSI=y
|
+CONFIG_MXC_CAMERA_OV5640_MIPI_V2=y
|
+CONFIG_VIDEO_AMPHION_VPU=y
|
+CONFIG_VIDEO_IMX8_JPEG=m
|
+CONFIG_VIDEO_HANTRO=m
|
+CONFIG_VIDEO_IMX219=m
|
+CONFIG_VIDEO_OV5640=y
|
+CONFIG_VIDEO_OV5645=m
|
+CONFIG_VIDEO_AP1302=y
|
+CONFIG_VIDEO_MT9M114=y
|
+CONFIG_IMX_DPU_CORE=y
|
+CONFIG_IMX8MM_LCDIF_CORE=y
|
+CONFIG_IMX_LCDIFV3_CORE=y
|
+CONFIG_DRM=y
|
+CONFIG_DRM_I2C_NXP_TDA998X=m
|
+CONFIG_DRM_MALI_DISPLAY=m
|
+CONFIG_DRM_NOUVEAU=m
|
+CONFIG_DRM_RCAR_DW_HDMI=m
|
+CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
|
+CONFIG_DRM_PANEL_LVDS=m
|
+CONFIG_DRM_PANEL_SIMPLE=y
|
+CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
|
+CONFIG_DRM_PANEL_RAYDIUM_RM67191=y
|
+CONFIG_DRM_PANEL_RAYDIUM_RM68200=y
|
+CONFIG_DRM_PANEL_ROCKTECK_HIMAX8394F=y
|
+CONFIG_DRM_PANEL_SEIKO_43WVF1G=y
|
+CONFIG_DRM_PANEL_SITRONIX_ST7703=m
|
+CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
|
+CONFIG_DRM_PANEL_WKS_101WX001=y
|
+CONFIG_DRM_DISPLAY_CONNECTOR=m
|
+CONFIG_DRM_LONTIUM_LT8912B=m
|
+CONFIG_DRM_LONTIUM_LT9611=m
|
+CONFIG_DRM_LONTIUM_LT9611UXC=m
|
+CONFIG_DRM_FSL_IMX_LVDS_BRIDGE=y
|
+CONFIG_DRM_NWL_MIPI_DSI=y
|
+CONFIG_DRM_NXP_SEIKO_43WVFIG=y
|
+CONFIG_DRM_PARADE_PS8640=m
|
+CONFIG_DRM_SII902X=m
|
+CONFIG_DRM_SIMPLE_BRIDGE=m
|
+CONFIG_DRM_THINE_THC63LVD1024=m
|
+CONFIG_DRM_TI_SN65DSI86=m
|
+CONFIG_DRM_I2C_ADV7511=y
|
+CONFIG_DRM_I2C_ADV7511_AUDIO=y
|
+CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
|
+CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
|
+CONFIG_DRM_DW_HDMI_GP_AUDIO=y
|
+CONFIG_DRM_DW_HDMI_CEC=m
|
+CONFIG_DRM_ITE_IT6263=y
|
+CONFIG_DRM_ITE_IT6161=y
|
+CONFIG_DRM_IMX=y
|
+CONFIG_DRM_IMX_LCDIF_MUX_DISPLAY=y
|
+CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
|
+CONFIG_DRM_IMX_TVE=y
|
+CONFIG_DRM_IMX_LDB=y
|
+CONFIG_DRM_IMX8QM_LDB=y
|
+CONFIG_DRM_IMX8QXP_LDB=y
|
+CONFIG_DRM_IMX8MP_LDB=y
|
+CONFIG_DRM_IMX93_LDB=y
|
+CONFIG_DRM_IMX_DW_MIPI_DSI=y
|
+CONFIG_DRM_IMX93_PARALLEL_DISPLAY_FORMAT=y
|
+CONFIG_DRM_IMX_HDMI=y
|
+CONFIG_DRM_IMX_SEC_DSIM=y
|
+CONFIG_DRM_IMX_DCNANO=y
|
+CONFIG_DRM_IMX_DCSS=y
|
+CONFIG_DRM_IMX_CDNS_MHDP=y
|
+CONFIG_DRM_ETNAVIV=m
|
+CONFIG_DRM_HISI_HIBMC=m
|
+CONFIG_DRM_HISI_KIRIN=m
|
+CONFIG_DRM_MXSFB=y
|
+CONFIG_DRM_PL111=m
|
+CONFIG_DRM_LIMA=m
|
+CONFIG_DRM_PANFROST=m
|
+CONFIG_FB=y
|
+CONFIG_FB_ARMCLCD=y
|
+CONFIG_FB_EFI=y
|
+CONFIG_FB_MXC_EINK_V2_PANEL=y
|
+CONFIG_BACKLIGHT_PWM=y
|
+CONFIG_BACKLIGHT_LP855X=m
|
+CONFIG_BACKLIGHT_GPIO=y
|
+CONFIG_FRAMEBUFFER_CONSOLE=y
|
+CONFIG_LOGO=y
|
+# CONFIG_LOGO_LINUX_MONO is not set
|
+# CONFIG_LOGO_LINUX_VGA16 is not set
|
+CONFIG_SOUND=y
|
+CONFIG_SND=y
|
+CONFIG_SND_ALOOP=m
|
+CONFIG_SND_USB_AUDIO=m
|
+CONFIG_SND_SOC=y
|
+CONFIG_SND_SOC_FSL_ASRC=m
|
+CONFIG_SND_SOC_FSL_MQS=m
|
+CONFIG_SND_SOC_FSL_MICFIL=m
|
+CONFIG_SND_SOC_FSL_EASRC=m
|
+CONFIG_SND_SOC_FSL_XCVR=m
|
+CONFIG_SND_SOC_FSL_ESAI_CLIENT=y
|
+CONFIG_SND_SOC_FSL_RPMSG=m
|
+CONFIG_SND_IMX_SOC=m
|
+CONFIG_SND_SOC_IMX_SGTL5000=m
|
+CONFIG_SND_SOC_IMX_SPDIF=m
|
+CONFIG_SND_SOC_FSL_ASOC_CARD=m
|
+CONFIG_SND_SOC_IMX_AUDMIX=m
|
+CONFIG_SND_SOC_IMX_HDMI=m
|
+CONFIG_SND_SOC_IMX_CARD=m
|
+CONFIG_SND_SOC_IMX_PCM512X=m
|
+CONFIG_SND_SOC_SOF_TOPLEVEL=y
|
+CONFIG_SND_SOC_SOF_OF=m
|
+CONFIG_SND_SOC_SOF_IMX_TOPLEVEL=y
|
+CONFIG_SND_SOC_SOF_IMX8=m
|
+CONFIG_SND_SOC_SOF_IMX8M=m
|
+CONFIG_SND_SOC_SOF_IMX8ULP=m
|
+CONFIG_SND_SOC_AK4613=m
|
+CONFIG_SND_SOC_BT_SCO=y
|
+CONFIG_SND_SOC_CROS_EC_CODEC=m
|
+CONFIG_SND_SOC_CS42XX8_I2C=y
|
+CONFIG_SND_SOC_DMIC=m
|
+CONFIG_SND_SOC_ES7134=m
|
+CONFIG_SND_SOC_ES7241=m
|
+CONFIG_SND_SOC_GTM601=m
|
+CONFIG_SND_SOC_MAX98357A=m
|
+CONFIG_SND_SOC_MAX98927=m
|
+CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
|
+CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
|
+CONFIG_SND_SOC_PCM3168A_I2C=m
|
+CONFIG_SND_SOC_RT5659=m
|
+CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
|
+CONFIG_SND_SOC_SIMPLE_MUX=m
|
+CONFIG_SND_SOC_SPDIF=m
|
+CONFIG_SND_SOC_TAS571X=m
|
+CONFIG_SND_SOC_WCD934X=m
|
+CONFIG_SND_SOC_WM8524=y
|
+CONFIG_SND_SOC_WM8904=m
|
+CONFIG_SND_SOC_WM8960=m
|
+CONFIG_SND_SOC_WM8962=m
|
+CONFIG_SND_SOC_WSA881X=m
|
+CONFIG_SND_SOC_RPMSG_WM8960=m
|
+CONFIG_SND_SOC_RPMSG_AK4497=m
|
+CONFIG_SND_SOC_LPASS_WSA_MACRO=m
|
+CONFIG_SND_SOC_LPASS_VA_MACRO=m
|
+CONFIG_SND_SIMPLE_CARD=y
|
+CONFIG_SND_AUDIO_GRAPH_CARD=y
|
+CONFIG_HID_A4TECH=y
|
+CONFIG_HID_APPLE=y
|
+CONFIG_HID_BELKIN=y
|
+CONFIG_HID_CHERRY=y
|
+CONFIG_HID_CHICONY=y
|
+CONFIG_HID_CYPRESS=y
|
+CONFIG_HID_EZKEY=y
|
+CONFIG_HID_ITE=y
|
+CONFIG_HID_KENSINGTON=y
|
+CONFIG_HID_LOGITECH=y
|
+CONFIG_HID_REDRAGON=y
|
+CONFIG_HID_MICROSOFT=y
|
+CONFIG_HID_MONTEREY=y
|
+CONFIG_HID_MULTITOUCH=m
|
+CONFIG_I2C_HID_ACPI=m
|
+CONFIG_I2C_HID_OF=m
|
+CONFIG_USB_CONN_GPIO=y
|
+CONFIG_USB=y
|
+CONFIG_USB_OTG=y
|
+CONFIG_USB_XHCI_HCD=y
|
+CONFIG_USB_XHCI_PCI_RENESAS=m
|
+CONFIG_USB_EHCI_HCD=y
|
+CONFIG_USB_EHCI_HCD_PLATFORM=y
|
+CONFIG_USB_OHCI_HCD=y
|
+CONFIG_USB_OHCI_HCD_PLATFORM=y
|
+CONFIG_USB_HCD_TEST_MODE=y
|
+CONFIG_USB_ACM=m
|
+CONFIG_USB_STORAGE=y
|
+CONFIG_USB_UAS=y
|
+CONFIG_USB_CDNS_SUPPORT=y
|
+CONFIG_USB_CDNS3=y
|
+CONFIG_USB_CDNS3_GADGET=y
|
+CONFIG_USB_CDNS3_HOST=y
|
+CONFIG_USB_MUSB_HDRC=y
|
+CONFIG_USB_DWC3=y
|
+CONFIG_USB_DWC2=y
|
+CONFIG_USB_CHIPIDEA=y
|
+CONFIG_USB_CHIPIDEA_UDC=y
|
+CONFIG_USB_CHIPIDEA_HOST=y
|
+CONFIG_USB_ISP1760=y
|
+CONFIG_USB_SERIAL=y
|
+CONFIG_USB_SERIAL_CONSOLE=y
|
+CONFIG_USB_SERIAL_GENERIC=y
|
+CONFIG_USB_SERIAL_SIMPLE=y
|
+CONFIG_USB_SERIAL_CP210X=m
|
+CONFIG_USB_SERIAL_FTDI_SIO=y
|
+CONFIG_USB_SERIAL_OPTION=m
|
+CONFIG_USB_TEST=m
|
+CONFIG_USB_EHSET_TEST_FIXTURE=y
|
+CONFIG_USB_HSIC_USB3503=y
|
+CONFIG_NOP_USB_XCEIV=y
|
+CONFIG_USB_MXS_PHY=y
|
+CONFIG_USB_ULPI=y
|
+CONFIG_USB_GADGET=y
|
+CONFIG_USB_SNP_UDC_PLAT=y
|
+CONFIG_USB_BDC_UDC=y
|
+CONFIG_USB_CONFIGFS=y
|
+CONFIG_USB_CONFIGFS_SERIAL=y
|
+CONFIG_USB_CONFIGFS_ACM=y
|
+CONFIG_USB_CONFIGFS_OBEX=y
|
+CONFIG_USB_CONFIGFS_NCM=y
|
+CONFIG_USB_CONFIGFS_ECM=y
|
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
|
+CONFIG_USB_CONFIGFS_RNDIS=y
|
+CONFIG_USB_CONFIGFS_EEM=y
|
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
|
+CONFIG_USB_CONFIGFS_F_LB_SS=y
|
+CONFIG_USB_CONFIGFS_F_FS=y
|
+CONFIG_USB_CONFIGFS_F_UAC1=y
|
+CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y
|
+CONFIG_USB_CONFIGFS_F_UAC2=y
|
+CONFIG_USB_CONFIGFS_F_MIDI=y
|
+CONFIG_USB_CONFIGFS_F_HID=y
|
+CONFIG_USB_CONFIGFS_F_UVC=y
|
+CONFIG_USB_ZERO=m
|
+CONFIG_USB_AUDIO=m
|
+CONFIG_USB_ETH=m
|
+CONFIG_USB_MASS_STORAGE=m
|
+CONFIG_USB_G_SERIAL=m
|
+CONFIG_TYPEC=y
|
+CONFIG_TYPEC_TCPM=y
|
+CONFIG_TYPEC_TCPCI=y
|
+CONFIG_TYPEC_FUSB302=m
|
+CONFIG_TYPEC_TPS6598X=m
|
+CONFIG_TYPEC_HD3SS3220=m
|
+CONFIG_TYPEC_SWITCH_GPIO=y
|
+CONFIG_MMC=y
|
+CONFIG_MMC_BLOCK_MINORS=32
|
+CONFIG_MMC_ARMMMCI=y
|
+CONFIG_MMC_SDHCI=y
|
+CONFIG_MMC_SDHCI_ACPI=y
|
+CONFIG_MMC_SDHCI_PLTFM=y
|
+CONFIG_MMC_SDHCI_OF_ARASAN=y
|
+CONFIG_MMC_SDHCI_OF_ESDHC=y
|
+CONFIG_MMC_SDHCI_CADENCE=y
|
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
|
+CONFIG_MMC_SDHCI_F_SDH30=y
|
+CONFIG_MMC_SPI=y
|
+CONFIG_MMC_DW=y
|
+CONFIG_MMC_DW_EXYNOS=y
|
+CONFIG_MMC_DW_HI3798CV200=y
|
+CONFIG_MMC_DW_K3=y
|
+CONFIG_MMC_MTK=y
|
+CONFIG_MMC_SDHCI_XENON=y
|
+CONFIG_MMC_SDHCI_AM654=y
|
+CONFIG_SCSI_UFSHCD=y
|
+CONFIG_SCSI_UFSHCD_PLATFORM=y
|
+CONFIG_NEW_LEDS=y
|
+CONFIG_LEDS_CLASS=y
|
+CONFIG_LEDS_CLASS_MULTICOLOR=m
|
+CONFIG_LEDS_LM3692X=m
|
+CONFIG_LEDS_PCA9532=m
|
+CONFIG_LEDS_GPIO=y
|
+CONFIG_LEDS_PCA995X=m
|
+CONFIG_LEDS_PWM=y
|
+CONFIG_LEDS_SYSCON=y
|
+CONFIG_LEDS_TRIGGER_TIMER=y
|
+CONFIG_LEDS_TRIGGER_DISK=y
|
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
+CONFIG_LEDS_TRIGGER_CPU=y
|
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
|
+CONFIG_LEDS_TRIGGER_PANIC=y
|
+CONFIG_EDAC=y
|
+CONFIG_EDAC_GHES=y
|
+CONFIG_EDAC_LAYERSCAPE=m
|
+CONFIG_EDAC_SYNOPSYS=y
|
+CONFIG_RTC_CLASS=y
|
+CONFIG_RTC_DRV_ISL1208=y
|
+CONFIG_DMADEVICES=y
|
+CONFIG_FSL_EDMA=y
|
+CONFIG_FSL_QDMA=m
|
+CONFIG_FSL_EDMA_V3=y
|
+CONFIG_IMX_SDMA=y
|
+CONFIG_MV_XOR_V2=y
|
+CONFIG_MXS_DMA=y
|
+CONFIG_MXC_PXP_V3=y
|
+CONFIG_PL330_DMA=y
|
+CONFIG_QCOM_HIDMA_MGMT=y
|
+CONFIG_QCOM_HIDMA=y
|
+CONFIG_DW_EDMA=y
|
+CONFIG_DW_EDMA_PCIE=y
|
+CONFIG_FSL_DPAA2_QDMA=m
|
+CONFIG_DMATEST=y
|
+CONFIG_DMABUF_HEAPS=y
|
+CONFIG_DMABUF_HEAPS_SYSTEM=y
|
+CONFIG_DMABUF_HEAPS_CMA=y
|
+CONFIG_DMABUF_HEAPS_DSP=y
|
+CONFIG_UIO_PCI_GENERIC=y
|
+CONFIG_UIO_IVSHMEM=y
|
+CONFIG_VFIO=y
|
+CONFIG_VFIO_PCI=y
|
+CONFIG_VFIO_FSL_MC=y
|
+CONFIG_VIRTIO_PCI=y
|
+CONFIG_VIRTIO_BALLOON=y
|
+CONFIG_VIRTIO_MMIO=y
|
+CONFIG_VIRTIO_IVSHMEM=y
|
+CONFIG_XEN_GNTDEV=y
|
+CONFIG_XEN_GRANT_DEV_ALLOC=y
|
+CONFIG_STAGING=y
|
+CONFIG_STAGING_MEDIA=y
|
+CONFIG_VIDEO_IMX_CAPTURE=y
|
+CONFIG_IMX8_MEDIA_DEVICE=m
|
+CONFIG_MHDP_HDMIRX=y
|
+CONFIG_MHDP_HDMIRX_CEC=y
|
+CONFIG_FSL_DPAA2=y
|
+CONFIG_FSL_PPFE=y
|
+CONFIG_FSL_PPFE_UTIL_DISABLED=y
|
+CONFIG_ETHOSU=y
|
+CONFIG_CHROME_PLATFORMS=y
|
+CONFIG_CROS_EC=y
|
+CONFIG_CROS_EC_I2C=y
|
+CONFIG_CROS_EC_SPI=y
|
+CONFIG_CROS_EC_CHARDEV=m
|
+CONFIG_CLK_VEXPRESS_OSC=y
|
+CONFIG_COMMON_CLK_RK808=y
|
+CONFIG_COMMON_CLK_SCMI=y
|
+CONFIG_COMMON_CLK_SCPI=y
|
+CONFIG_COMMON_CLK_CS2000_CP=y
|
+CONFIG_COMMON_CLK_FSL_SAI=y
|
+CONFIG_COMMON_CLK_S2MPS11=y
|
+CONFIG_COMMON_CLK_XGENE=y
|
+CONFIG_COMMON_CLK_PWM=y
|
+CONFIG_COMMON_CLK_VC5=y
|
+CONFIG_CLK_IMX8MM=y
|
+CONFIG_CLK_IMX8MN=y
|
+CONFIG_CLK_IMX8MP=y
|
+CONFIG_CLK_IMX8MQ=y
|
+CONFIG_CLK_IMX8QXP=y
|
+CONFIG_CLK_IMX8ULP=y
|
+CONFIG_CLK_IMX93=y
|
+CONFIG_HWSPINLOCK=y
|
+CONFIG_ARM_MHU=y
|
+CONFIG_IMX_MBOX=y
|
+CONFIG_PLATFORM_MHU=y
|
+CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
|
+CONFIG_ARM_SMMU=y
|
+CONFIG_ARM_SMMU_V3=y
|
+CONFIG_REMOTEPROC=y
|
+CONFIG_IMX_REMOTEPROC=y
|
+CONFIG_IMX_DSP_REMOTEPROC=m
|
+CONFIG_RPMSG_CHAR=m
|
+CONFIG_RPMSG_CTRL=m
|
+CONFIG_RPMSG_QCOM_GLINK_RPM=y
|
+CONFIG_SOUNDWIRE=m
|
+CONFIG_SOUNDWIRE_QCOM=m
|
+CONFIG_SOC_BRCMSTB=y
|
+CONFIG_FSL_DPAA=y
|
+CONFIG_FSL_MC_DPIO=y
|
+CONFIG_FSL_RCPM=y
|
+CONFIG_FSL_QIXIS=y
|
+CONFIG_SOC_TI=y
|
+CONFIG_EXTCON_PTN5150=m
|
+CONFIG_EXTCON_USB_GPIO=y
|
+CONFIG_EXTCON_USBC_CROS_EC=y
|
+CONFIG_IIO=y
|
+CONFIG_FXLS8962AF_I2C=m
|
+CONFIG_IIO_ST_ACCEL_3AXIS=m
|
+CONFIG_IMX8QXP_ADC=y
|
+CONFIG_IMX93_ADC=y
|
+CONFIG_MS1112=y
|
+CONFIG_BMG160=m
|
+CONFIG_IIO_ST_GYRO_3AXIS=m
|
+CONFIG_MAX30100=m
|
+CONFIG_MAX30102=m
|
+CONFIG_DHT11=y
|
+CONFIG_HDC100X=y
|
+CONFIG_HTS221=y
|
+CONFIG_FXOS8700_I2C=y
|
+CONFIG_RPMSG_IIO_PEDOMETER=m
|
+CONFIG_INV_MPU6050_I2C=m
|
+CONFIG_IIO_ST_LSM6DSX=y
|
+CONFIG_SENSORS_ISL29018=y
|
+CONFIG_IIO_ST_MAGN_3AXIS=m
|
+CONFIG_MPL3115=y
|
+CONFIG_MS5611=m
|
+CONFIG_MS5611_I2C=m
|
+CONFIG_PWM=y
|
+CONFIG_PWM_ADP5585=y
|
+CONFIG_PWM_CROS_EC=m
|
+CONFIG_PWM_FSL_FTM=m
|
+CONFIG_PWM_IMX27=y
|
+CONFIG_PWM_RPCHIP=y
|
+CONFIG_PWM_SL28CPLD=m
|
+CONFIG_SL28CPLD_INTC=y
|
+CONFIG_RESET_IMX7=y
|
+CONFIG_RESET_IMX8ULP_SIM=y
|
+CONFIG_PHY_XGENE=y
|
+CONFIG_PHY_MIXEL_LVDS=y
|
+CONFIG_PHY_MIXEL_LVDS_COMBO=y
|
+CONFIG_PHY_CADENCE_SALVO=y
|
+CONFIG_PHY_FSL_IMX8MP_LVDS=y
|
+CONFIG_PHY_FSL_IMX93_MIPI_DPHY=y
|
+CONFIG_PHY_MIXEL_MIPI_DPHY=y
|
+CONFIG_PHY_FSL_IMX8M_PCIE=y
|
+CONFIG_PHY_FSL_IMX8Q_PCIE=y
|
+CONFIG_PHY_SAMSUNG_HDMI_PHY=y
|
+CONFIG_PHY_QCOM_USB_HS=y
|
+CONFIG_PHY_SAMSUNG_USB2=y
|
+CONFIG_ARM_CCI_PMU=m
|
+CONFIG_ARM_CCN=m
|
+CONFIG_ARM_CMN=m
|
+CONFIG_ARM_SMMU_V3_PMU=m
|
+CONFIG_ARM_DSU_PMU=m
|
+CONFIG_FSL_IMX8_DDR_PMU=y
|
+CONFIG_FSL_IMX9_DDR_PMU=y
|
+CONFIG_ARM_SPE_PMU=m
|
+CONFIG_ARM_DMC620_PMU=m
|
+CONFIG_HISI_PMU=y
|
+CONFIG_NVMEM_IMX_OCOTP=y
|
+CONFIG_NVMEM_IMX_OCOTP_SCU=y
|
+CONFIG_NVMEM_RMEM=m
|
+CONFIG_FPGA=y
|
+CONFIG_FPGA_BRIDGE=m
|
+CONFIG_ALTERA_FREEZE_BRIDGE=m
|
+CONFIG_FPGA_REGION=m
|
+CONFIG_OF_FPGA_REGION=m
|
+CONFIG_TEE=y
|
+CONFIG_OPTEE=y
|
+CONFIG_MUX_MMIO=y
|
+CONFIG_SLIM_QCOM_CTRL=m
|
+CONFIG_MXC_SIM=y
|
+CONFIG_MXC_GPU_VIV=y
|
+CONFIG_MXC_EMVSIM=y
|
+CONFIG_EXT2_FS=y
|
+CONFIG_EXT3_FS=y
|
+CONFIG_EXT4_FS_POSIX_ACL=y
|
+CONFIG_FANOTIFY=y
|
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
|
+CONFIG_QUOTA=y
|
+CONFIG_AUTOFS4_FS=y
|
+CONFIG_FUSE_FS=m
|
+CONFIG_CUSE=m
|
+CONFIG_OVERLAY_FS=m
|
+CONFIG_VFAT_FS=y
|
+CONFIG_EXFAT_FS=y
|
+CONFIG_NTFS_FS=y
|
+CONFIG_NTFS_RW=y
|
+CONFIG_NTFS3_FS=y
|
+CONFIG_NTFS3_64BIT_CLUSTER=y
|
+CONFIG_NTFS3_LZX_XPRESS=y
|
+CONFIG_NTFS3_FS_POSIX_ACL=y
|
+CONFIG_TMPFS_POSIX_ACL=y
|
+CONFIG_HUGETLBFS=y
|
+CONFIG_EFIVAR_FS=y
|
+CONFIG_JFFS2_FS=y
|
+CONFIG_NFS_FS=y
|
+CONFIG_NFS_V4=y
|
+CONFIG_NFS_V4_1=y
|
+CONFIG_NFS_V4_2=y
|
+CONFIG_ROOT_NFS=y
|
+CONFIG_NLS_CODEPAGE_437=y
|
+CONFIG_NLS_CODEPAGE_936=y
|
+CONFIG_NLS_CODEPAGE_950=y
|
+CONFIG_NLS_CODEPAGE_874=y
|
+CONFIG_NLS_ISO8859_1=y
|
+CONFIG_NLS_UTF8=y
|
+CONFIG_TRUSTED_KEYS=m
|
+# CONFIG_TRUSTED_KEYS_TPM is not set
|
+# CONFIG_TRUSTED_KEYS_TEE is not set
|
+CONFIG_SECURITY=y
|
+CONFIG_CRYPTO_USER=y
|
+CONFIG_CRYPTO_TEST=m
|
+CONFIG_CRYPTO_ANUBIS=m
|
+CONFIG_CRYPTO_ARIA=m
|
+CONFIG_CRYPTO_BLOWFISH=m
|
+CONFIG_CRYPTO_CAMELLIA=m
|
+CONFIG_CRYPTO_CAST5=m
|
+CONFIG_CRYPTO_CAST6=m
|
+CONFIG_CRYPTO_FCRYPT=m
|
+CONFIG_CRYPTO_KHAZAD=m
|
+CONFIG_CRYPTO_SEED=m
|
+CONFIG_CRYPTO_SERPENT=m
|
+CONFIG_CRYPTO_TEA=m
|
+CONFIG_CRYPTO_TWOFISH=m
|
+CONFIG_CRYPTO_ARC4=m
|
+CONFIG_CRYPTO_CFB=m
|
+CONFIG_CRYPTO_CTS=m
|
+CONFIG_CRYPTO_LRW=m
|
+CONFIG_CRYPTO_OFB=m
|
+CONFIG_CRYPTO_PCBC=m
|
+CONFIG_CRYPTO_CHACHA20POLY1305=m
|
+CONFIG_CRYPTO_ECHAINIV=y
|
+CONFIG_CRYPTO_TLS=m
|
+CONFIG_CRYPTO_BLAKE2B=m
|
+CONFIG_CRYPTO_MD4=m
|
+CONFIG_CRYPTO_RMD160=m
|
+CONFIG_CRYPTO_STREEBOG=m
|
+CONFIG_CRYPTO_VMAC=m
|
+CONFIG_CRYPTO_WP512=m
|
+CONFIG_CRYPTO_XCBC=m
|
+CONFIG_CRYPTO_XXHASH=m
|
+CONFIG_CRYPTO_LZO=y
|
+CONFIG_CRYPTO_ZSTD=y
|
+CONFIG_CRYPTO_ANSI_CPRNG=y
|
+CONFIG_CRYPTO_USER_API_HASH=m
|
+CONFIG_CRYPTO_USER_API_SKCIPHER=m
|
+CONFIG_CRYPTO_USER_API_RNG=m
|
+CONFIG_CRYPTO_USER_API_AEAD=m
|
+CONFIG_CRYPTO_CHACHA20_NEON=m
|
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
|
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
|
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
|
+CONFIG_CRYPTO_SHA512_ARM64_CE=m
|
+CONFIG_CRYPTO_SHA3_ARM64=m
|
+CONFIG_CRYPTO_SM3_ARM64_CE=m
|
+CONFIG_CRYPTO_POLYVAL_ARM64_CE=m
|
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
|
+CONFIG_CRYPTO_AES_ARM64_BS=m
|
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
|
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
|
+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=m
|
+CONFIG_CRYPTO_DEV_FSL_CAAM=m
|
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m
|
+CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m
|
+CONFIG_CRYPTO_DEV_CCREE=m
|
+CONFIG_CRYPTO_DEV_HISI_SEC2=m
|
+CONFIG_CRYPTO_DEV_HISI_ZIP=m
|
+CONFIG_CRYPTO_DEV_HISI_HPRE=m
|
+CONFIG_CRYPTO_DEV_HISI_TRNG=m
|
+CONFIG_CRYPTO_DEV_AMLOGIC_GXL=m
|
+CONFIG_INDIRECT_PIO=y
|
+CONFIG_CRC_CCITT=m
|
+CONFIG_CRC8=y
|
+CONFIG_CMA_SIZE_MBYTES=32
|
+CONFIG_PRINTK_TIME=y
|
+CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
|
+CONFIG_DEBUG_INFO_REDUCED=y
|
+CONFIG_MAGIC_SYSRQ=y
|
+CONFIG_DEBUG_FS=y
|
+# CONFIG_SCHED_DEBUG is not set
|
+# CONFIG_DEBUG_PREEMPT is not set
|
+# CONFIG_FTRACE is not set
|
+CONFIG_CORESIGHT=y
|
+CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
|
+CONFIG_CORESIGHT_CATU=m
|
+CONFIG_CORESIGHT_SINK_TPIU=m
|
+CONFIG_CORESIGHT_SINK_ETBV10=m
|
+CONFIG_CORESIGHT_SOURCE_ETM4X=y
|
+CONFIG_CORESIGHT_STM=m
|
+CONFIG_CORESIGHT_CPU_DEBUG=m
|
+CONFIG_CORESIGHT_CTI=m
|
+CONFIG_MEMTEST=y
|
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
|
index 3946eb595..15278c13c 100644
|
--- a/drivers/iio/adc/Kconfig
|
+++ b/drivers/iio/adc/Kconfig
|
@@ -1164,6 +1164,18 @@ config TI_ADC161S626
|
This driver can also be built as a module. If so, the module will be
|
called ti-adc161s626.
|
|
+config MS1112
|
+ tristate "Ruimeng Technology MS1112 ADC"
|
+ depends on I2C
|
+ select IIO_BUFFER
|
+ select IIO_TRIGGERED_BUFFER
|
+ help
|
+ If you say yes here you get support for Ruimeng Technology ADS1015
|
+ ADC chip.
|
+
|
+ This driver can also be built as a module. If so, the module will be
|
+ called ms1112.
|
+
|
config TI_ADS1015
|
tristate "Texas Instruments ADS1015 ADC"
|
depends on I2C
|
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
|
index 83233c38c..f403164cf 100644
|
--- a/drivers/iio/adc/Makefile
|
+++ b/drivers/iio/adc/Makefile
|
@@ -104,6 +104,7 @@ obj-$(CONFIG_TI_ADC12138) += ti-adc12138.o
|
obj-$(CONFIG_TI_ADC108S102) += ti-adc108s102.o
|
obj-$(CONFIG_TI_ADC128S052) += ti-adc128s052.o
|
obj-$(CONFIG_TI_ADC161S626) += ti-adc161s626.o
|
+obj-$(CONFIG_MS1112) += ms1112.o
|
obj-$(CONFIG_TI_ADS1015) += ti-ads1015.o
|
obj-$(CONFIG_TI_ADS7950) += ti-ads7950.o
|
obj-$(CONFIG_TI_ADS8344) += ti-ads8344.o
|
diff --git a/drivers/iio/adc/ms1112.c b/drivers/iio/adc/ms1112.c
|
new file mode 100644
|
index 000000000..cf8ea5c66
|
--- /dev/null
|
+++ b/drivers/iio/adc/ms1112.c
|
@@ -0,0 +1,569 @@
|
+// SPDX-License-Identifier: GPL-2.0-only
|
+/*
|
+ * MS1112 - Ruimeng Technology Analog-to-Digital Converter
|
+ *
|
+ * Copyright (c) 2024, LingYun IoT System Studio.
|
+ *
|
+ * IIO driver for MS1112 ADC 7-bit I2C slave address: 0x4A
|
+ */
|
+
|
+#include <linux/init.h>
|
+#include <linux/module.h>
|
+#include <linux/errno.h>
|
+#include <linux/gpio.h>
|
+#include <linux/cdev.h>
|
+#include <linux/device.h>
|
+#include <linux/of_gpio.h>
|
+#include <linux/semaphore.h>
|
+#include <linux/timer.h>
|
+#include <linux/i2c.h>
|
+#include <asm/uaccess.h>
|
+#include <asm/io.h>
|
+#include <linux/iio/iio.h>
|
+#include <linux/iio/driver.h>
|
+
|
+#define MS1112_DRV_NAME "ms1112"
|
+
|
+#define MS1112_CONV_REG 0x00
|
+#define MS1112_CFG_REG 0x01
|
+#define MS1112_DEFAULT_CONFIG 0xFC
|
+
|
+#define MS1112_CHANNELS 4
|
+#define MS1112_CFG_DR_SHIFT 2
|
+#define MS1112_CFG_MOD_SHIFT 4
|
+#define MS1112_CFG_PGA_SHIFT 0
|
+#define MS1112_CFG_MUX_SHIFT 5
|
+
|
+#define MS1112_CFG_DR_MASK GENMASK(3, 2)
|
+#define MS1112_CFG_MOD_MASK BIT(4)
|
+#define MS1112_CFG_PGA_MASK GENMASK(1, 0)
|
+#define MS1112_CFG_MUX_MASK GENMASK(6, 5)
|
+
|
+#define MS1112_DEFAULT_PGA 0
|
+#define MS1112_DEFAULT_DATA_RATE 3
|
+#define MS1112_DEFAULT_CHAN 2
|
+#define MS1112_DEFAULT_MODE 1
|
+
|
+#define MS1112_CONTINUOUS 0
|
+#define MS1112_SINGLESHOT 1
|
+
|
+struct ms1112_chip_data {
|
+ struct iio_chan_spec const *channels;
|
+ int num_channels;
|
+ const struct iio_info *info;
|
+ const int *data_rate;
|
+ const int data_rate_len;
|
+ const int *scale;
|
+ const int scale_len;
|
+ bool has_comparator;
|
+};
|
+
|
+enum ms1112_channels {
|
+ MS1112_AIN0_AIN1 = 0,
|
+ MS1112_AIN2,
|
+ MS1112_AIN0,
|
+ MS1112_AIN1,
|
+ MS1112_TIMESTAMP,
|
+};
|
+
|
+static const int ms1112_data_rate[] = {
|
+ 240,60,30,15
|
+};
|
+
|
+static const int ms1112_fullscale_range[] = {
|
+ 2048
|
+};
|
+
|
+static const int ms1112_scale[] = { /* 12bit ADC */
|
+ 2048,11,
|
+ 2048,13,
|
+ 2048,14,
|
+ 2048,15
|
+};
|
+
|
+#define FIT_CHECK(_testbits, _fitbits) \
|
+ ( \
|
+ (_fitbits) * \
|
+ !!sizeof(struct { \
|
+ static_assert((_testbits) <= (_fitbits)); \
|
+ int pad; \
|
+ }) \
|
+ )
|
+
|
+#define MS1112_V_CHAN(_chan, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \
|
+ .type = IIO_VOLTAGE, \
|
+ .indexed = 1, \
|
+ .address = _addr, \
|
+ .channel = _chan, \
|
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
|
+ BIT(IIO_CHAN_INFO_SCALE) | \
|
+ BIT(IIO_CHAN_INFO_SAMP_FREQ), \
|
+ .info_mask_shared_by_all_available = \
|
+ BIT(IIO_CHAN_INFO_SCALE) | \
|
+ BIT(IIO_CHAN_INFO_SAMP_FREQ), \
|
+ .scan_index = _addr, \
|
+ .scan_type = { \
|
+ .sign = 's', \
|
+ .realbits = (_realbits), \
|
+ .storagebits = FIT_CHECK((_realbits) + (_shift), 16), \
|
+ .shift = (_shift), \
|
+ .endianness = IIO_CPU, \
|
+ }, \
|
+ .event_spec = (_event_spec), \
|
+ .num_event_specs = (_num_event_specs), \
|
+ .datasheet_name = "AIN"#_chan, \
|
+}
|
+
|
+#define MS1112_V_DIFF_CHAN(_chan, _chan2, _addr, _realbits, _shift, _event_spec, _num_event_specs) { \
|
+ .type = IIO_VOLTAGE, \
|
+ .differential = 1, \
|
+ .indexed = 1, \
|
+ .address = _addr, \
|
+ .channel = _chan, \
|
+ .channel2 = _chan2, \
|
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
|
+ BIT(IIO_CHAN_INFO_SCALE) | \
|
+ BIT(IIO_CHAN_INFO_SAMP_FREQ), \
|
+ .info_mask_shared_by_all_available = \
|
+ BIT(IIO_CHAN_INFO_SCALE) | \
|
+ BIT(IIO_CHAN_INFO_SAMP_FREQ), \
|
+ .scan_index = _addr, \
|
+ .scan_type = { \
|
+ .sign = 's', \
|
+ .realbits = (_realbits), \
|
+ .storagebits = FIT_CHECK((_realbits) + (_shift), 16), \
|
+ .shift = (_shift), \
|
+ .endianness = IIO_CPU, \
|
+ }, \
|
+ .event_spec = (_event_spec), \
|
+ .num_event_specs = (_num_event_specs), \
|
+ .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
|
+}
|
+
|
+struct ms1112_channel_data {
|
+ bool enabled;
|
+ unsigned int pga;
|
+ unsigned int data_rate;
|
+ unsigned int mode;
|
+};
|
+
|
+struct ms1112_thresh_data {
|
+ int high_thresh;
|
+ int low_thresh;
|
+};
|
+
|
+struct ms1112_data {
|
+ struct ms1112_channel_data channel_data[MS1112_CHANNELS];
|
+ struct ms1112_thresh_data thresh_data[MS1112_CHANNELS];
|
+ const struct ms1112_chip_data *chip;
|
+ struct mutex lock;
|
+ void *private_data;
|
+ struct i2c_client *client;
|
+};
|
+
|
+/* MS1112 don't use the register address */
|
+static int ms1112_read_regs(struct ms1112_data *dev, uint8_t reg, void *buf, uint8_t size)
|
+{
|
+ int ret = 0;
|
+ struct i2c_msg msg[1];
|
+ struct i2c_client *client = dev->client;
|
+
|
+ msg[0].addr = client->addr;
|
+ msg[0].flags = I2C_M_RD;
|
+ msg[0].buf = buf;
|
+ msg[0].len = size;
|
+
|
+ ret = i2c_transfer(client->adapter, msg, 1);
|
+ if(ret != 1) {
|
+ dev_err(&dev->client->dev, "%s() i2c_transfer error, ret=%d\n", __func__, ret);
|
+ ret = -EREMOTEIO;
|
+ }
|
+
|
+ return ret;
|
+}
|
+
|
+/* MS1112 don't use the register address */
|
+static s32 ms1112_write_regs(struct ms1112_data *dev, uint8_t reg, uint8_t *data, uint8_t bytes)
|
+{
|
+ int ret = 0;
|
+ struct i2c_msg msg;
|
+ struct i2c_client *client = dev->client;
|
+
|
+ msg.addr = client->addr;
|
+ msg.flags = 0;
|
+ msg.buf = data;
|
+ msg.len = bytes;
|
+
|
+ ret = i2c_transfer(client->adapter, &msg, 1);
|
+ if(ret != 1) {
|
+ dev_err(&dev->client->dev, "%s() i2c_transfer error, ret=%d\n", __func__, ret);
|
+ ret = -EREMOTEIO;
|
+ }
|
+
|
+ return ret;
|
+}
|
+
|
+static int ms1112_readdata(struct ms1112_data *dev,unsigned int *val)
|
+{
|
+ unsigned char buf[3];
|
+ unsigned char rx_data[3];
|
+ int rv = 0;
|
+
|
+ rv = ms1112_read_regs(dev, MS1112_CONV_REG, rx_data, 3);
|
+ if(rv<0) {
|
+ return rv;
|
+ }
|
+
|
+ buf[0] = rx_data[0];
|
+ buf[1] = rx_data[1];
|
+ buf[2] = rx_data[2];
|
+
|
+ *val = (buf[0]<<8) | buf[1];
|
+ return rv;
|
+}
|
+
|
+static int ms1112_get_adc_result(struct ms1112_data *data, int chan, int *val)
|
+{
|
+ int ret = 0;
|
+ int pga, dr , mode;
|
+ uint8_t mask, cfg;
|
+
|
+ if (chan < 0 || chan >= MS1112_CHANNELS)
|
+ return -EINVAL;
|
+
|
+ mode = data->channel_data[chan].mode;
|
+ pga = data->channel_data[chan].pga;
|
+ dr = data->channel_data[chan].data_rate;
|
+
|
+ mask = MS1112_CFG_MUX_MASK | MS1112_CFG_PGA_MASK |
|
+ MS1112_CFG_DR_MASK | MS1112_CFG_MOD_MASK | MS1112_SINGLESHOT << 7;
|
+
|
+ cfg = chan << MS1112_CFG_MUX_SHIFT | pga << MS1112_CFG_PGA_SHIFT |
|
+ dr << MS1112_CFG_DR_SHIFT | mode << MS1112_CFG_MOD_SHIFT | MS1112_SINGLESHOT << 7;
|
+
|
+ cfg = (cfg & mask);
|
+
|
+ ms1112_write_regs(data, MS1112_CFG_REG, &cfg, 1);
|
+
|
+ ret = ms1112_readdata(data,val);
|
+ return ret;
|
+}
|
+
|
+static int ms1112_set_scale(struct ms1112_data *data, struct iio_chan_spec const *chan,
|
+ int scale, int uscale)
|
+{
|
+ int i;
|
+ int fullscale = div_s64((scale * 1000000LL + uscale) <<
|
+ (chan->scan_type.realbits - 1), 1000000);
|
+
|
+ for (i = 0; i < ARRAY_SIZE(ms1112_fullscale_range); i++) {
|
+ if (ms1112_fullscale_range[i] == fullscale) {
|
+ data->channel_data[chan->address].pga = i;
|
+ return 0;
|
+ }
|
+ }
|
+
|
+ return -EINVAL;
|
+}
|
+
|
+static int ms1112_set_data_rate(struct ms1112_data *data, int chan, int rate)
|
+{
|
+ int i;
|
+
|
+ for (i = 0; i < data->chip->data_rate_len; i++) {
|
+ if (data->chip->data_rate[i] == rate) {
|
+ data->channel_data[chan].data_rate = i;
|
+ return 0;
|
+ }
|
+ }
|
+
|
+ return -EINVAL;
|
+}
|
+
|
+static int ms1112_read_avail(struct iio_dev *indio_dev,
|
+ struct iio_chan_spec const *chan,
|
+ const int **vals, int *type, int *length,
|
+ long mask)
|
+{
|
+ struct ms1112_data *data = iio_priv(indio_dev);
|
+
|
+ if (chan->type != IIO_VOLTAGE)
|
+ return -EINVAL;
|
+
|
+ switch (mask) {
|
+ case IIO_CHAN_INFO_SCALE:
|
+ *type = IIO_VAL_FRACTIONAL_LOG2;
|
+ *vals = data->chip->scale;
|
+ *length = data->chip->scale_len;
|
+ return IIO_AVAIL_LIST;
|
+ case IIO_CHAN_INFO_SAMP_FREQ:
|
+ *type = IIO_VAL_INT;
|
+ *vals = data->chip->data_rate;
|
+ *length = data->chip->data_rate_len;
|
+ return IIO_AVAIL_LIST;
|
+ default:
|
+ return -EINVAL;
|
+ }
|
+}
|
+
|
+static int ms1112_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask)
|
+{
|
+ int ret, idx;
|
+ struct ms1112_data *data = iio_priv(indio_dev);
|
+
|
+ mutex_lock(&data->lock);
|
+ switch (mask) {
|
+ case IIO_CHAN_INFO_RAW:
|
+
|
+ ret = iio_device_claim_direct_mode(indio_dev);
|
+ if (ret)
|
+ break;
|
+
|
+ ret = ms1112_get_adc_result(data, chan->address, val);
|
+ if (ret < 0) {
|
+ goto release_direct;
|
+ }
|
+
|
+ *val = sign_extend32(*val >> chan->scan_type.shift,
|
+ chan->scan_type.realbits - 1);
|
+
|
+ ret = IIO_VAL_INT;
|
+release_direct:
|
+ iio_device_release_direct_mode(indio_dev);
|
+ break;
|
+
|
+ case IIO_CHAN_INFO_SCALE:
|
+ idx = data->channel_data[chan->address].pga;
|
+ *val = ms1112_fullscale_range[idx];
|
+ *val2 = chan->scan_type.realbits - 1;
|
+ ret = IIO_VAL_FRACTIONAL_LOG2;
|
+ break;
|
+ case IIO_CHAN_INFO_SAMP_FREQ:
|
+ idx = data->channel_data[chan->address].data_rate;
|
+ *val = data->chip->data_rate[idx];
|
+ ret = IIO_VAL_INT;
|
+ break;
|
+ default:
|
+ ret = -EINVAL;
|
+ break;
|
+ }
|
+ mutex_unlock(&data->lock);
|
+
|
+ return ret;
|
+}
|
+
|
+static int ms1112_write_raw(struct iio_dev *indio_dev,
|
+ struct iio_chan_spec const *chan, int val,
|
+ int val2, long mask)
|
+{
|
+ struct ms1112_data *data = iio_priv(indio_dev);
|
+ int ret;
|
+
|
+ mutex_lock(&data->lock);
|
+ switch (mask) {
|
+ case IIO_CHAN_INFO_SCALE:
|
+ ret = ms1112_set_scale(data, chan, val, val2);
|
+ break;
|
+ case IIO_CHAN_INFO_SAMP_FREQ:
|
+ ret = ms1112_set_data_rate(data, chan->address, val);
|
+ break;
|
+ default:
|
+ ret = -EINVAL;
|
+ break;
|
+ }
|
+ mutex_unlock(&data->lock);
|
+
|
+ return ret;
|
+}
|
+
|
+static const struct iio_info ms1112_info = {
|
+ .read_raw = ms1112_read_raw,
|
+ .write_raw = ms1112_write_raw,
|
+ .read_avail = ms1112_read_avail,
|
+};
|
+
|
+
|
+static const struct iio_chan_spec ms1112_channels[] = {
|
+ MS1112_V_DIFF_CHAN(0, 1, MS1112_AIN0_AIN1, 16, 0, NULL, 0),
|
+ MS1112_V_CHAN(2, MS1112_AIN2, 16, 0, NULL, 0),
|
+ MS1112_V_CHAN(0, MS1112_AIN0, 16, 0, NULL, 0),
|
+ MS1112_V_CHAN(1, MS1112_AIN1, 16, 0, NULL, 0),
|
+ IIO_CHAN_SOFT_TIMESTAMP(MS1112_TIMESTAMP),
|
+};
|
+
|
+static int ms1112_client_get_channels_config(struct i2c_client *client)
|
+{
|
+ struct iio_dev *indio_dev = i2c_get_clientdata(client);
|
+ struct ms1112_data *data = iio_priv(indio_dev);
|
+ struct device *dev = &client->dev;
|
+ struct fwnode_handle *node;
|
+ int i = -1;
|
+
|
+ device_for_each_child_node(dev, node) {
|
+ u32 pval;
|
+ unsigned int channel;
|
+ unsigned int pga = MS1112_DEFAULT_PGA;
|
+ unsigned int data_rate = MS1112_DEFAULT_DATA_RATE;
|
+ unsigned int mode = MS1112_DEFAULT_MODE;
|
+
|
+ if (fwnode_property_read_u32(node, "reg", &pval)) {
|
+ dev_err(dev, "invalid reg on %pfw\n", node);
|
+ continue;
|
+ }
|
+
|
+ channel = pval;
|
+ if (channel >= MS1112_CHANNELS) {
|
+ dev_err(dev, "invalid channel index %d on %pfw\n",
|
+ channel, node);
|
+ continue;
|
+ }
|
+
|
+ if (!fwnode_property_read_u32(node, "ti,gain", &pval)) {
|
+ pga = pval;
|
+ if (pga > 3 ) {
|
+ dev_err(dev, "invalid gain on %pfw\n", node);
|
+ fwnode_handle_put(node);
|
+ return -EINVAL;
|
+ }
|
+ }
|
+
|
+ if (!fwnode_property_read_u32(node, "ti,datarate", &pval)) {
|
+ data_rate = pval;
|
+ if (data_rate > 3) {
|
+ dev_err(dev, "invalid data_rate on %pfw\n", node);
|
+ fwnode_handle_put(node);
|
+ return -EINVAL;
|
+ }
|
+ }
|
+
|
+ if (!fwnode_property_read_u32(node, "ti,mode", &pval)) {
|
+ mode = pval;
|
+ if (mode > 1) {
|
+ dev_err(dev, "invalid mode on %pfw\n", node);
|
+ fwnode_handle_put(node);
|
+ return -EINVAL;
|
+ }
|
+ }
|
+
|
+
|
+ data->channel_data[channel].pga = pga;
|
+ data->channel_data[channel].data_rate = data_rate;
|
+ data->channel_data[channel].mode = mode;
|
+ i++;
|
+ }
|
+
|
+ return i < 0 ? -EINVAL : 0;
|
+}
|
+
|
+static void ms1112_get_channels_config(struct i2c_client *client)
|
+{
|
+ unsigned int k;
|
+
|
+ struct iio_dev *indio_dev = i2c_get_clientdata(client);
|
+ struct ms1112_data *data = iio_priv(indio_dev);
|
+
|
+ if (!ms1112_client_get_channels_config(client))
|
+ return;
|
+
|
+ /* fallback on default configuration */
|
+ for (k = 0; k < MS1112_CHANNELS; ++k) {
|
+ data->channel_data[k].pga = MS1112_DEFAULT_PGA;
|
+ data->channel_data[k].data_rate = MS1112_DEFAULT_DATA_RATE;
|
+ data->channel_data[k].mode = MS1112_DEFAULT_MODE;
|
+ }
|
+}
|
+
|
+static int ms1112_probe(struct i2c_client *client,const struct i2c_device_id *id)
|
+{
|
+ struct iio_dev *indio_dev;
|
+ const struct ms1112_chip_data *chip;
|
+ struct ms1112_data *data;
|
+ int ret;
|
+ int i;
|
+
|
+ chip = device_get_match_data(&client->dev);
|
+ if (!chip)
|
+ chip = (const struct ms1112_chip_data *)id->driver_data;
|
+ if (!chip)
|
+ return dev_err_probe(&client->dev, -EINVAL, "Unknown chip\n");
|
+
|
+ indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*indio_dev));
|
+ if (!indio_dev)
|
+ return -ENOMEM;
|
+
|
+ data = iio_priv(indio_dev);
|
+ i2c_set_clientdata(client, indio_dev);
|
+
|
+ mutex_init(&data->lock);
|
+
|
+ indio_dev->name = MS1112_DRV_NAME;
|
+ indio_dev->info = chip->info;
|
+ indio_dev->modes = INDIO_DIRECT_MODE;
|
+ indio_dev->channels = chip->channels;
|
+ indio_dev->num_channels = chip->num_channels;
|
+ data->chip = chip;
|
+ data->client = client;
|
+
|
+ for (i = 0; i < MS1112_CHANNELS; i++) {
|
+ int realbits = indio_dev->channels[i].scan_type.realbits;
|
+
|
+ data->thresh_data[i].low_thresh = -1 << (realbits - 1);
|
+ data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1;
|
+ }
|
+
|
+ /* we need to keep this ABI the same as used by hwmon ADS1015 driver */
|
+ ms1112_get_channels_config(client);
|
+
|
+ ret = iio_device_register(indio_dev);
|
+ if (ret)
|
+ dev_err(&client->dev, "Failed to register IIO device\n");
|
+ return ret;
|
+}
|
+
|
+static void ms1112_remove(struct i2c_client *client)
|
+{
|
+ struct iio_dev *indio_dev = i2c_get_clientdata(client);
|
+
|
+ iio_device_unregister(indio_dev);
|
+
|
+}
|
+
|
+static const struct ms1112_chip_data ms1112_data = {
|
+ .channels = ms1112_channels,
|
+ .num_channels = ARRAY_SIZE(ms1112_channels),
|
+ .info = &ms1112_info,
|
+ .data_rate = ms1112_data_rate,
|
+ .data_rate_len = ARRAY_SIZE(ms1112_data_rate),
|
+ .scale = ms1112_scale,
|
+ .scale_len = ARRAY_SIZE(ms1112_scale),
|
+ .has_comparator = false,
|
+};
|
+
|
+static const struct i2c_device_id ms1112_id[] = {
|
+ { "ms1112", (kernel_ulong_t)&ms1112_data },
|
+ {}
|
+};
|
+MODULE_DEVICE_TABLE(i2c, ms1112_id);
|
+
|
+static const struct of_device_id ms1112_of_match[] = {
|
+ { .compatible = "ms,ms1112" },
|
+ { },
|
+};
|
+MODULE_DEVICE_TABLE(of, ms1112_of_match);
|
+
|
+static struct i2c_driver ms1112_driver = {
|
+ .driver = {
|
+ .owner = THIS_MODULE,
|
+ .name = "ms1112",
|
+ .of_match_table = ms1112_of_match,
|
+ },
|
+ .probe = ms1112_probe,
|
+ .remove = ms1112_remove,
|
+ .id_table = ms1112_id,
|
+};
|
+
|
+module_i2c_driver(ms1112_driver);
|
+
|
+MODULE_AUTHOR("Tang Junfeng");
|
+MODULE_DESCRIPTION("MS1112 IIO ADC Driver");
|
+MODULE_LICENSE("GPL");
|
