diff --git a/.gitignore b/.gitignore
|
index 3a4d056e..1893a337 100644
|
--- a/.gitignore
|
+++ b/.gitignore
|
@@ -30,6 +30,7 @@
|
*.order
|
*.patch
|
*.s
|
+*.S
|
*.su
|
*.swp
|
*.tab.[ch]
|
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
|
index 8b65ac0b..5a613cbc 100644
|
--- a/arch/arm/dts/Makefile
|
+++ b/arch/arm/dts/Makefile
|
@@ -942,6 +942,8 @@ dtb-$(CONFIG_MX6ULL) += \
|
imx6ull-14x14-ddr3-val-gpmi-weim.dtb \
|
imx6ull-14x14-ddr3-val-tsc.dtb \
|
imx6ull-14x14-evk.dtb \
|
+ alientek-imx6ull-v20.dtb \
|
+ alientek-imx6ull-v24.dtb \
|
imx6ull-14x14-evk-emmc.dtb \
|
imx6ull-14x14-evk-gpmi-weim.dtb \
|
imx6ull-9x9-evk.dtb \
|
diff --git a/arch/arm/dts/alientek-imx6ull-v20.dts b/arch/arm/dts/alientek-imx6ull-v20.dts
|
new file mode 100644
|
index 00000000..3dee0233
|
--- /dev/null
|
+++ b/arch/arm/dts/alientek-imx6ull-v20.dts
|
@@ -0,0 +1,41 @@
|
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
+//
|
+// Copyright (C) 2022 LingYun IoT System Studio.
|
+
|
+/dts-v1/;
|
+
|
+#include "alientek-imx6ull.dts"
|
+
|
+&fec2 {
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_enet2>;
|
+ phy-mode = "rmii";
|
+ phy-handle = <ðphy1>;
|
+ phy-supply = <®_peri_3v3>;
|
+ phy-reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
|
+ phy-reset-duration = <100>;
|
+ phy-reset-post-delay = <100>;
|
+ status = "okay";
|
+
|
+ mdio {
|
+ #address-cells = <1>;
|
+ #size-cells = <0>;
|
+
|
+ ethphy0: ethernet-phy@2 {
|
+ compatible = "ethernet-phy-id0022.1560";
|
+ reg = <0>;
|
+ micrel,led-mode = <1>;
|
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
|
+ clock-names = "rmii-ref";
|
+ };
|
+
|
+ ethphy1: ethernet-phy@1 {
|
+ compatible = "ethernet-phy-id0022.1560";
|
+ reg = <1>;
|
+ micrel,led-mode = <1>;
|
+ clocks = <&clks IMX6UL_CLK_ENET2_REF>;
|
+ clock-names = "rmii-ref";
|
+ };
|
+ };
|
+};
|
+
|
diff --git a/arch/arm/dts/alientek-imx6ull-v24.dts b/arch/arm/dts/alientek-imx6ull-v24.dts
|
new file mode 100644
|
index 00000000..e78bf08d
|
--- /dev/null
|
+++ b/arch/arm/dts/alientek-imx6ull-v24.dts
|
@@ -0,0 +1,47 @@
|
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
+//
|
+// Copyright (C) 2022 LingYun IoT System Studio.
|
+
|
+/dts-v1/;
|
+
|
+#include "alientek-imx6ull.dts"
|
+
|
+&fec1 {
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_enet1>;
|
+ phy-mode = "rmii";
|
+ phy-handle = <ðphy0>;
|
+ phy-supply = <®_peri_3v3>;
|
+ status = "okay";
|
+};
|
+
|
+&fec2 {
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_enet2>;
|
+ phy-mode = "rmii";
|
+ phy-handle = <ðphy1>;
|
+ phy-supply = <®_peri_3v3>;
|
+ status = "okay";
|
+
|
+ mdio {
|
+ #address-cells = <1>;
|
+ #size-cells = <0>;
|
+
|
+ ethphy0: ethernet-phy@2 {
|
+ compatible = "ethernet-phy-id001c.c800";
|
+ reg = <2>;
|
+ micrel,led-mode = <1>;
|
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
|
+ clock-names = "rmii-ref";
|
+ };
|
+
|
+ ethphy1: ethernet-phy@1 {
|
+ compatible = "ethernet-phy-id001c.c800";
|
+ reg = <1>;
|
+ micrel,led-mode = <1>;
|
+ clocks = <&clks IMX6UL_CLK_ENET2_REF>;
|
+ clock-names = "rmii-ref";
|
+ };
|
+ };
|
+};
|
+
|
diff --git a/arch/arm/dts/alientek-imx6ull.dts b/arch/arm/dts/alientek-imx6ull.dts
|
new file mode 100644
|
index 00000000..f63335db
|
--- /dev/null
|
+++ b/arch/arm/dts/alientek-imx6ull.dts
|
@@ -0,0 +1,259 @@
|
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
+//
|
+// Copyright (C) 2022 LingYun IoT System Studio.
|
+
|
+/dts-v1/;
|
+
|
+#include "imx6ull.dtsi"
|
+
|
+/{
|
+ model = "Freescale i.MX6 ULL 14x14 EVK Board";
|
+ compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
|
+
|
+ chosen {
|
+ stdout-path = &uart1;
|
+ };
|
+
|
+ memory@80000000 {
|
+ device_type = "memory";
|
+ reg = <0x80000000 0x20000000>;
|
+ };
|
+
|
+ reserved-memory {
|
+ #address-cells = <1>;
|
+ #size-cells = <1>;
|
+ ranges;
|
+
|
+ linux,cma {
|
+ compatible = "shared-dma-pool";
|
+ reusable;
|
+ size = <0xa000000>;
|
+ linux,cma-default;
|
+ };
|
+ };
|
+
|
+ reg_sd1_vmmc: regulator-sd1-vmmc {
|
+ compatible = "regulator-fixed";
|
+ regulator-name = "VSD_3V3";
|
+ regulator-min-microvolt = <3300000>;
|
+ regulator-max-microvolt = <3300000>;
|
+ gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
|
+ off-on-delay-us = <20000>;
|
+ enable-active-high;
|
+ };
|
+
|
+ reg_peri_3v3: regulator-peri-3v3 {
|
+ compatible = "regulator-fixed";
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_peri_3v3>;
|
+ regulator-name = "VPERI_3V3";
|
+ regulator-min-microvolt = <3300000>;
|
+ regulator-max-microvolt = <3300000>;
|
+ gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
|
+ regulator-always-on;
|
+ };
|
+
|
+ leds {
|
+ compatible = "gpio-leds";
|
+ status = "okay";
|
+ led0 {
|
+ label = "red";
|
+ gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
|
+ linux,default-trigger = "heartbeat";
|
+ default-state = "on";
|
+ };
|
+ };
|
+};
|
+
|
+
|
+&clks {
|
+ assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
|
+ assigned-clock-rates = <786432000>;
|
+};
|
+
|
+&uart1 {
|
+ pinctrl-names = "default";
|
+ pinctrl-0 = <&pinctrl_uart1>;
|
+ status = "okay";
|
+};
|
+
|
+&usbotg1 {
|
+ dr_mode = "otg";
|
+ srp-disable;
|
+ hnp-disable;
|
+ adp-disable;
|
+ status = "okay";
|
+};
|
+
|
+&usbotg2 {
|
+ dr_mode = "host";
|
+ disable-over-current;
|
+ status = "okay";
|
+};
|
+
|
+&usbphy1 {
|
+ tx-d-cal = <0x5>;
|
+};
|
+
|
+&usbphy2 {
|
+ tx-d-cal = <0x5>;
|
+};
|
+
|
+&usdhc1 {
|
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
+ pinctrl-0 = <&pinctrl_usdhc1>;
|
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
|
+ keep-power-in-suspend;
|
+ wakeup-source;
|
+ vmmc-supply = <®_sd1_vmmc>;
|
+ status = "okay";
|
+};
|
+
|
+&usdhc2 {
|
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
+ pinctrl-0 = <&pinctrl_usdhc2_8bit>;
|
+ pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
|
+ pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
|
+ bus-width = <8>;
|
+ non-removable;
|
+ status = "okay";
|
+};
|
+
|
+&iomuxc {
|
+ pinctrl-names = "default";
|
+ pinctrl_enet1: enet1grp {
|
+ fsl,pins = <
|
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
|
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
|
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
|
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
|
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
|
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
|
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
|
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
|
+ >;
|
+ };
|
+
|
+ pinctrl_enet2: enet2grp {
|
+ fsl,pins = <
|
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
|
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
|
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
|
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
|
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
|
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
|
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
|
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
|
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
|
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
|
+ >;
|
+ };
|
+
|
+ pinctrl_peri_3v3: peri3v3grp {
|
+ fsl,pins = <
|
+ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
|
+ >;
|
+ };
|
+
|
+ pinctrl_uart1: uart1grp {
|
+ fsl,pins = <
|
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
|
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
|
+ >;
|
+ };
|
+
|
+ pinctrl_usdhc1: usdhc1grp {
|
+ fsl,pins = <
|
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
|
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
|
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
|
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
|
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
|
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
|
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
|
+ MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
|
+ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
|
+ >;
|
+ };
|
+
|
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
|
+ fsl,pins = <
|
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
|
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
|
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
|
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
|
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
|
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
|
+ >;
|
+ };
|
+
|
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
|
+ fsl,pins = <
|
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
|
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
|
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
|
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
|
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
|
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
|
+ >;
|
+ };
|
+
|
+ pinctrl_usdhc2: usdhc2grp {
|
+ fsl,pins = <
|
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
|
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
|
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
|
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
|
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
|
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
|
+ >;
|
+ };
|
+
|
+ pinctrl_usdhc2_8bit: usdhc2grp_8bit {
|
+ fsl,pins = <
|
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
|
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
|
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
|
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
|
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
|
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
|
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
|
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
|
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
|
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
|
+ >;
|
+ };
|
+
|
+ pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
|
+ fsl,pins = <
|
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
|
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
|
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
|
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
|
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
|
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
|
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
|
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
|
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
|
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
|
+ >;
|
+ };
|
+
|
+ pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
|
+ fsl,pins = <
|
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
|
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
|
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
|
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
|
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
|
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
|
+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
|
+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
|
+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
|
+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
|
+ >;
|
+ };
|
+};
|
+
|
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
|
index a7a04350..6616b8f9 100644
|
--- a/arch/arm/mach-imx/mx6/Kconfig
|
+++ b/arch/arm/mach-imx/mx6/Kconfig
|
@@ -624,15 +624,12 @@ config TARGET_MX6ULL_9X9_EVK
|
select OF_SYSTEM_SETUP
|
imply CMD_DM
|
|
-config TARGET_MX6ULL_14X14_EVK
|
- bool "Support mx6ull_14x14_evk"
|
+config TARGET_ALIENTEK_IMX6ULL
|
+ bool "Support Alientek iMX6ULL Board v20/v24"
|
depends on MX6ULL
|
select BOARD_LATE_INIT
|
select DM
|
select DM_THERMAL
|
- select IOMUX_LPSR
|
- select IMX_MODULE_FUSE
|
- select OF_SYSTEM_SETUP
|
imply CMD_DM
|
|
config TARGET_MX6ULZ_SMM_M2
|
@@ -875,6 +872,7 @@ source "board/freescale/mx6ul_14x14_ddr3_val/Kconfig"
|
source "board/freescale/mx6ul_14x14_lpddr2_val/Kconfig"
|
source "board/freescale/mx6ullevk/Kconfig"
|
source "board/freescale/mx6ull_ddr3_val/Kconfig"
|
+source "board/freescale/alientek-imx6ull/Kconfig"
|
source "board/bosch/acc/Kconfig"
|
source "board/grinn/liteboard/Kconfig"
|
source "board/phytec/pcm058/Kconfig"
|
diff --git a/board/freescale/alientek-imx6ull/Kconfig b/board/freescale/alientek-imx6ull/Kconfig
|
new file mode 100644
|
index 00000000..c0d67681
|
--- /dev/null
|
+++ b/board/freescale/alientek-imx6ull/Kconfig
|
@@ -0,0 +1,17 @@
|
+if TARGET_ALIENTEK_IMX6ULL
|
+
|
+config SYS_BOARD
|
+ default "alientek-imx6ull"
|
+
|
+config SYS_VENDOR
|
+ default "freescale"
|
+
|
+config SYS_CONFIG_NAME
|
+ default "alientek-imx6ull"
|
+
|
+config IMX_CONFIG
|
+ default "board/freescale/alientek-imx6ull/imximage.cfg"
|
+
|
+config TEXT_BASE
|
+ default 0x87800000
|
+endif
|
diff --git a/board/freescale/alientek-imx6ull/MAINTAINERS b/board/freescale/alientek-imx6ull/MAINTAINERS
|
new file mode 100644
|
index 00000000..1b97ad3f
|
--- /dev/null
|
+++ b/board/freescale/alientek-imx6ull/MAINTAINERS
|
@@ -0,0 +1,6 @@
|
+MX6ULLEVK BOARD
|
+M: Peng Fan <peng.fan@nxp.com>
|
+S: Maintained
|
+F: board/freescale/mx6ullevk/
|
+F: include/configs/mx6ullevk.h
|
+F: configs/alientek-imx6ull-v20_defconfig
|
diff --git a/board/freescale/alientek-imx6ull/Makefile b/board/freescale/alientek-imx6ull/Makefile
|
new file mode 100644
|
index 00000000..86ce97fd
|
--- /dev/null
|
+++ b/board/freescale/alientek-imx6ull/Makefile
|
@@ -0,0 +1,4 @@
|
+# SPDX-License-Identifier: GPL-2.0+
|
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
|
+
|
+obj-y := alientek-imx6ull.o
|
diff --git a/board/freescale/alientek-imx6ull/alientek-imx6ull.c b/board/freescale/alientek-imx6ull/alientek-imx6ull.c
|
new file mode 100644
|
index 00000000..598eb7df
|
--- /dev/null
|
+++ b/board/freescale/alientek-imx6ull/alientek-imx6ull.c
|
@@ -0,0 +1,365 @@
|
+// SPDX-License-Identifier: GPL-2.0+
|
+/*
|
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
|
+ * Copyright 2017 NXP
|
+ */
|
+
|
+#include <init.h>
|
+#include <asm/arch/clock.h>
|
+#include <asm/arch/iomux.h>
|
+#include <asm/arch/imx-regs.h>
|
+#include <asm/arch/crm_regs.h>
|
+#include <asm/arch/mx6-pins.h>
|
+#include <asm/arch/sys_proto.h>
|
+#include <asm/global_data.h>
|
+#include <asm/gpio.h>
|
+#include <asm/mach-imx/iomux-v3.h>
|
+#include <asm/mach-imx/boot_mode.h>
|
+#include <asm/mach-imx/mxc_i2c.h>
|
+#include <asm/io.h>
|
+#include <common.h>
|
+#include <env.h>
|
+#include <fsl_esdhc_imx.h>
|
+#include <i2c.h>
|
+#include <miiphy.h>
|
+#include <linux/sizes.h>
|
+#include <linux/delay.h>
|
+#include <mmc.h>
|
+#include <miiphy.h>
|
+#include <power/pmic.h>
|
+#include <power/pfuze3000_pmic.h>
|
+#include "../common/pfuze.h"
|
+
|
+DECLARE_GLOBAL_DATA_PTR;
|
+
|
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
+ PAD_CTL_ODE)
|
+
|
+#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
|
+ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
|
+
|
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
|
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
|
+ PAD_CTL_SRE_FAST)
|
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
|
+
|
+
|
+#ifdef CONFIG_DM_PMIC
|
+int power_init_board(void)
|
+{
|
+ struct udevice *dev;
|
+ int ret, dev_id, rev_id;
|
+ unsigned int reg;
|
+
|
+ ret = pmic_get("pfuze3000@8", &dev);
|
+ if (ret == -ENODEV)
|
+ return 0;
|
+ if (ret != 0)
|
+ return ret;
|
+
|
+ dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
|
+ rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
|
+ printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
|
+
|
+ /* disable Low Power Mode during standby mode */
|
+ reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
|
+ reg |= 0x1;
|
+ pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
|
+
|
+ /* SW1B step ramp up time from 2us to 4us/25mV */
|
+ pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
|
+
|
+ /* SW1B mode to APS/PFM */
|
+ pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
|
+
|
+ /* SW1B standby voltage set to 0.975V */
|
+ pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
|
+
|
+ return 0;
|
+}
|
+
|
+#ifdef CONFIG_LDO_BYPASS_CHECK
|
+void ldo_mode_set(int ldo_bypass)
|
+{
|
+ unsigned int value;
|
+ u32 vddarm;
|
+ struct udevice *dev;
|
+ int ret;
|
+
|
+ ret = pmic_get("pfuze3000@8", &dev);
|
+ if (ret == -ENODEV) {
|
+ printf("No PMIC found!\n");
|
+ return;
|
+ }
|
+
|
+ /* switch to ldo_bypass mode */
|
+ if (ldo_bypass) {
|
+ prep_anatop_bypass();
|
+ /* decrease VDDARM to 1.275V */
|
+ value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
|
+ value &= ~0x1f;
|
+ value |= PFUZE3000_SW1AB_SETP(12750);
|
+ pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value);
|
+
|
+ set_anatop_bypass(1);
|
+ vddarm = PFUZE3000_SW1AB_SETP(11750);
|
+
|
+ value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
|
+ value &= ~0x1f;
|
+ value |= vddarm;
|
+ pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value);
|
+
|
+ finish_anatop_bypass();
|
+
|
+ printf("switch to ldo_bypass mode!\n");
|
+ }
|
+}
|
+#endif
|
+#endif
|
+
|
+int dram_init(void)
|
+{
|
+ gd->ram_size = imx_ddr_size();
|
+
|
+ return 0;
|
+}
|
+
|
+int board_mmc_get_env_dev(int devno)
|
+{
|
+ return devno;
|
+}
|
+
|
+#ifdef CONFIG_FSL_QSPI
|
+
|
+#ifndef CONFIG_DM_SPI
|
+#define QSPI_PAD_CTRL1 \
|
+ (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
|
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
|
+
|
+static iomux_v3_cfg_t const quadspi_pads[] = {
|
+ MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
+ MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
+ MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
+ MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
+ MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
+ MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
|
+};
|
+#endif
|
+
|
+static int board_qspi_init(void)
|
+{
|
+#ifndef CONFIG_DM_SPI
|
+ /* Set the iomux */
|
+ imx_iomux_v3_setup_multiple_pads(quadspi_pads,
|
+ ARRAY_SIZE(quadspi_pads));
|
+#endif
|
+ /* Set the clock */
|
+ enable_qspi_clk(0);
|
+
|
+ return 0;
|
+}
|
+#endif
|
+
|
+#ifdef CONFIG_NAND_MXS
|
+static iomux_v3_cfg_t const nand_pads[] = {
|
+ MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
+ MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
+ MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
+ MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
+ MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
+ MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
+ MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
+ MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
+ MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
+ MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
+ MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
+ MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
+ MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
+ MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
+ MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
+ MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
+ MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
|
+};
|
+
|
+static void setup_gpmi_nand(void)
|
+{
|
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
+
|
+ /* config gpmi nand iomux */
|
+ imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
|
+
|
+ setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
|
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
|
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
|
+
|
+ /* enable apbh clock gating */
|
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
|
+}
|
+#endif
|
+
|
+#ifdef CONFIG_FEC_MXC
|
+static int setup_fec(void)
|
+{
|
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
+ int ret;
|
+
|
+ /*
|
+ * Use 50M anatop loopback REF_CLK1 for ENET1,
|
+ * clear gpr1[13], set gpr1[17].
|
+ */
|
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
|
+ IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
|
+ /*
|
+ * Use 50M anatop loopback REF_CLK2 for ENET2,
|
+ * clear gpr1[14], set gpr1[18].
|
+ */
|
+ if (!check_module_fused(MODULE_ENET2)) {
|
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
|
+ IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
|
+ }
|
+
|
+ ret = enable_fec_anatop_clock(0, ENET_50MHZ);
|
+ if (ret)
|
+ return ret;
|
+
|
+ if (!check_module_fused(MODULE_ENET2)) {
|
+ ret = enable_fec_anatop_clock(1, ENET_50MHZ);
|
+ if (ret)
|
+ return ret;
|
+ }
|
+
|
+ enable_enet_clk(1);
|
+
|
+ return 0;
|
+}
|
+
|
+int board_phy_config(struct phy_device *phydev)
|
+{
|
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
|
+
|
+ if (phydev->drv->config)
|
+ phydev->drv->config(phydev);
|
+
|
+ return 0;
|
+}
|
+#endif
|
+
|
+#ifdef CONFIG_VIDEO
|
+static iomux_v3_cfg_t const lcd_pads[] = {
|
+ /* Use GPIO for Brightness adjustment, duty cycle = period. */
|
+ MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
+};
|
+
|
+static int setup_lcd(void)
|
+{
|
+ enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
|
+
|
+ imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
|
+
|
+ /* Reset the LCD */
|
+ gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
|
+ gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
|
+ udelay(500);
|
+ gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
|
+
|
+ /* Set Brightness to high */
|
+ gpio_request(IMX_GPIO_NR(1, 8), "backlight");
|
+ gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
|
+
|
+ return 0;
|
+}
|
+#else
|
+static inline int setup_lcd(void) { return 0; }
|
+#endif
|
+
|
+int board_early_init_f(void)
|
+{
|
+ return 0;
|
+}
|
+
|
+int board_init(void)
|
+{
|
+ /* Address of boot parameters */
|
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
+
|
+#ifdef CONFIG_FEC_MXC
|
+ setup_fec();
|
+#endif
|
+
|
+#ifdef CONFIG_FSL_QSPI
|
+ board_qspi_init();
|
+#endif
|
+
|
+#ifdef CONFIG_NAND_MXS
|
+ setup_gpmi_nand();
|
+#endif
|
+
|
+ return 0;
|
+}
|
+
|
+#ifdef CONFIG_CMD_BMODE
|
+static const struct boot_mode board_boot_modes[] = {
|
+ /* 4 bit bus width */
|
+ {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
|
+ {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
|
+ {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
|
+ {NULL, 0},
|
+};
|
+#endif
|
+
|
+int board_late_init(void)
|
+{
|
+#ifdef CONFIG_CMD_BMODE
|
+ add_board_boot_modes(board_boot_modes);
|
+#endif
|
+
|
+ env_set("tee", "no");
|
+#ifdef CONFIG_IMX_OPTEE
|
+ env_set("tee", "yes");
|
+#endif
|
+
|
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
+ env_set("board_name", "EVK");
|
+
|
+ if (is_mx6ull_9x9_evk())
|
+ env_set("board_rev", "9X9");
|
+ else
|
+ env_set("board_rev", "14X14");
|
+
|
+ if (is_cpu_type(MXC_CPU_MX6ULZ)) {
|
+ env_set("board_name", "ULZ-EVK");
|
+ env_set("usb_net_cmd", "usb start");
|
+ }
|
+#endif
|
+
|
+ setup_lcd();
|
+
|
+#ifdef CONFIG_ENV_IS_IN_MMC
|
+ board_late_mmc_env_init();
|
+#endif
|
+
|
+ set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
|
+
|
+ return 0;
|
+}
|
+
|
+int checkboard(void)
|
+{
|
+ if (is_mx6ull_9x9_evk())
|
+ puts("Board: MX6ULL 9x9 EVK\n");
|
+ else if (is_cpu_type(MXC_CPU_MX6ULZ))
|
+ puts("Board: MX6ULZ 14x14 EVK\n");
|
+ else
|
+ puts("Board: MX6ULL 14x14 EVK\n");
|
+
|
+ return 0;
|
+}
|
+
|
+void board_quiesce_devices(void)
|
+{
|
+#if defined(CONFIG_VIDEO_MXS)
|
+ enable_lcdif_clock(LCDIF1_BASE_ADDR, 0);
|
+#endif
|
+}
|
diff --git a/board/freescale/alientek-imx6ull/imximage.cfg b/board/freescale/alientek-imx6ull/imximage.cfg
|
new file mode 100644
|
index 00000000..451ff602
|
--- /dev/null
|
+++ b/board/freescale/alientek-imx6ull/imximage.cfg
|
@@ -0,0 +1,120 @@
|
+/* SPDX-License-Identifier: GPL-2.0+ */
|
+/*
|
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
|
+ * Copyright 2017 NXP
|
+ *
|
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
|
+ * and create imximage boot image
|
+ *
|
+ * The syntax is taken as close as possible with the kwbimage
|
+ */
|
+
|
+#include <config.h>
|
+
|
+/* image version */
|
+
|
+IMAGE_VERSION 2
|
+
|
+/*
|
+ * Boot Device : one of
|
+ * spi/sd/nand/onenand, qspi/nor
|
+ */
|
+
|
+#ifdef CONFIG_QSPI_BOOT
|
+BOOT_FROM qspi
|
+#elif defined(CONFIG_NOR_BOOT)
|
+BOOT_FROM nor
|
+#else
|
+BOOT_FROM sd
|
+#endif
|
+
|
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
|
+/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
|
+PLUGIN board/freescale/alientek-imx6ull/plugin.bin 0x00907000
|
+#else
|
+
|
+#ifdef CONFIG_IMX_HAB
|
+CSF CONFIG_CSF_SIZE
|
+#endif
|
+
|
+/*
|
+ * Device Configuration Data (DCD)
|
+ *
|
+ * Each entry must have the format:
|
+ * Addr-type Address Value
|
+ *
|
+ * where:
|
+ * Addr-type register length (1,2 or 4 bytes)
|
+ * Address absolute address of the register
|
+ * value value to be stored in the register
|
+ */
|
+
|
+/* Enable all clocks */
|
+DATA 4 0x020c4068 0xffffffff
|
+DATA 4 0x020c406c 0xffffffff
|
+DATA 4 0x020c4070 0xffffffff
|
+DATA 4 0x020c4074 0xffffffff
|
+DATA 4 0x020c4078 0xffffffff
|
+DATA 4 0x020c407c 0xffffffff
|
+DATA 4 0x020c4080 0xffffffff
|
+
|
+#ifdef CONFIG_IMX_OPTEE
|
+DATA 4 0x20e4024 0x00000001
|
+CHECK_BITS_SET 4 0x20e4024 0x1
|
+#endif
|
+
|
+DATA 4 0x020E04B4 0x000C0000
|
+DATA 4 0x020E04AC 0x00000000
|
+DATA 4 0x020E027C 0x00000030
|
+DATA 4 0x020E0250 0x00000030
|
+DATA 4 0x020E024C 0x00000030
|
+DATA 4 0x020E0490 0x00000030
|
+DATA 4 0x020E0288 0x000C0030
|
+DATA 4 0x020E0270 0x00000000
|
+DATA 4 0x020E0260 0x00000030
|
+DATA 4 0x020E0264 0x00000030
|
+DATA 4 0x020E04A0 0x00000030
|
+DATA 4 0x020E0494 0x00020000
|
+DATA 4 0x020E0280 0x00000030
|
+DATA 4 0x020E0284 0x00000030
|
+DATA 4 0x020E04B0 0x00020000
|
+DATA 4 0x020E0498 0x00000030
|
+DATA 4 0x020E04A4 0x00000030
|
+DATA 4 0x020E0244 0x00000030
|
+DATA 4 0x020E0248 0x00000030
|
+DATA 4 0x021B001C 0x00008000
|
+DATA 4 0x021B0800 0xA1390003
|
+DATA 4 0x021B080C 0x00000004
|
+DATA 4 0x021B083C 0x41640158
|
+DATA 4 0x021B0848 0x40403237
|
+DATA 4 0x021B0850 0x40403C33
|
+DATA 4 0x021B081C 0x33333333
|
+DATA 4 0x021B0820 0x33333333
|
+DATA 4 0x021B082C 0xf3333333
|
+DATA 4 0x021B0830 0xf3333333
|
+DATA 4 0x021B08C0 0x00944009
|
+DATA 4 0x021B08b8 0x00000800
|
+DATA 4 0x021B0004 0x0002002D
|
+DATA 4 0x021B0008 0x1B333030
|
+DATA 4 0x021B000C 0x676B52F3
|
+DATA 4 0x021B0010 0xB66D0B63
|
+DATA 4 0x021B0014 0x01FF00DB
|
+DATA 4 0x021B0018 0x00201740
|
+DATA 4 0x021B001C 0x00008000
|
+DATA 4 0x021B002C 0x000026D2
|
+DATA 4 0x021B0030 0x006B1023
|
+DATA 4 0x021B0040 0x0000004F
|
+DATA 4 0x021B0000 0x84180000
|
+DATA 4 0x021B0890 0x00400000
|
+DATA 4 0x021B001C 0x02008032
|
+DATA 4 0x021B001C 0x00008033
|
+DATA 4 0x021B001C 0x00048031
|
+DATA 4 0x021B001C 0x15208030
|
+DATA 4 0x021B001C 0x04008040
|
+DATA 4 0x021B0020 0x00000800
|
+DATA 4 0x021B0818 0x00000227
|
+DATA 4 0x021B0004 0x0002552D
|
+DATA 4 0x021B0404 0x00011006
|
+DATA 4 0x021B001C 0x00000000
|
+
|
+#endif
|
diff --git a/board/freescale/alientek-imx6ull/imximage_lpddr2.cfg b/board/freescale/alientek-imx6ull/imximage_lpddr2.cfg
|
new file mode 100644
|
index 00000000..23d770eb
|
--- /dev/null
|
+++ b/board/freescale/alientek-imx6ull/imximage_lpddr2.cfg
|
@@ -0,0 +1,125 @@
|
+/*
|
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
|
+ * Copyright 2017 NXP
|
+ *
|
+ * SPDX-License-Identifier: GPL-2.0+
|
+ *
|
+ * Refer docs/README.imxmage for more details about how-to configure
|
+ * and create imximage boot image
|
+ *
|
+ * The syntax is taken as close as possible with the kwbimage
|
+ */
|
+
|
+#include <config.h>
|
+
|
+/* image version */
|
+
|
+IMAGE_VERSION 2
|
+
|
+/*
|
+ * Boot Device : one of
|
+ * spi/sd/nand/onenand, qspi/nor
|
+ */
|
+
|
+#ifdef CONFIG_QSPI_BOOT
|
+BOOT_FROM qspi
|
+#elif defined(CONFIG_NOR_BOOT)
|
+BOOT_FROM nor
|
+#else
|
+BOOT_FROM sd
|
+#endif
|
+
|
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
|
+/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
|
+PLUGIN board/freescale/mx6ullevk/plugin.bin 0x00907000
|
+#else
|
+
|
+#ifdef CONFIG_IMX_HAB
|
+CSF CONFIG_CSF_SIZE
|
+#endif
|
+
|
+/*
|
+ * Device Configuration Data (DCD)
|
+ *
|
+ * Each entry must have the format:
|
+ * Addr-type Address Value
|
+ *
|
+ * where:
|
+ * Addr-type register length (1,2 or 4 bytes)
|
+ * Address absolute address of the register
|
+ * value value to be stored in the register
|
+ */
|
+
|
+DATA 4 0x020c4068 0xffffffff
|
+DATA 4 0x020c406c 0xffffffff
|
+DATA 4 0x020c4070 0xffffffff
|
+DATA 4 0x020c4074 0xffffffff
|
+DATA 4 0x020c4078 0xffffffff
|
+DATA 4 0x020c407c 0xffffffff
|
+DATA 4 0x020c4080 0xffffffff
|
+
|
+#ifdef CONFIG_IMX_OPTEE
|
+DATA 4 0x20e4024 0x00000001
|
+CHECK_BITS_SET 4 0x20e4024 0x1
|
+#endif
|
+
|
+DATA 4 0x020E04B4 0x00080000
|
+DATA 4 0x020E04AC 0x00000000
|
+DATA 4 0x020E027C 0x00000030
|
+DATA 4 0x020E0250 0x00000030
|
+DATA 4 0x020E024C 0x00000030
|
+DATA 4 0x020E0490 0x00000030
|
+DATA 4 0x020E0288 0x00000030
|
+DATA 4 0x020E0270 0x00000000
|
+DATA 4 0x020E0260 0x00000000
|
+DATA 4 0x020E0264 0x00000000
|
+DATA 4 0x020E04A0 0x00000030
|
+DATA 4 0x020E0494 0x00020000
|
+DATA 4 0x020E0280 0x00003030
|
+DATA 4 0x020E0284 0x00003030
|
+DATA 4 0x020E04B0 0x00020000
|
+DATA 4 0x020E0498 0x00000030
|
+DATA 4 0x020E04A4 0x00000030
|
+DATA 4 0x020E0244 0x00000030
|
+DATA 4 0x020E0248 0x00000030
|
+
|
+DATA 4 0x021B001C 0x00008000
|
+DATA 4 0x021B085C 0x1b4700c7
|
+DATA 4 0x021B0800 0xA1390003
|
+DATA 4 0x021B0890 0x23400A38
|
+DATA 4 0x021B08b8 0x00000800
|
+
|
+DATA 4 0x021B081C 0x33333333
|
+DATA 4 0x021B0820 0x33333333
|
+DATA 4 0x021B082C 0xf3333333
|
+DATA 4 0x021B0830 0xf3333333
|
+DATA 4 0x021B083C 0x20000000
|
+DATA 4 0x021B0848 0x40403439
|
+DATA 4 0x021B0850 0x4040342D
|
+DATA 4 0x021B08C0 0x00921012
|
+DATA 4 0x021B08b8 0x00000800
|
+
|
+DATA 4 0x021B0004 0x00020052
|
+DATA 4 0x021B0008 0x00000000
|
+DATA 4 0x021B000C 0x33374133
|
+DATA 4 0x021B0010 0x00100A82
|
+DATA 4 0x021B0038 0x00170557
|
+DATA 4 0x021B0014 0x00000093
|
+DATA 4 0x021B0018 0x00201748
|
+DATA 4 0x021B002C 0x0F9F26D2
|
+DATA 4 0x021B0030 0x009F0010
|
+DATA 4 0x021B0040 0x00000047
|
+DATA 4 0x021B0000 0x83100000
|
+DATA 4 0x021B001C 0x00008010
|
+DATA 4 0x021B001C 0x003F8030
|
+DATA 4 0x021B001C 0xFF0A8030
|
+DATA 4 0x021B001C 0x82018030
|
+DATA 4 0x021B001C 0x04028030
|
+DATA 4 0x021B001C 0x01038030
|
+DATA 4 0x021B0020 0x00001800
|
+DATA 4 0x021B0818 0x00000000
|
+DATA 4 0x021B0800 0xA1310003
|
+DATA 4 0x021B0004 0x00025552
|
+DATA 4 0x021B0404 0x00011006
|
+DATA 4 0x021B001C 0x00000000
|
+#endif
|
diff --git a/board/freescale/alientek-imx6ull/plugin.S b/board/freescale/alientek-imx6ull/plugin.S
|
new file mode 100644
|
index 00000000..812088d1
|
--- /dev/null
|
+++ b/board/freescale/alientek-imx6ull/plugin.S
|
@@ -0,0 +1,263 @@
|
+/* SPDX-License-Identifier: GPL-2.0+ */
|
+/*
|
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
|
+ * Copyright 2017 NXP
|
+ */
|
+
|
+#include <config.h>
|
+
|
+/* DDR script */
|
+.macro imx6ull_ddr3_evk_setting
|
+ ldr r0, =IOMUXC_BASE_ADDR
|
+ ldr r1, =0x000C0000
|
+ str r1, [r0, #0x4B4]
|
+ ldr r1, =0x00000000
|
+ str r1, [r0, #0x4AC]
|
+ ldr r1, =0x00000030
|
+ str r1, [r0, #0x27C]
|
+ ldr r1, =0x00000030
|
+ str r1, [r0, #0x250]
|
+ str r1, [r0, #0x24C]
|
+ str r1, [r0, #0x490]
|
+ ldr r1, =0x000C0030
|
+ str r1, [r0, #0x288]
|
+
|
+ ldr r1, =0x00000000
|
+ str r1, [r0, #0x270]
|
+
|
+ ldr r1, =0x00000030
|
+ str r1, [r0, #0x260]
|
+ str r1, [r0, #0x264]
|
+ str r1, [r0, #0x4A0]
|
+
|
+ ldr r1, =0x00020000
|
+ str r1, [r0, #0x494]
|
+
|
+ ldr r1, =0x00000030
|
+ str r1, [r0, #0x280]
|
+ ldr r1, =0x00000030
|
+ str r1, [r0, #0x284]
|
+
|
+ ldr r1, =0x00020000
|
+ str r1, [r0, #0x4B0]
|
+
|
+ ldr r1, =0x00000030
|
+ str r1, [r0, #0x498]
|
+ str r1, [r0, #0x4A4]
|
+ str r1, [r0, #0x244]
|
+ str r1, [r0, #0x248]
|
+
|
+ ldr r0, =MMDC_P0_BASE_ADDR
|
+ ldr r1, =0x00008000
|
+ str r1, [r0, #0x1C]
|
+ ldr r1, =0xA1390003
|
+ str r1, [r0, #0x800]
|
+ ldr r1, =0x00000004
|
+ str r1, [r0, #0x80C]
|
+ ldr r1, =0x41640158
|
+ str r1, [r0, #0x83C]
|
+ ldr r1, =0x40403237
|
+ str r1, [r0, #0x848]
|
+ ldr r1, =0x40403C33
|
+ str r1, [r0, #0x850]
|
+ ldr r1, =0x33333333
|
+ str r1, [r0, #0x81C]
|
+ str r1, [r0, #0x820]
|
+ ldr r1, =0xF3333333
|
+ str r1, [r0, #0x82C]
|
+ str r1, [r0, #0x830]
|
+ ldr r1, =0x00944009
|
+ str r1, [r0, #0x8C0]
|
+ ldr r1, =0x00000800
|
+ str r1, [r0, #0x8B8]
|
+ ldr r1, =0x0002002D
|
+ str r1, [r0, #0x004]
|
+ ldr r1, =0x1B333030
|
+ str r1, [r0, #0x008]
|
+ ldr r1, =0x676B52F3
|
+ str r1, [r0, #0x00C]
|
+ ldr r1, =0xB66D0B63
|
+ str r1, [r0, #0x010]
|
+ ldr r1, =0x01FF00DB
|
+ str r1, [r0, #0x014]
|
+ ldr r1, =0x00201740
|
+ str r1, [r0, #0x018]
|
+ ldr r1, =0x00008000
|
+ str r1, [r0, #0x01C]
|
+ ldr r1, =0x000026D2
|
+ str r1, [r0, #0x02C]
|
+ ldr r1, =0x006B1023
|
+ str r1, [r0, #0x030]
|
+ ldr r1, =0x0000004F
|
+ str r1, [r0, #0x040]
|
+ ldr r1, =0x84180000
|
+ str r1, [r0, #0x000]
|
+ ldr r1, =0x00400000
|
+ str r1, [r0, #0x890]
|
+ ldr r1, =0x02008032
|
+ str r1, [r0, #0x01C]
|
+ ldr r1, =0x00008033
|
+ str r1, [r0, #0x01C]
|
+ ldr r1, =0x00048031
|
+ str r1, [r0, #0x01C]
|
+ ldr r1, =0x15208030
|
+ str r1, [r0, #0x01C]
|
+ ldr r1, =0x04008040
|
+ str r1, [r0, #0x01C]
|
+ ldr r1, =0x00000800
|
+ str r1, [r0, #0x020]
|
+ ldr r1, =0x00000227
|
+ str r1, [r0, #0x818]
|
+ ldr r1, =0x0002552D
|
+ str r1, [r0, #0x004]
|
+ ldr r1, =0x00011006
|
+ str r1, [r0, #0x404]
|
+ ldr r1, =0x00000000
|
+ str r1, [r0, #0x01C]
|
+.endm
|
+
|
+.macro imx6ull_lpddr2_evk_setting
|
+ ldr r0, =IOMUXC_BASE_ADDR
|
+ ldr r1, =0x00080000
|
+ str r1, [r0, #0x4B4]
|
+ ldr r1, =0x00000000
|
+ str r1, [r0, #0x4AC]
|
+ ldr r1, =0x00000030
|
+ str r1, [r0, #0x27C]
|
+ str r1, [r0, #0x250]
|
+ str r1, [r0, #0x24C]
|
+ str r1, [r0, #0x490]
|
+ str r1, [r0, #0x288]
|
+
|
+ ldr r1, =0x00000000
|
+ str r1, [r0, #0x270]
|
+ str r1, [r0, #0x260]
|
+ str r1, [r0, #0x264]
|
+
|
+ ldr r1, =0x00000030
|
+ str r1, [r0, #0x4A0]
|
+
|
+ ldr r1, =0x00020000
|
+ str r1, [r0, #0x494]
|
+
|
+ ldr r1, =0x00003030
|
+ str r1, [r0, #0x280]
|
+ ldr r1, =0x00003030
|
+ str r1, [r0, #0x284]
|
+
|
+ ldr r1, =0x00020000
|
+ str r1, [r0, #0x4B0]
|
+
|
+ ldr r1, =0x00000030
|
+ str r1, [r0, #0x498]
|
+ str r1, [r0, #0x4A4]
|
+ str r1, [r0, #0x244]
|
+ str r1, [r0, #0x248]
|
+
|
+ ldr r0, =MMDC_P0_BASE_ADDR
|
+ ldr r1, =0x00008000
|
+ str r1, [r0, #0x1C]
|
+ ldr r1, =0x1b4700c7
|
+ str r1, [r0, #0x85c]
|
+ ldr r1, =0xA1390003
|
+ str r1, [r0, #0x800]
|
+ ldr r1, =0x23400A38
|
+ str r1, [r0, #0x890]
|
+ ldr r1, =0x00000800
|
+ str r1, [r0, #0x8b8]
|
+ ldr r1, =0x33333333
|
+ str r1, [r0, #0x81C]
|
+ str r1, [r0, #0x820]
|
+ ldr r1, =0xF3333333
|
+ str r1, [r0, #0x82C]
|
+ str r1, [r0, #0x830]
|
+ ldr r1, =0x20000000
|
+ str r1, [r0, #0x83C]
|
+ ldr r1, =0x40403439
|
+ str r1, [r0, #0x848]
|
+ ldr r1, =0x4040342D
|
+ str r1, [r0, #0x850]
|
+ ldr r1, =0x00921012
|
+ str r1, [r0, #0x8C0]
|
+ ldr r1, =0x00000800
|
+ str r1, [r0, #0x8B8]
|
+
|
+ ldr r1, =0x00020052
|
+ str r1, [r0, #0x004]
|
+ ldr r1, =0x00000000
|
+ str r1, [r0, #0x008]
|
+ ldr r1, =0x33374133
|
+ str r1, [r0, #0x00C]
|
+ ldr r1, =0x00100A82
|
+ str r1, [r0, #0x010]
|
+ ldr r1, =0x00170557
|
+ str r1, [r0, #0x038]
|
+ ldr r1, =0x00000093
|
+ str r1, [r0, #0x014]
|
+ ldr r1, =0x00201748
|
+ str r1, [r0, #0x018]
|
+ ldr r1, =0x0F9F26D2
|
+ str r1, [r0, #0x02C]
|
+ ldr r1, =0x009F0010
|
+ str r1, [r0, #0x030]
|
+ ldr r1, =0x00000047
|
+ str r1, [r0, #0x040]
|
+ ldr r1, =0x83100000
|
+ str r1, [r0, #0x000]
|
+ ldr r1, =0x00008010
|
+ str r1, [r0, #0x01C]
|
+ ldr r1, =0x003F8030
|
+ str r1, [r0, #0x01C]
|
+ ldr r1, =0xFF0A8030
|
+ str r1, [r0, #0x01C]
|
+ ldr r1, =0x82018030
|
+ str r1, [r0, #0x01C]
|
+ ldr r1, =0x04028030
|
+ str r1, [r0, #0x01C]
|
+ ldr r1, =0x01038030
|
+ str r1, [r0, #0x01C]
|
+ ldr r1, =0x00001800
|
+ str r1, [r0, #0x020]
|
+ ldr r1, =0x00000000
|
+ str r1, [r0, #0x818]
|
+ ldr r1, =0xA1310003
|
+ str r1, [r0, #0x800]
|
+ ldr r1, =0x00025552
|
+ str r1, [r0, #0x004]
|
+ ldr r1, =0x00011006
|
+ str r1, [r0, #0x404]
|
+ ldr r1, =0x00000000
|
+ str r1, [r0, #0x01C]
|
+.endm
|
+
|
+.macro imx6_clock_gating
|
+ ldr r0, =CCM_BASE_ADDR
|
+ ldr r1, =0xFFFFFFFF
|
+ str r1, [r0, #0x68]
|
+ str r1, [r0, #0x6C]
|
+ str r1, [r0, #0x70]
|
+ str r1, [r0, #0x74]
|
+ str r1, [r0, #0x78]
|
+ str r1, [r0, #0x7C]
|
+ str r1, [r0, #0x80]
|
+
|
+#ifdef CONFIG_IMX_OPTEE
|
+ ldr r0, =0x20e4024
|
+ ldr r1, =0x1
|
+ str r1, [r0]
|
+#endif
|
+.endm
|
+
|
+.macro imx6_qos_setting
|
+.endm
|
+
|
+.macro imx6_ddr_setting
|
+#if defined (CONFIG_TARGET_MX6ULL_9X9_EVK)
|
+ imx6ull_lpddr2_evk_setting
|
+#else
|
+ imx6ull_ddr3_evk_setting
|
+#endif
|
+.endm
|
+
|
+/* include the common plugin code here */
|
+#include <asm/arch/mx6_plugin.S>
|
diff --git a/configs/alientek-imx6ull-v20_defconfig b/configs/alientek-imx6ull-v20_defconfig
|
new file mode 100644
|
index 00000000..1af20da1
|
--- /dev/null
|
+++ b/configs/alientek-imx6ull-v20_defconfig
|
@@ -0,0 +1,113 @@
|
+CONFIG_ARM=y
|
+CONFIG_ARCH_MX6=y
|
+CONFIG_SYS_MALLOC_LEN=0x1000000
|
+CONFIG_NR_DRAM_BANKS=1
|
+CONFIG_SYS_MEMTEST_START=0x80000000
|
+CONFIG_SYS_MEMTEST_END=0x88000000
|
+CONFIG_ENV_SIZE=0x2000
|
+CONFIG_ENV_OFFSET=0xE0000
|
+CONFIG_MX6ULL=y
|
+CONFIG_TARGET_ALIENTEK_IMX6ULL=y
|
+# CONFIG_LDO_BYPASS_CHECK is not set
|
+CONFIG_SYS_I2C_MXC_I2C1=y
|
+CONFIG_SYS_I2C_MXC_I2C2=y
|
+CONFIG_DM_GPIO=y
|
+CONFIG_DEFAULT_DEVICE_TREE="alientek-imx6ull-v20"
|
+CONFIG_SUPPORT_RAW_INITRD=y
|
+CONFIG_USE_BOOTCOMMAND=y
|
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
|
+CONFIG_ARCH_MISC_INIT=y
|
+CONFIG_BOOTDELAY=3
|
+# CONFIG_CONSOLE_MUX is not set
|
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
+CONFIG_BOARD_EARLY_INIT_F=y
|
+CONFIG_HUSH_PARSER=y
|
+CONFIG_SYS_MAXARGS=32
|
+CONFIG_SYS_PBSIZE=532
|
+CONFIG_CMD_BOOTZ=y
|
+# CONFIG_CMD_IMLS is not set
|
+CONFIG_CMD_MEMTEST=y
|
+CONFIG_CMD_GPIO=y
|
+CONFIG_CMD_I2C=y
|
+CONFIG_CMD_MMC=y
|
+CONFIG_CMD_SF=y
|
+CONFIG_CMD_USB=y
|
+CONFIG_CMD_DHCP=y
|
+CONFIG_CMD_PING=y
|
+CONFIG_CMD_BMP=y
|
+CONFIG_CMD_CACHE=y
|
+CONFIG_CMD_RNG=y
|
+CONFIG_CMD_NET=y
|
+CONFIG_CMD_EXT2=y
|
+CONFIG_CMD_EXT4=y
|
+CONFIG_CMD_EXT4_WRITE=y
|
+CONFIG_CMD_FAT=y
|
+CONFIG_CMD_FS_GENERIC=y
|
+CONFIG_OF_CONTROL=y
|
+CONFIG_ENV_OVERWRITE=y
|
+CONFIG_ENV_IS_IN_MMC=y
|
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
+CONFIG_SYS_MMC_ENV_DEV=1
|
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
+CONFIG_USE_ETHPRIME=y
|
+CONFIG_ETHPRIME="eth1"
|
+CONFIG_BOUNCE_BUFFER=y
|
+CONFIG_FSL_DCP_RNG=y
|
+CONFIG_DM_74X164=y
|
+CONFIG_DM_I2C=y
|
+CONFIG_SYS_I2C_MXC=y
|
+CONFIG_FSL_USDHC=y
|
+CONFIG_MTD=y
|
+CONFIG_DM_SPI_FLASH=y
|
+CONFIG_SF_DEFAULT_SPEED=40000000
|
+CONFIG_SPI_FLASH_STMICRO=y
|
+CONFIG_PHYLIB=y
|
+CONFIG_PHY_SMCS=y
|
+CONFIG_DM_ETH_PHY=y
|
+CONFIG_FEC_MXC=y
|
+CONFIG_MII=y
|
+CONFIG_PINCTRL=y
|
+CONFIG_PINCTRL_IMX6=y
|
+CONFIG_DM_REGULATOR=y
|
+CONFIG_DM_REGULATOR_FIXED=y
|
+CONFIG_DM_REGULATOR_GPIO=y
|
+CONFIG_DM_RNG=y
|
+CONFIG_DM_SERIAL=y
|
+CONFIG_MXC_UART=y
|
+CONFIG_SPI=y
|
+CONFIG_DM_SPI=y
|
+CONFIG_FSL_QSPI=y
|
+CONFIG_SOFT_SPI=y
|
+CONFIG_IMX_THERMAL=y
|
+CONFIG_USB=y
|
+CONFIG_USB_MAX_CONTROLLER_COUNT=2
|
+CONFIG_USB_STORAGE=y
|
+CONFIG_CMD_USB_MASS_STORAGE=y
|
+CONFIG_USB_HOST_ETHER=y
|
+CONFIG_USB_ETHER_ASIX=y
|
+CONFIG_VIDEO=y
|
+CONFIG_VIDEO_LINK=y
|
+CONFIG_VIDEO_LOGO=y
|
+CONFIG_SYS_WHITE_ON_BLACK=y
|
+CONFIG_VIDEO_MXS=y
|
+CONFIG_SPLASH_SCREEN=y
|
+CONFIG_SPLASH_SCREEN_ALIGN=y
|
+CONFIG_BMP_16BPP=y
|
+
|
+CONFIG_USB_GADGET=y
|
+CONFIG_USB_GADGET_DOWNLOAD=y
|
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
|
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
|
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
|
+CONFIG_CI_UDC=y
|
+
|
+CONFIG_CMD_FASTBOOT=y
|
+CONFIG_USB_FUNCTION_FASTBOOT=y
|
+CONFIG_FASTBOOT_UUU_SUPPORT=y
|
+CONFIG_FASTBOOT=y
|
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
|
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
|
+CONFIG_FASTBOOT_FLASH=y
|
+CONFIG_EFI_PARTITION=y
|
+CONFIG_CMD_CRC32=y
|
+CONFIG_CRC32_VERIFY=y
|
diff --git a/configs/alientek-imx6ull-v24_defconfig b/configs/alientek-imx6ull-v24_defconfig
|
new file mode 100644
|
index 00000000..79128a1d
|
--- /dev/null
|
+++ b/configs/alientek-imx6ull-v24_defconfig
|
@@ -0,0 +1,114 @@
|
+CONFIG_ARM=y
|
+CONFIG_ARCH_MX6=y
|
+CONFIG_SYS_MALLOC_LEN=0x1000000
|
+CONFIG_NR_DRAM_BANKS=1
|
+CONFIG_SYS_MEMTEST_START=0x80000000
|
+CONFIG_SYS_MEMTEST_END=0x88000000
|
+CONFIG_ENV_SIZE=0x2000
|
+CONFIG_ENV_OFFSET=0xE0000
|
+CONFIG_MX6ULL=y
|
+CONFIG_TARGET_ALIENTEK_IMX6ULL=y
|
+# CONFIG_LDO_BYPASS_CHECK is not set
|
+CONFIG_SYS_I2C_MXC_I2C1=y
|
+CONFIG_SYS_I2C_MXC_I2C2=y
|
+CONFIG_DM_GPIO=y
|
+CONFIG_DEFAULT_DEVICE_TREE="alientek-imx6ull-v24"
|
+CONFIG_SUPPORT_RAW_INITRD=y
|
+CONFIG_USE_BOOTCOMMAND=y
|
+CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi"
|
+CONFIG_ARCH_MISC_INIT=y
|
+CONFIG_BOOTDELAY=3
|
+# CONFIG_CONSOLE_MUX is not set
|
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
+CONFIG_BOARD_EARLY_INIT_F=y
|
+CONFIG_HUSH_PARSER=y
|
+CONFIG_SYS_MAXARGS=32
|
+CONFIG_SYS_PBSIZE=532
|
+CONFIG_CMD_BOOTZ=y
|
+# CONFIG_CMD_IMLS is not set
|
+CONFIG_CMD_MEMTEST=y
|
+CONFIG_CMD_GPIO=y
|
+CONFIG_CMD_I2C=y
|
+CONFIG_CMD_MMC=y
|
+CONFIG_CMD_SF=y
|
+CONFIG_CMD_USB=y
|
+CONFIG_CMD_DHCP=y
|
+CONFIG_CMD_PING=y
|
+CONFIG_CMD_BMP=y
|
+CONFIG_CMD_CACHE=y
|
+CONFIG_CMD_RNG=y
|
+CONFIG_CMD_NET=y
|
+CONFIG_CMD_EXT2=y
|
+CONFIG_CMD_EXT4=y
|
+CONFIG_CMD_EXT4_WRITE=y
|
+CONFIG_CMD_FAT=y
|
+CONFIG_CMD_FS_GENERIC=y
|
+CONFIG_OF_CONTROL=y
|
+CONFIG_ENV_OVERWRITE=y
|
+CONFIG_ENV_IS_IN_MMC=y
|
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
+CONFIG_SYS_MMC_ENV_DEV=1
|
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
+CONFIG_USE_ETHPRIME=y
|
+CONFIG_ETHPRIME="eth1"
|
+CONFIG_BOUNCE_BUFFER=y
|
+CONFIG_FSL_DCP_RNG=y
|
+CONFIG_DM_74X164=y
|
+CONFIG_DM_I2C=y
|
+CONFIG_SYS_I2C_MXC=y
|
+CONFIG_FSL_USDHC=y
|
+CONFIG_MTD=y
|
+CONFIG_DM_SPI_FLASH=y
|
+CONFIG_SF_DEFAULT_SPEED=40000000
|
+CONFIG_SPI_FLASH_STMICRO=y
|
+CONFIG_PHYLIB=y
|
+CONFIG_PHY_MICREL=y
|
+CONFIG_PHY_MICREL_KSZ8XXX=y
|
+CONFIG_DM_ETH_PHY=y
|
+CONFIG_FEC_MXC=y
|
+CONFIG_MII=y
|
+CONFIG_PINCTRL=y
|
+CONFIG_PINCTRL_IMX6=y
|
+CONFIG_DM_REGULATOR=y
|
+CONFIG_DM_REGULATOR_FIXED=y
|
+CONFIG_DM_REGULATOR_GPIO=y
|
+CONFIG_DM_RNG=y
|
+CONFIG_DM_SERIAL=y
|
+CONFIG_MXC_UART=y
|
+CONFIG_SPI=y
|
+CONFIG_DM_SPI=y
|
+CONFIG_FSL_QSPI=y
|
+CONFIG_SOFT_SPI=y
|
+CONFIG_IMX_THERMAL=y
|
+CONFIG_USB=y
|
+CONFIG_USB_MAX_CONTROLLER_COUNT=2
|
+CONFIG_USB_STORAGE=y
|
+CONFIG_CMD_USB_MASS_STORAGE=y
|
+CONFIG_USB_HOST_ETHER=y
|
+CONFIG_USB_ETHER_ASIX=y
|
+CONFIG_VIDEO=y
|
+CONFIG_VIDEO_LINK=y
|
+CONFIG_VIDEO_LOGO=y
|
+CONFIG_SYS_WHITE_ON_BLACK=y
|
+CONFIG_VIDEO_MXS=y
|
+CONFIG_SPLASH_SCREEN=y
|
+CONFIG_SPLASH_SCREEN_ALIGN=y
|
+CONFIG_BMP_16BPP=y
|
+
|
+CONFIG_USB_GADGET=y
|
+CONFIG_USB_GADGET_DOWNLOAD=y
|
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
|
+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
|
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
|
+CONFIG_CI_UDC=y
|
+
|
+CONFIG_CMD_FASTBOOT=y
|
+CONFIG_USB_FUNCTION_FASTBOOT=y
|
+CONFIG_FASTBOOT_UUU_SUPPORT=y
|
+CONFIG_FASTBOOT=y
|
+CONFIG_FASTBOOT_BUF_ADDR=0x83800000
|
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
|
+CONFIG_FASTBOOT_FLASH=y
|
+CONFIG_EFI_PARTITION=y
|
+CONFIG_CMD_CRC32=y
|
+CONFIG_CRC32_VERIFY=y
|
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
|
index 50e15cd3..be7bf91c 100644
|
--- a/drivers/net/phy/phy.c
|
+++ b/drivers/net/phy/phy.c
|
@@ -182,6 +182,8 @@ int genphy_config_aneg(struct phy_device *phydev)
|
{
|
int result;
|
|
+ phy_reset(phydev);
|
+
|
if (phydev->autoneg != AUTONEG_ENABLE)
|
return genphy_setup_forced(phydev);
|
|
diff --git a/include/configs/alientek-imx6ull.h b/include/configs/alientek-imx6ull.h
|
new file mode 100644
|
index 00000000..c27fef3f
|
--- /dev/null
|
+++ b/include/configs/alientek-imx6ull.h
|
@@ -0,0 +1,204 @@
|
+/* SPDX-License-Identifier: GPL-2.0+ */
|
+/*
|
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
|
+ * Copyright 2017 NXP
|
+ *
|
+ * Configuration settings for the Freescale i.MX6UL 14x14 EVK board.
|
+ */
|
+#ifndef __ALIENTEK_IMX6ULL_CONFIG_H
|
+#define __ALIENTEK_IMX6ULL_CONFIG_H
|
+
|
+#ifdef CONFIG_CMD_NET
|
+#define CONFIG_FEC_ENET_DEV 1
|
+#endif
|
+
|
+#include <asm/arch/imx-regs.h>
|
+#include <linux/sizes.h>
|
+#include <linux/stringify.h>
|
+#include "mx6_common.h"
|
+#include <asm/mach-imx/gpio.h>
|
+#include "imx_env.h"
|
+
|
+#define is_mx6ull_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6ULL_9X9_EVK)
|
+
|
+#ifdef CONFIG_TARGET_MX6ULL_9X9_EVK
|
+#define BOOTARGS_CMA_SIZE "cma=96M "
|
+#else
|
+#define BOOTARGS_CMA_SIZE ""
|
+#endif
|
+
|
+#define CFG_MXC_UART_BASE UART1_BASE
|
+
|
+/* MMC Configs */
|
+#ifdef CONFIG_FSL_USDHC
|
+#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
|
+
|
+/* NAND pin conflicts with usdhc2 */
|
+#ifdef CONFIG_NAND_MXS
|
+#define CONFIG_SYS_FSL_USDHC_NUM 1
|
+#else
|
+#define CONFIG_SYS_FSL_USDHC_NUM 2
|
+#endif
|
+#endif
|
+
|
+#ifdef CONFIG_NAND_BOOT
|
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs)"
|
+#else
|
+#define MFG_NAND_PARTITION ""
|
+#endif
|
+
|
+#define CFG_MFG_ENV_SETTINGS \
|
+ CFG_MFG_ENV_SETTINGS_DEFAULT \
|
+ "initrd_addr=0x86800000\0" \
|
+ "initrd_high=0xffffffff\0" \
|
+ "emmc_dev=1\0"\
|
+ "emmc_ack=1\0"\
|
+ "sd_dev=1\0" \
|
+ "mtdparts=" MFG_NAND_PARTITION \
|
+ "\0"\
|
+
|
+#if defined(CONFIG_NAND_BOOT)
|
+#define CFG_EXTRA_ENV_SETTINGS \
|
+ CFG_MFG_ENV_SETTINGS \
|
+ TEE_ENV \
|
+ "splashimage=0x8c000000\0" \
|
+ "fdt_addr=0x83000000\0" \
|
+ "fdt_high=0xffffffff\0" \
|
+ "tee_addr=0x84000000\0" \
|
+ "console=ttymxc0\0" \
|
+ "bootargs=console=ttymxc0,115200 ubi.mtd=nandrootfs " \
|
+ "root=ubi0:rootfs rootfstype=ubifs " \
|
+ BOOTARGS_CMA_SIZE \
|
+ MFG_NAND_PARTITION \
|
+ "\0" \
|
+ "bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\
|
+ "nand read ${fdt_addr} 0x5000000 0x100000;"\
|
+ "if test ${tee} = yes; then " \
|
+ "nand read ${tee_addr} 0x6000000 0x400000;"\
|
+ "bootm ${tee_addr} - ${fdt_addr};" \
|
+ "else " \
|
+ "bootz ${loadaddr} - ${fdt_addr};" \
|
+ "fi\0"
|
+
|
+#else
|
+#define CFG_EXTRA_ENV_SETTINGS \
|
+ CFG_MFG_ENV_SETTINGS \
|
+ TEE_ENV \
|
+ "script=boot.scr\0" \
|
+ "image=zImage\0" \
|
+ "console=ttymxc0\0" \
|
+ "fdt_high=0xffffffff\0" \
|
+ "initrd_high=0xffffffff\0" \
|
+ "fdt_file=undefined\0" \
|
+ "fdt_addr=0x83000000\0" \
|
+ "tee_addr=0x84000000\0" \
|
+ "tee_file=undefined\0" \
|
+ "boot_fdt=try\0" \
|
+ "ip_dyn=yes\0" \
|
+ "splashimage=0x8c000000\0" \
|
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
+ "mmcpart=1\0" \
|
+ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
|
+ "mmcautodetect=yes\0" \
|
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
|
+ BOOTARGS_CMA_SIZE \
|
+ "root=${mmcroot}\0" \
|
+ "loadbootscript=" \
|
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
+ "bootscript=echo Running bootscript from mmc ...; " \
|
+ "source\0" \
|
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
+ "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \
|
+ "mmcboot=echo Booting from mmc ...; " \
|
+ "run mmcargs; " \
|
+ "if test ${tee} = yes; then " \
|
+ "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \
|
+ "else " \
|
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
+ "if run loadfdt; then " \
|
+ "bootz ${loadaddr} - ${fdt_addr}; " \
|
+ "else " \
|
+ "if test ${boot_fdt} = try; then " \
|
+ "bootz; " \
|
+ "else " \
|
+ "echo WARN: Cannot load the DT; " \
|
+ "fi; " \
|
+ "fi; " \
|
+ "else " \
|
+ "bootz; " \
|
+ "fi; " \
|
+ "fi;\0" \
|
+ "netargs=setenv bootargs console=${console},${baudrate} " \
|
+ BOOTARGS_CMA_SIZE \
|
+ "root=/dev/nfs " \
|
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
+ "netboot=echo Booting from net ...; " \
|
+ "${usb_net_cmd}; " \
|
+ "run netargs; " \
|
+ "if test ${ip_dyn} = yes; then " \
|
+ "setenv get_cmd dhcp; " \
|
+ "else " \
|
+ "setenv get_cmd tftp; " \
|
+ "fi; " \
|
+ "${get_cmd} ${image}; " \
|
+ "if test ${tee} = yes; then " \
|
+ "${get_cmd} ${tee_addr} ${tee_file}; " \
|
+ "${get_cmd} ${fdt_addr} ${fdt_file}; " \
|
+ "bootm ${tee_addr} - ${fdt_addr}; " \
|
+ "else " \
|
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
+ "bootz ${loadaddr} - ${fdt_addr}; " \
|
+ "else " \
|
+ "if test ${boot_fdt} = try; then " \
|
+ "bootz; " \
|
+ "else " \
|
+ "echo WARN: Cannot load the DT; " \
|
+ "fi; " \
|
+ "fi; " \
|
+ "else " \
|
+ "bootz; " \
|
+ "fi; " \
|
+ "fi;\0" \
|
+ "findfdt="\
|
+ "if test $fdt_file = undefined; then " \
|
+ "if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \
|
+ "setenv fdt_file imx6ulz-14x14-evk.dtb; fi; " \
|
+ "if test $board_name = EVK && test $board_rev = 9X9; then " \
|
+ "setenv fdt_file imx6ull-9x9-evk.dtb; fi; " \
|
+ "if test $board_name = EVK && test $board_rev = 14X14; then " \
|
+ "setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \
|
+ "if test $fdt_file = undefined; then " \
|
+ "echo WARNING: Could not determine dtb to use; " \
|
+ "fi; " \
|
+ "fi;\0" \
|
+ "findtee="\
|
+ "if test $tee_file = undefined; then " \
|
+ "if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \
|
+ "setenv tee_file uTee-6ulzevk; fi; " \
|
+ "if test $board_name = EVK && test $board_rev = 9X9; then " \
|
+ "setenv tee_file uTee-6ullevk; fi; " \
|
+ "if test $board_name = EVK && test $board_rev = 14X14; then " \
|
+ "setenv tee_file uTee-6ullevk; fi; " \
|
+ "if test $tee_file = undefined; then " \
|
+ "echo WARNING: Could not determine tee to use; " \
|
+ "fi; " \
|
+ "fi;\0" \
|
+
|
+#endif
|
+
|
+/* Miscellaneous configurable options */
|
+
|
+/* Physical Memory Map */
|
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
+
|
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM
|
+#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
+#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
+
|
+/* environment organization */
|
+
|
+/* NAND stuff */
|
+#define CFG_SYS_NAND_BASE 0x40000000
|
+#endif
|
