/*********************************************************************************
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* Copyright: (C) 2023 LingYun IoT System Studio. All Rights Reserved.
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* Author: Guo Wenxue <guowenxue@gmail.com>
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*
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* Description: This file is W25Qxx SPI Norflash driver on RaspberryPi 40Pin.
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*
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* W25QXX RaspberryPi 40Pin
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* VCC <---> 3.3V(Pin#1)
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* CS <---> CS(Pin#24)
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* DO <---> MISO(Pin#21)
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* GND <---> GND(Pin#9)
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* CLK <---> SCLK(Pin#23)
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* DI <---> MOSI(Pin#19)
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*
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********************************************************************************/
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#ifndef _W25QFLASH_H
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#define _W25QFLASH_H
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#include <stdbool.h>
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#define _W25QXX_DEBUG 1
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/* Flash opcodes. Refer to <<W25Q256JV.pdf>> P26 Table 8.1.2 Instruction Set Table */
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#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
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#define SPINOR_OP_RDUID 0x4b /* Read unique ID */
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#define SPINOR_OP_WRSR1 0x01 /* Write status register-1 */
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#define SPINOR_OP_WRSR2 0x31 /* Write status register-2 */
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#define SPINOR_OP_WRSR3 0x11 /* Write status register-3 */
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#define SPINOR_OP_BP 0x02 /* Byte program */
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#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
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#define SPINOR_OP_WRDI 0x04 /* Write disable */
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#define SPINOR_OP_RDSR1 0x05 /* Read status register-1 */
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#define SPINOR_OP_RDSR2 0x35 /* Read status register-2 */
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#define SPINOR_OP_RDSR3 0x15 /* Read status register-3 */
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#define SPINOR_OP_WREN 0x06 /* Write enable */
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#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
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#define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
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#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
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#define SPINOR_OP_BE_4K_4B 0xdc /* Block erase (64KiB) with 4-Byte Address */
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#define SPINOR_OP_BE_4K 0xd8 /* Block erase (64KiB) */
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#define SPINOR_OP_SE_4B 0x21 /* Sector erase (4KiB) with 4-Byte Address */
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#define SPINOR_OP_SE 0x20 /* Sector erase (4KiB) */
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#define SPINOR_OP_PP_4B 0x12 /* Page Program (up to 256 bytes) with 4-Byte Address */
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#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
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#define SPINOR_OP_SRSTEN 0x66 /* Software Reset Enable */
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#define SPINOR_OP_SRST 0x99 /* Software Reset */
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typedef struct spi_info
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{
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int hspi; /* SPI device description */
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void (*select)(struct spi_info *spi); /* CS enable function */
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void (*deselect)(struct spi_info *spi); /* CS disable function */
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void (*xcmd)(struct spi_info *spi, uint8_t command); /* Send a byte command */
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void (*xfer)(struct spi_info *spi, uint8_t *send_buf, uint8_t *recv_buf, int bytes); /* Transmit and Receive N byte */
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} spi_info_t;
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typedef struct flash_info
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{
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char *name; /* Chip name */
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uint32_t jedec_id; /* JEDEC ID, 3 bytes */
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uint64_t capacity; /* Chip size in bytes */
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uint32_t block_size; /* Block size in bytes */
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uint32_t sector_size; /* Sector size in bytes */
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uint32_t page_size; /* Page size in bytes */
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uint32_t n_blocks; /* Number of blocks */
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uint32_t n_sectors; /* Number of sectors */
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uint32_t n_pages; /* Number of pages */
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} flash_info_t;
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typedef struct spinor_info
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{
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spi_info_t *spi;
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flash_info_t *flash;
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uint8_t lock;
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} spinor_info_t;
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/* Status registers */
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enum
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{
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REG_STATUS1,
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REG_STATUS2,
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REG_STATUS3,
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REG_STATUS_MAX,
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};
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/*+-------------------------------+
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*| SPI Norflash HighLevel API |
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*+-------------------------------+*/
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/* SPI Norflash API test function */
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extern void spinor_test(void);
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/* Initial SPI and detect the flash chip */
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extern int spinor_init(struct spinor_info *spinor);
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/* Description: Erase whole flash chip.
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* Reference : P60, 8.2.32 Chip Erase (C7h / 60h)
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*/
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extern int spinor_erase_chip(struct spinor_info *spinor);
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/* Description: Erase blocks by 64KiB,
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* Reference : P59, 8.2.31 64KB Block Erase with 4-Byte Address (DCh)
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* @address is the erase start physical address, which can be not block alignment such as 0x10001.
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* @size is the erase size, which can be larger than a block such as 4097, and it will erase 2 blocks;
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*/
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extern int spinor_erase_block(struct spinor_info *spinor, uint32_t address, uint32_t size);
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/* Description: Erase sectors by 4KiB
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* Reference : P56, 8.2.28 Sector Erase with 4-Byte Address (21h)
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* @address is the erase start physical address, which can be not sector alignment such as 0x1001.
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* @size is the erase size, which can be larger than a sector such as 4097, and it will erase 2 sectors;
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*/
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extern int spinor_erase_sector(struct spinor_info *spinor, uint32_t address, uint32_t size);
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/* Description: Page random write by 256B
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* @addr is the write start physical address, which can be not page alignment such as 0x101.
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* @size is the write size, which can be larger than a page such as 257, and it will write 2 pages;
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*/
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extern int spinor_write(struct spinor_info *spinor, uint32_t address, uint8_t *data, uint32_t bytes);
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/* Description: The Fast Read instruction can read the entire memory chip.
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* Reference : P41, 8.2.13 Fast Read with 4-Byte Address (0Ch)
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* @address is the read start physical address, which can be not page alignment such as 0x101.
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* @size is the read size, which can be larger than a page such as 257, and it will read 2 pages;
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*/
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extern int spinor_read(struct spinor_info *spinor, uint32_t address, uint8_t *buf, uint32_t bytes);
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/*+-------------------------------+
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*| SPI Norflash LowLevel API |
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*+-------------------------------+*/
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/* Detect the norflash by JEDEC ID */
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int spinor_detect_by_jedec(struct spinor_info *spinor);
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/* Description: Read the chipset UNIQUE ID.
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* Reference : P68, 8.2.40 Read Unique ID Number (4Bh)
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*/
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int spinor_read_uniqid(struct spi_info *spi, uint8_t *uniq_id);
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/* Description: Read the chipset JEDEC ID.
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* Reference : P69, 8.2.41 Read JEDEC ID (9Fh)
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*/
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uint32_t spinor_read_jedecid(struct spi_info *spi);
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/* Description: Write Enable
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* Reference : P31, 8.2.1 Write Enable (06h)
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*/
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void spinor_write_enable(struct spi_info *spi);
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/* Description: Write Disable
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* Reference : P32, 8.2.3 Write Disable (04h)
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*/
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void spinor_write_disable(struct spi_info *spi);
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/* Description: Read Status Register
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* Reference : P32, 8.2.4 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h)
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*/
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uint8_t spinor_read_status_reg(struct spi_info *spi, uint8_t reg);
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/* Description: Write Status Register
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* Reference : P33, 8.2.5 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h)
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*/
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void spinor_write_status_reg(struct spi_info *spi, uint8_t reg, uint8_t value);
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/* Description: Wait flash program/erase finished by read Status Register for BUSY bit
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* Reference : P15, 7.1 Status Registers
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*/
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void spinor_WaitForWriteEnd(struct spi_info *spi);
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#endif
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