build-imxboard.git

			@@ -24,10 +24,10 @@
			imx8mm-ddr4-ab2.dtb \
			diff --git a/arch/arm/dts/igkboard-imx8mp-u-boot.dtsi b/arch/arm/dts/igkboard-imx8mp-u-boot.dtsi
			new file mode 100644
			index 00000000..202e5307
			index 00000000..b69049bb
			--- /dev/null
			+++ b/arch/arm/dts/igkboard-imx8mp-u-boot.dtsi
			@@ -0,0 +1,74 @@
			@@ -0,0 +1,86 @@
			+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
			+/*
			+ * Copy from imx8mp-venice-u-boot.dtsi
			@@ -102,12 +102,24 @@
			+&pinctrl_wdog {
			+ u-boot,dm-spl;
			+};
			+
			+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25} {
			+ u-boot,dm-spl;
			+};
			+
			+&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
			+ u-boot,dm-spl;
			+};
			+
			+&pinctrl_pmic {
			+ u-boot,dm-spl;
			+};
			diff --git a/arch/arm/dts/igkboard-imx8mp.dts b/arch/arm/dts/igkboard-imx8mp.dts
			new file mode 100644
			index 00000000..a21acb92
			index 00000000..cddc9470
			--- /dev/null
			+++ b/arch/arm/dts/igkboard-imx8mp.dts
			@@ -0,0 +1,486 @@
			@@ -0,0 +1,475 @@
			+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
			+/*
			+ * Copyright 2023 LingYun IoT System Studio.
			@@ -125,41 +137,30 @@
			+ model = "LingYun IoT Gateway Kits Board based on i.MX8MP";
			+ compatible = "lingyun,igkboard-imx8mp", "fsl,imx8mp";
			+
			+ /* console and bootargs */
			+ chosen {
			+ bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
			+ stdout-path = &uart2;
			+ };
			+ /* console and bootargs */
			+ chosen {
			+ bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
			+ stdout-path = &uart2;
			+ };
			+
			+ /* MT53D512M32D2DS-053 WT:D, 8GB LPDDR4 */
			+ /* MT53D512M32D2DS-053 WT:D, 2GB LPDDR4 */
			+ memory@80000000 {
			+ device_type = "memory";
			+ reg = <0x0 0x80000000 0 0x80000000>;
			+ };
			+
			+ /* SD2_RESET_B for TF card */
			+ reg_usdhc2_vmmc: regulator-usdhc2 {
			+ compatible = "regulator-fixed";
			+ regulator-name = "VSD_3V3";
			+ regulator-min-microvolt = <3300000>;
			+ regulator-max-microvolt = <3300000>;
			+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
			+ enable-active-high;
			+ startup-delay-us = <100>;
			+ off-on-delay-us = <12000>;
			+ };
			+ };
			+
			+ leds {
			+ compatible = "gpio-leds";
			+ pinctrl-names = "default";
			+ pinctrl-0 = <&pinctrl_gpio_led>;
			+ pinctrl-0 = <&pinctrl_leds>;
			+ status = "okay";
			+
			+ sysled {
			+ label = "sysled";
			+ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
			+ default-state = "on";
			+ };
			+ };
			+ };
			+ };
			+};
			+
			+/*+------------------------+
			@@ -206,15 +207,14 @@
			+ +------------------------+*/
			+
			+&usdhc2 {
			+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
			+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
			+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
			+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
			+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
			+ vmmc-supply = <&reg_usdhc2_vmmc>;
			+ bus-width = <4>;
			+ no-1-8-v;
			+ status = "okay";
			+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
			+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
			+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
			+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
			+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
			+ bus-width = <4>;
			+ no-1-8-v;
			+ status = "okay";
			+};
			+
			+/*+------------------------+
			@@ -222,25 +222,25 @@
			+ +------------------------+*/
			+
			+&usb3_phy0 {
			+ fsl,phy-tx-vref-tune = <6>;
			+ fsl,phy-tx-rise-tune = <0>;
			+ fsl,phy-tx-preemp-amp-tune = <3>;
			+ fsl,phy-comp-dis-tune = <7>;
			+ fsl,pcs-tx-deemph-3p5db = <0x21>;
			+ fsl,phy-pcs-tx-swing-full = <0x7f>;
			+ status = "okay";
			+ fsl,phy-tx-vref-tune = <6>;
			+ fsl,phy-tx-rise-tune = <0>;
			+ fsl,phy-tx-preemp-amp-tune = <3>;
			+ fsl,phy-comp-dis-tune = <7>;
			+ fsl,pcs-tx-deemph-3p5db = <0x21>;
			+ fsl,phy-pcs-tx-swing-full = <0x7f>;
			+ status = "okay";
			+};
			+
			+&usb3_0 {
			+ status = "okay";
			+ status = "okay";
			+};
			+
			+&usb_dwc3_0 {
			+ dr_mode = "peripheral";
			+ hnp-disable;
			+ srp-disable;
			+ adp-disable;
			+ status = "okay";
			+ dr_mode = "peripheral";
			+ hnp-disable;
			+ srp-disable;
			+ adp-disable;
			+ status = "okay";
			+};
			+
			+/*+------------------------+
			@@ -249,67 +249,69 @@
			+
			+/* Renesas USB 3.0 Hub uPD720210 */
			+&usb3_phy1 {
			+ fsl,phy-tx-preemp-amp-tune = <2>;
			+ status = "okay";
			+ fsl,phy-tx-preemp-amp-tune = <2>;
			+ status = "okay";
			+};
			+
			+&usb3_1 {
			+ status = "okay";
			+ status = "okay";
			+};
			+
			+&usb_dwc3_1 {
			+ dr_mode = "host";
			+ status = "okay";
			+ dr_mode = "host";
			+ status = "okay";
			+};
			+
			+/*+------------------------+
			+ \| Ethernet \|
			+ +------------------------+*/
			+
			+/* First 1000Mbps Ethernet For TSN on ENET */
			+&eqos {
			+ pinctrl-names = "default";
			+ pinctrl-0 = <&pinctrl_eqos>;
			+ phy-mode = "rgmii-id";
			+ phy-handle = <&ethphy0>;
			+ snps,reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
			+ snps,reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
			+ snps,reset-delays-us = <100000 200000 150000>;
			+ status = "okay";
			+
			+ mdio {
			+ compatible = "snps,dwmac-mdio";
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ ethphy0: ethernet-phy@1 {
			+ ethphy0: ethernet-phy@0 { /* YT8521SH-CA */
			+ compatible = "ethernet-phy-ieee802.3-c22";
			+ reg = <0>;
			+ reg = <0>;
			+ eee-broken-1000t;
			+ };
			+ };
			+ };
			+ };
			+};
			+
			+/* Second 1000Mbps Ethernet on ENET1 */
			+&fec {
			+ pinctrl-names = "default";
			+ pinctrl-0 = <&pinctrl_fec>;
			+ phy-mode = "rgmii-id";
			+ phy-handle = <&ethphy1>;
			+ phy-reset-duration = <200>;
			+ phy-reset-post-delay = <150>;
			+ phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
			+
			+ phy-reset-duration = <200>;
			+ phy-reset-post-delay = <150>;
			+ phy-reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
			+
			+ fsl,magic-packet;
			+ status = "okay";
			+
			+ mdio {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+
			+ ethphy1: ethernet-phy@1 {
			+ ethphy1: ethernet-phy@0 { /* YT8521SH-CA */
			+ compatible = "ethernet-phy-ieee802.3-c22";
			+ reg = <0>;
			+ reg = <0>;
			+ eee-broken-1000t;
			+ };
			+ };
			+ };
			+ };
			+};
			+
			+/*+------------------------+
			@@ -317,282 +319,281 @@
			+ +------------------------+*/
			+
			+&i2c1 {
			+ clock-frequency = <400000>;
			+ pinctrl-names = "default", "gpio";
			+ pinctrl-0 = <&pinctrl_i2c1>;
			+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
			+ scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
			+ sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
			+ status = "okay";
			+ clock-frequency = <400000>;
			+ pinctrl-names = "default", "gpio";
			+ pinctrl-0 = <&pinctrl_i2c1>;
			+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
			+ scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
			+ sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
			+ status = "okay";
			+
			+ pmic@25 {
			+ compatible = "nxp,pca9450c";
			+ reg = <0x25>;
			+ pinctrl-names = "default";
			+ pinctrl-0 = <&pinctrl_pmic>;
			+ interrupt-parent = <&gpio1>;
			+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
			+ pmic@25 {
			+ compatible = "nxp,pca9450c";
			+ reg = <0x25>;
			+ pinctrl-names = "default";
			+ pinctrl-0 = <&pinctrl_pmic>;
			+ interrupt-parent = <&gpio1>;
			+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
			+
			+ regulators {
			+ buck1: BUCK1 {
			+ regulator-name = "BUCK1";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <2187500>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ regulator-ramp-delay = <3125>;
			+ };
			+ regulators {
			+ buck1: BUCK1 {
			+ regulator-name = "BUCK1";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <2187500>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ regulator-ramp-delay = <3125>;
			+ };
			+
			+ buck2: BUCK2 {
			+ regulator-name = "BUCK2";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <2187500>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ regulator-ramp-delay = <3125>;
			+ nxp,dvs-run-voltage = <950000>;
			+ nxp,dvs-standby-voltage = <850000>;
			+ };
			+ buck2: BUCK2 {
			+ regulator-name = "BUCK2";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <2187500>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ regulator-ramp-delay = <3125>;
			+ nxp,dvs-run-voltage = <950000>;
			+ nxp,dvs-standby-voltage = <850000>;
			+ };
			+
			+ buck4: BUCK4{
			+ regulator-name = "BUCK4";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <3400000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ buck4: BUCK4{
			+ regulator-name = "BUCK4";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <3400000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+
			+ buck5: BUCK5{
			+ regulator-name = "BUCK5";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <3400000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ buck5: BUCK5{
			+ regulator-name = "BUCK5";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <3400000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+
			+ buck6: BUCK6 {
			+ regulator-name = "BUCK6";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <3400000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ buck6: BUCK6 {
			+ regulator-name = "BUCK6";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <3400000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+
			+ ldo1: LDO1 {
			+ regulator-name = "LDO1";
			+ regulator-min-microvolt = <1600000>;
			+ regulator-max-microvolt = <3300000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ ldo1: LDO1 {
			+ regulator-name = "LDO1";
			+ regulator-min-microvolt = <1600000>;
			+ regulator-max-microvolt = <3300000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+
			+ ldo2: LDO2 {
			+ regulator-name = "LDO2";
			+ regulator-min-microvolt = <800000>;
			+ regulator-max-microvolt = <1150000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ ldo2: LDO2 {
			+ regulator-name = "LDO2";
			+ regulator-min-microvolt = <800000>;
			+ regulator-max-microvolt = <1150000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+
			+ ldo3: LDO3 {
			+ regulator-name = "LDO3";
			+ regulator-min-microvolt = <800000>;
			+ regulator-max-microvolt = <3300000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ ldo3: LDO3 {
			+ regulator-name = "LDO3";
			+ regulator-min-microvolt = <800000>;
			+ regulator-max-microvolt = <3300000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+
			+ ldo4: LDO4 {
			+ regulator-name = "LDO4";
			+ regulator-min-microvolt = <800000>;
			+ regulator-max-microvolt = <3300000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ ldo4: LDO4 {
			+ regulator-name = "LDO4";
			+ regulator-min-microvolt = <800000>;
			+ regulator-max-microvolt = <3300000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+
			+ ldo5: LDO5 {
			+ regulator-name = "LDO5";
			+ regulator-min-microvolt = <1800000>;
			+ regulator-max-microvolt = <3300000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ };
			+ };
			+ ldo5: LDO5 {
			+ regulator-name = "LDO5";
			+ regulator-min-microvolt = <1800000>;
			+ regulator-max-microvolt = <3300000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ };
			+ };
			+};
			+
			+&iomuxc {
			+ pinctrl-names = "default";
			+ pinctrl-names = "default";
			+
			+ pinctrl_gpio_led: gpioledgrp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
			+ >;
			+ };
			+ pinctrl_leds: ledsgrp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
			+ >;
			+ };
			+
			+ pinctrl_uart2: uart2grp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
			+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
			+ >;
			+ };
			+ pinctrl_wdog: wdoggrp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
			+ >;
			+ };
			+
			+ pinctrl_i2c1: i2c1grp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
			+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
			+ >;
			+ };
			+ pinctrl_uart2: uart2grp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
			+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
			+ >;
			+ };
			+
			+ pinctrl_i2c1_gpio: i2c1grp-gpio {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
			+ MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
			+ >;
			+ };
			+ pinctrl_i2c1: i2c1grp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
			+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
			+ >;
			+ };
			+
			+ pinctrl_pmic: pmicirq {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
			+ >;
			+ };
			+ pinctrl_i2c1_gpio: i2c1grp-gpio {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
			+ MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
			+ >;
			+ };
			+
			+ pinctrl_usdhc2: usdhc2grp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
			+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
			+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
			+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
			+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
			+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
			+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
			+ >;
			+ };
			+ pinctrl_pmic: pmicirq {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
			+ >;
			+ };
			+
			+ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
			+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
			+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
			+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
			+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
			+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
			+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
			+ >;
			+ };
			+ pinctrl_usdhc2_gpio: usdhc2grp-gpio {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
			+ >;
			+ };
			+
			+ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
			+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
			+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
			+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
			+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
			+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
			+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
			+ >;
			+ };
			+ pinctrl_usdhc2: usdhc2grp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
			+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
			+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
			+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
			+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
			+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
			+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
			+ >;
			+ };
			+
			+ pinctrl_usdhc2_gpio: usdhc2grp-gpio {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
			+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
			+ >;
			+ };
			+ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
			+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
			+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
			+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
			+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
			+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
			+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
			+ >;
			+ };
			+
			+ pinctrl_usdhc3: usdhc3grp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
			+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
			+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
			+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
			+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
			+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
			+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
			+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
			+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
			+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
			+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
			+ >;
			+ };
			+ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
			+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
			+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
			+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
			+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
			+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
			+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
			+ >;
			+ };
			+
			+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
			+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
			+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
			+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
			+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
			+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
			+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
			+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
			+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
			+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
			+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
			+ >;
			+ };
			+ pinctrl_usdhc3: usdhc3grp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
			+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
			+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
			+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
			+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
			+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
			+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
			+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
			+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
			+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
			+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
			+ >;
			+ };
			+
			+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
			+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
			+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
			+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
			+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
			+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
			+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
			+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
			+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
			+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
			+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
			+ >;
			+ };
			+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
			+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
			+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
			+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
			+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
			+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
			+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
			+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
			+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
			+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
			+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
			+ >;
			+ };
			+
			+ pinctrl_eqos: eqosgrp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
			+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
			+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
			+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
			+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
			+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
			+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
			+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
			+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
			+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
			+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
			+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
			+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
			+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
			+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
			+ >;
			+ };
			+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
			+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
			+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
			+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
			+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
			+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
			+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
			+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
			+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
			+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
			+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
			+ >;
			+ };
			+
			+ pinctrl_fec: fecgrp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
			+ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
			+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
			+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
			+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
			+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
			+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
			+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
			+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
			+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
			+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
			+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
			+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
			+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
			+ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
			+ >;
			+ };
			+ pinctrl_eqos: eqosgrp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
			+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
			+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
			+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
			+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
			+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
			+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
			+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
			+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
			+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
			+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
			+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
			+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
			+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
			+ MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x22
			+ >;
			+ };
			+
			+ pinctrl_wdog: wdoggrp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
			+ >;
			+ };
			+ pinctrl_fec: fecgrp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
			+ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
			+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
			+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
			+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
			+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
			+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
			+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
			+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
			+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
			+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
			+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
			+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
			+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
			+ MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x11
			+ >;
			+ };
			+};
			diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
			index b1240279..e9bcd610 100644
			@@ -3252,10 +3253,10 @@
			+}
			diff --git a/configs/igkboard-imx8mp_defconfig b/configs/igkboard-imx8mp_defconfig
			new file mode 100644
			index 00000000..40c3b634
			index 00000000..b063a6e8
			--- /dev/null
			+++ b/configs/igkboard-imx8mp_defconfig
			@@ -0,0 +1,199 @@
			@@ -0,0 +1,166 @@
			+CONFIG_ARM=y
			+CONFIG_ARCH_IMX8M=y
			+CONFIG_TEXT_BASE=0x40200000
			@@ -3263,34 +3264,33 @@
			+CONFIG_SPL_GPIO=y
			+CONFIG_SPL_LIBCOMMON_SUPPORT=y
			+CONFIG_SPL_LIBGENERIC_SUPPORT=y
			+CONFIG_IMX_BOOTAUX=y
			+CONFIG_NR_DRAM_BANKS=3
			+CONFIG_ENV_SIZE=0x4000
			+CONFIG_ENV_OFFSET=0x700000
			+CONFIG_ENV_SECT_SIZE=0x10000
			+CONFIG_SYS_MEMTEST_START=0x60000000
			+CONFIG_SYS_MEMTEST_END=0xC0000000
			+CONFIG_SYS_I2C_MXC_I2C1=y
			+CONFIG_SYS_I2C_MXC_I2C2=y
			+CONFIG_SYS_I2C_MXC_I2C3=y
			+CONFIG_DM_GPIO=y
			+CONFIG_DEFAULT_DEVICE_TREE="igkboard-imx8mp"
			+CONFIG_SPL_TEXT_BASE=0x920000
			+CONFIG_TARGET_IGKBOARD_IMX8MP=y
			+CONFIG_SYS_PROMPT="u-boot=> "
			+CONFIG_SPL_SERIAL=y
			+CONFIG_SPL_DRIVERS_MISC=y
			+CONFIG_SPL_STACK=0x96dff0
			+CONFIG_SPL=y
			+CONFIG_IMX_BOOTAUX=y
			+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
			+CONFIG_SYS_LOAD_ADDR=0x40400000
			+CONFIG_DISTRO_DEFAULTS=y
			+CONFIG_OF_BOARD_FIXUP=y
			+CONFIG_SYS_MEMTEST_START=0x60000000
			+CONFIG_SYS_MEMTEST_END=0xC0000000
			+CONFIG_REMAKE_ELF=y
			+CONFIG_SYS_MONITOR_LEN=524288
			+CONFIG_DEFAULT_DEVICE_TREE="igkboard-imx8mp"
			+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
			+CONFIG_FIT=y
			+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
			+CONFIG_SPL_LOAD_FIT=y
			+# CONFIG_USE_SPL_FIT_GENERATOR is not set
			+CONFIG_REMAKE_ELF=y
			+CONFIG_OF_BOARD_SETUP=y
			+CONFIG_OF_SYSTEM_SETUP=y
			+CONFIG_DISTRO_DEFAULTS=y
			+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
			+CONFIG_DEFAULT_FDT_FILE="igkboard-imx8mp.dtb"
			+CONFIG_ARCH_MISC_INIT=y
			+CONFIG_BOARD_EARLY_INIT_F=y
			@@ -3302,7 +3302,6 @@
			+CONFIG_SPL_BOARD_INIT=y
			+CONFIG_SPL_BOOTROM_SUPPORT=y
			+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
			+CONFIG_SPL_STACK=0x96dff0
			+CONFIG_SYS_SPL_MALLOC=y
			+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
			+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
			@@ -3315,31 +3314,29 @@
			+CONFIG_SYS_MAXARGS=64
			+CONFIG_SYS_CBSIZE=2048
			+CONFIG_SYS_PBSIZE=2074
			+# CONFIG_BOOTM_NETBSD is not set
			+CONFIG_SYS_BOOTM_LEN=0x2000000
			+CONFIG_NR_DRAM_BANKS=3
			+CONFIG_HUSH_PARSER=y
			+# CONFIG_CMD_EXPORTENV is not set
			+# CONFIG_CMD_IMPORTENV is not set
			+CONFIG_CMD_ERASEENV=y
			+CONFIG_CMD_CRC32=y
			+CONFIG_CRC32_VERIFY=y
			+# CONFIG_BOOTM_NETBSD is not set
			+CONFIG_CMD_MEMTEST=y
			+CONFIG_CMD_CLK=y
			+CONFIG_CMD_FUSE=y
			+CONFIG_CMD_GPIO=y
			+CONFIG_CMD_I2C=y
			+CONFIG_CMD_MMC=y
			+CONFIG_CMD_CACHE=y
			+CONFIG_CMD_REGULATOR=y
			+CONFIG_CMD_MEMTEST=y
			+CONFIG_CMD_EXT2=y
			+CONFIG_CMD_EXT4=y
			+CONFIG_CMD_EXT4_WRITE=y
			+CONFIG_CMD_FAT=y
			+CONFIG_CMD_LED=y
			+CONFIG_CMD_FS_GENERIC=y
			+CONFIG_CMD_NAND_TRIMFFS=y
			+CONFIG_CMD_USB=y
			+CONFIG_CMD_USB_MASS_STORAGE=y
			+CONFIG_CMD_BMP=y
			+CONFIG_CMD_CACHE=y
			+CONFIG_CMD_REGULATOR=y
			+CONFIG_CMD_EXT4_WRITE=y
			+CONFIG_CMD_MTDPARTS=y
			+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
			+CONFIG_MTDPARTS_SKIP_INVALID=y
			+CONFIG_CMD_UBI=y
			+CONFIG_OF_CONTROL=y
			+CONFIG_SPL_OF_CONTROL=y
			+CONFIG_ENV_OVERWRITE=y
			@@ -3348,7 +3345,6 @@
			+CONFIG_ENV_IS_IN_NAND=y
			+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
			+CONFIG_SYS_MMC_ENV_DEV=1
			+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
			+CONFIG_USE_ETHPRIME=y
			+CONFIG_ETHPRIME="eth1"
			+CONFIG_SPL_DM=y
			@@ -3356,43 +3352,44 @@
			+CONFIG_CLK_COMPOSITE_CCF=y
			+CONFIG_SPL_CLK_IMX8MP=y
			+CONFIG_CLK_IMX8MP=y
			+CONFIG_MXC_GPIO=y
			+CONFIG_DM_PCA953X=y
			+CONFIG_FASTBOOT=y
			+CONFIG_USB_FUNCTION_FASTBOOT=y
			+CONFIG_CMD_FASTBOOT=y
			+CONFIG_ANDROID_BOOT_IMAGE=y
			+CONFIG_FASTBOOT_UUU_SUPPORT=y
			+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
			+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
			+CONFIG_FASTBOOT_FLASH=y
			+CONFIG_MXC_GPIO=y
			+CONFIG_DM_PCA953X=y
			+CONFIG_DM_I2C=y
			+CONFIG_SYS_I2C_MXC=y
			+CONFIG_LED=y
			+CONFIG_LED_GPIO=y
			+CONFIG_DM_MMC=y
			+CONFIG_EFI_PARTITION=y
			+CONFIG_SUPPORT_EMMC_BOOT=y
			+CONFIG_MMC_IO_VOLTAGE=y
			+CONFIG_MMC_UHS_SUPPORT=y
			+CONFIG_MMC_HS400_ES_SUPPORT=y
			+CONFIG_MMC_HS400_SUPPORT=y
			+CONFIG_FSL_USDHC=y
			+CONFIG_MTD=y
			+CONFIG_DM_MTD=y
			+CONFIG_MTD_RAW_NAND=y
			+CONFIG_SYS_NAND_USE_FLASH_BBT=y
			+CONFIG_NAND_MXS=y
			+CONFIG_NAND_MXS_DT=y
			+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
			+CONFIG_SYS_NAND_ONFI_DETECTION=y
			+CONFIG_PHY_REALTEK=y
			+CONFIG_DM_ETH_PHY=y
			+CONFIG_PHY_GIGE=y
			+CONFIG_PHY=y
			+CONFIG_PHY_IMX8MQ_USB=y
			+CONFIG_DWC_ETH_QOS=y
			+CONFIG_DWC_ETH_QOS_IMX=y
			+CONFIG_FEC_MXC=y
			+CONFIG_MII=y
			+
			+CONFIG_PHY=y
			+CONFIG_PHY_IMX8MQ_USB=y
			+CONFIG_PINCTRL=y
			+CONFIG_SPL_PINCTRL=y
			+CONFIG_PINCTRL_IMX8M=y
			+CONFIG_POWER_DOMAIN=y
			+CONFIG_IMX8M_POWER_DOMAIN=y
			+CONFIG_IMX8M_BLK_CTRL=y
			+CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
			+CONFIG_DM_PMIC=y
			+CONFIG_SPL_DM_PMIC_PCA9450=y
			@@ -3405,56 +3402,27 @@
			+CONFIG_SYSRESET_PSCI=y
			+CONFIG_DM_THERMAL=y
			+CONFIG_IMX_TMU=y
			+CONFIG_USB_TCPC=n
			+CONFIG_USB=y
			+CONFIG_USB_XHCI_HCD=y
			+CONFIG_USB_XHCI_DWC3=y
			+CONFIG_USB_DWC3=y
			+CONFIG_USB_GADGET=y
			+CONFIG_USB_STORAGE=y
			+CONFIG_DM_USB=y
			+
			+CONFIG_OF_LIBFDT_OVERLAY=y
			+CONFIG_USB_GADGET_MANUFACTURER="FSL"
			+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
			+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
			+CONFIG_USB_GADGET_DOWNLOAD=y
			+CONFIG_USB_XHCI_HCD=y
			+CONFIG_USB_XHCI_IMX8M=y
			+CONFIG_USB_XHCI_DWC3=y
			+CONFIG_USB_DWC3=y
			+CONFIG_USB_DWC3_GADGET=y
			+
			+CONFIG_OF_BOARD_FIXUP=y
			+CONFIG_OF_BOARD_SETUP=y
			+
			+CONFIG_IMX8M_BLK_CTRL=y
			+CONFIG_VIDEO_IMX_LCDIFV3=y
			+CONFIG_VIDEO_IMX_SEC_DSI=y
			+CONFIG_VIDEO=y
			+CONFIG_VIDEO_LOGO=y
			+CONFIG_SYS_WHITE_ON_BLACK=y
			+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
			+CONFIG_VIDEO_IMX_SEC_DSI=y
			+CONFIG_VIDEO_IMX_LCDIFV3=y
			+CONFIG_SPLASH_SCREEN=y
			+CONFIG_SPLASH_SCREEN_ALIGN=y
			+CONFIG_BMP_16BPP=y
			+CONFIG_BMP_24BPP=y
			+CONFIG_BMP_32BPP=y
			+CONFIG_VIDEO_LOGO=y
			+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
			+CONFIG_VIDEO_ADV7535=y
			+CONFIG_SYS_WHITE_ON_BLACK=y
			+CONFIG_SPLASH_SCREEN=y
			+CONFIG_SPLASH_SCREEN_ALIGN=y
			+CONFIG_CMD_BMP=y
			+
			+CONFIG_CMD_NAND=y
			+CONFIG_CMD_UBI=y
			+CONFIG_CMD_NAND_TRIMFFS=y
			+CONFIG_MTD_RAW_NAND=y
			+CONFIG_MTD=y
			+CONFIG_DM_MTD=y
			+CONFIG_CMD_MTDPARTS=y
			+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
			+CONFIG_MTDPARTS_SKIP_INVALID=y
			+CONFIG_NAND=y
			+CONFIG_NAND_MXS=y
			+CONFIG_NAND_MXS_DT=y
			+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
			+CONFIG_SYS_NAND_USE_FLASH_BBT=y
			+CONFIG_SYS_NAND_ONFI_DETECTION=y
			+CONFIG_OF_LIBFDT_OVERLAY=y
			diff --git a/diff b/diff
			new file mode 100644
			index 00000000..9e1d6d4f
			@@ -3745,10 +3713,10 @@
			++CONFIG_SYS_NAND_ONFI_DETECTION=y
			diff --git a/include/configs/igkboard-imx8mp.h b/include/configs/igkboard-imx8mp.h
			new file mode 100644
			index 00000000..bc2686b2
			index 00000000..16a4cb9b
			--- /dev/null
			+++ b/include/configs/igkboard-imx8mp.h
			@@ -0,0 +1,189 @@
			@@ -0,0 +1,183 @@
			+/* SPDX-License-Identifier: GPL-2.0+ */
			+/*
			+ * Copyright 2019 NXP
			@@ -3912,20 +3880,14 @@
			+#define CFG_SYS_INIT_RAM_SIZE 0x80000
			+
			+
			+/* Totally 6GB DDR */
			+/* Totally 2GB DDR */
			+#define CFG_SYS_SDRAM_BASE 0x40000000
			+#define PHYS_SDRAM 0x40000000
			+#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
			+#define PHYS_SDRAM_2 0x100000000
			+#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK
			+#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */
			+#else
			+#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
			+#endif
			+#define PHYS_SDRAM 0x40000000
			+#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */
			+
			+#define CFG_MXC_UART_BASE UART2_BASE_ADDR
			+
			+#define CFG_SYS_NAND_BASE 0x20000000
			+#define CFG_SYS_NAND_BASE 0x20000000
			+
			+#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK
			+#define CFG_SYS_FSL_USDHC_NUM 1