Patch:IGKBoard-IMX8MP: Add WM8960 audio codec support

guowenxue

2024-07-17 35deaefe2a198508903c5657a0fa7cb2ad60f56d

 bootloader/patches/alientek-imx6ull-v20/uboot-imx-lf-6.1.36-2.1.0.patch

@@ -1,12 +1,25 @@
diff --git a/.gitignore b/.gitignore
index 3a4d056e..1893a337 100644
--- a/.gitignore
+++ b/.gitignore
@@ -30,6 +30,7 @@
 *.order
 *.patch
 *.s
+*.S
 *.su
 *.swp
 *.tab.[ch]
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8b65ac0b..b5259693 100644
index 8b65ac0b..5a613cbc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -942,6 +942,7 @@ dtb-$(CONFIG_MX6ULL) += \
@@ -942,6 +942,8 @@ dtb-$(CONFIG_MX6ULL) += \
    imx6ull-14x14-ddr3-val-gpmi-weim.dtb \
    imx6ull-14x14-ddr3-val-tsc.dtb \
    imx6ull-14x14-evk.dtb \
+   alientek-imx6ull-v20.dtb \
+   alientek-imx6ull-v24.dtb \
    imx6ull-14x14-evk-emmc.dtb \
    imx6ull-14x14-evk-gpmi-weim.dtb \
    imx6ull-9x9-evk.dtb \
@@ -112,10 +125,10 @@
+
diff --git a/arch/arm/dts/alientek-imx6ull.dts b/arch/arm/dts/alientek-imx6ull.dts
new file mode 100644
index 00000000..93a117fc
index 00000000..f63335db
--- /dev/null
+++ b/arch/arm/dts/alientek-imx6ull.dts
@@ -0,0 +1,237 @@
@@ -0,0 +1,259 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Copyright (C) 2022 LingYun IoT System Studio.
@@ -195,6 +208,28 @@
+   status = "okay";
+};
+
+&usbotg1 {
+    dr_mode = "otg";
+    srp-disable;
+    hnp-disable;
+    adp-disable;
+    status = "okay";
+};
+
+&usbotg2 {
+    dr_mode = "host";
+    disable-over-current;
+    status = "okay";
+};
+
+&usbphy1 {
+    tx-d-cal = <0x5>;
+};
+
+&usbphy2 {
+    tx-d-cal = <0x5>;
+};
+
+&usdhc1 {
+   pinctrl-names = "default", "state_100mhz", "state_200mhz";
+   pinctrl-0 = <&pinctrl_usdhc1>;
@@ -255,8 +290,8 @@
+
+   pinctrl_uart1: uart1grp {
+      fsl,pins = <
+         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX    0x1b0b1
+         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX    0x1b0b1
+         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
+         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
+      >;
+   };
+
@@ -276,23 +311,23 @@
+
+   pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+      fsl,pins = <
+         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x170b9
+         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x100b9
+         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x170b9
+         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x170b9
+         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x170b9
+         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x170b9
+         MX6UL_PAD_SD1_CMD__USDHC1_CMD         0x170b9
+         MX6UL_PAD_SD1_CLK__USDHC1_CLK         0x100b9
+         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0      0x170b9
+         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1      0x170b9
+         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2      0x170b9
+         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3      0x170b9
+      >;
+   };
+
+   pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+      fsl,pins = <
+         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x170f9
+         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x100f9
+         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x170f9
+         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x170f9
+         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x170f9
+         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x170f9
+         MX6UL_PAD_SD1_CMD__USDHC1_CMD         0x170f9
+         MX6UL_PAD_SD1_CLK__USDHC1_CLK         0x100f9
+         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0      0x170f9
+         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1      0x170f9
+         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2      0x170f9
+         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3      0x170f9
+      >;
+   };
+
@@ -300,10 +335,10 @@
+      fsl,pins = <
+         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x17059
+         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x17059
+         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0    0x17059
+         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1    0x17059
+         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2    0x17059
+         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3    0x17059
+         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0      0x17059
+         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1      0x17059
+         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2      0x17059
+         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3      0x17059
+      >;
+   };
+
@@ -311,14 +346,14 @@
+      fsl,pins = <
+         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x10069
+         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x17059
+         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0    0x17059
+         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1    0x17059
+         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2    0x17059
+         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3    0x17059
+         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4    0x17059
+         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5    0x17059
+         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6    0x17059
+         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7    0x17059
+         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0      0x17059
+         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1      0x17059
+         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2      0x17059
+         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3      0x17059
+         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4      0x17059
+         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5      0x17059
+         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6      0x17059
+         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7      0x17059
+      >;
+   };
+
@@ -326,14 +361,14 @@
+      fsl,pins = <
+         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x100b9
+         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x170b9
+         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0    0x170b9
+         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1    0x170b9
+         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2    0x170b9
+         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3    0x170b9
+         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4    0x170b9
+         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5    0x170b9
+         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6    0x170b9
+         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7    0x170b9
+         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0      0x170b9
+         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1      0x170b9
+         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2      0x170b9
+         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3      0x170b9
+         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4      0x170b9
+         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5      0x170b9
+         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6      0x170b9
+         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7      0x170b9
+      >;
+   };
+
@@ -341,14 +376,14 @@
+      fsl,pins = <
+         MX6UL_PAD_NAND_RE_B__USDHC2_CLK         0x100f9
+         MX6UL_PAD_NAND_WE_B__USDHC2_CMD         0x170f9
+         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0    0x170f9
+         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1    0x170f9
+         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2    0x170f9
+         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3    0x170f9
+         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4    0x170f9
+         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5    0x170f9
+         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6    0x170f9
+         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7    0x170f9
+         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0      0x170f9
+         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1      0x170f9
+         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2      0x170f9
+         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3      0x170f9
+         MX6UL_PAD_NAND_DATA04__USDHC2_DATA4      0x170f9
+         MX6UL_PAD_NAND_DATA05__USDHC2_DATA5      0x170f9
+         MX6UL_PAD_NAND_DATA06__USDHC2_DATA6      0x170f9
+         MX6UL_PAD_NAND_DATA07__USDHC2_DATA7      0x170f9
+      >;
+   };
+};