build-imxboard.git

			@@ -116,10 +116,10 @@
			+};
			diff --git a/arch/arm/dts/igkboard-imx8mp.dts b/arch/arm/dts/igkboard-imx8mp.dts
			new file mode 100644
			index 00000000..523d5f32
			index 00000000..2cad034a
			--- /dev/null
			+++ b/arch/arm/dts/igkboard-imx8mp.dts
			@@ -0,0 +1,486 @@
			@@ -0,0 +1,469 @@
			+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
			+/*
			+ * Copyright 2023 LingYun IoT System Studio.
			@@ -137,41 +137,30 @@
			+ model = "LingYun IoT Gateway Kits Board based on i.MX8MP";
			+ compatible = "lingyun,igkboard-imx8mp", "fsl,imx8mp";
			+
			+ /* console and bootargs */
			+ chosen {
			+ bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
			+ stdout-path = &uart2;
			+ };
			+ /* console and bootargs */
			+ chosen {
			+ bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
			+ stdout-path = &uart2;
			+ };
			+
			+ /* MT53D512M32D2DS-053 WT:D, 2GB LPDDR4 */
			+ /* MT53D512M32D2DS-053 WT:D, 2GB LPDDR4 */
			+ memory@80000000 {
			+ device_type = "memory";
			+ reg = <0x0 0x80000000 0 0x80000000>;
			+ };
			+
			+ /* SD2_RESET_B for TF card */
			+ reg_usdhc2_vmmc: regulator-usdhc2 {
			+ compatible = "regulator-fixed";
			+ regulator-name = "VSD_3V3";
			+ regulator-min-microvolt = <3300000>;
			+ regulator-max-microvolt = <3300000>;
			+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
			+ enable-active-high;
			+ startup-delay-us = <100>;
			+ off-on-delay-us = <12000>;
			+ };
			+ reg = <0x0 0x80000000 0 0x40000000>;
			+ };
			+
			+ leds {
			+ compatible = "gpio-leds";
			+ pinctrl-names = "default";
			+ pinctrl-0 = <&pinctrl_gpio_led>;
			+ pinctrl-0 = <&pinctrl_leds>;
			+ status = "okay";
			+
			+ sysled {
			+ label = "sysled";
			+ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
			+ default-state = "on";
			+ };
			+ };
			+ };
			+ };
			+};
			+
			+/*+------------------------+
			@@ -218,15 +207,14 @@
			+ +------------------------+*/
			+
			+&usdhc2 {
			+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
			+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
			+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
			+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
			+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
			+ vmmc-supply = <&reg_usdhc2_vmmc>;
			+ bus-width = <4>;
			+ no-1-8-v;
			+ status = "okay";
			+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
			+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
			+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
			+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
			+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
			+ bus-width = <4>;
			+ no-1-8-v;
			+ status = "okay";
			+};
			+
			+/*+------------------------+
			@@ -234,25 +222,25 @@
			+ +------------------------+*/
			+
			+&usb3_phy0 {
			+ fsl,phy-tx-vref-tune = <6>;
			+ fsl,phy-tx-rise-tune = <0>;
			+ fsl,phy-tx-preemp-amp-tune = <3>;
			+ fsl,phy-comp-dis-tune = <7>;
			+ fsl,pcs-tx-deemph-3p5db = <0x21>;
			+ fsl,phy-pcs-tx-swing-full = <0x7f>;
			+ status = "okay";
			+ fsl,phy-tx-vref-tune = <6>;
			+ fsl,phy-tx-rise-tune = <0>;
			+ fsl,phy-tx-preemp-amp-tune = <3>;
			+ fsl,phy-comp-dis-tune = <7>;
			+ fsl,pcs-tx-deemph-3p5db = <0x21>;
			+ fsl,phy-pcs-tx-swing-full = <0x7f>;
			+ status = "okay";
			+};
			+
			+&usb3_0 {
			+ status = "okay";
			+ status = "okay";
			+};
			+
			+&usb_dwc3_0 {
			+ dr_mode = "peripheral";
			+ hnp-disable;
			+ srp-disable;
			+ adp-disable;
			+ status = "okay";
			+ dr_mode = "peripheral";
			+ hnp-disable;
			+ srp-disable;
			+ adp-disable;
			+ status = "okay";
			+};
			+
			+/*+------------------------+
			@@ -261,67 +249,65 @@
			+
			+/* Renesas USB 3.0 Hub uPD720210 */
			+&usb3_phy1 {
			+ fsl,phy-tx-preemp-amp-tune = <2>;
			+ status = "okay";
			+ fsl,phy-tx-preemp-amp-tune = <2>;
			+ status = "okay";
			+};
			+
			+&usb3_1 {
			+ status = "okay";
			+ status = "okay";
			+};
			+
			+&usb_dwc3_1 {
			+ dr_mode = "host";
			+ status = "okay";
			+ dr_mode = "host";
			+ status = "okay";
			+};
			+
			+/*+------------------------+
			+ \| Ethernet \|
			+ +------------------------+*/
			+
			+/* First 1000Mbps Ethernet For TSN on ENET */
			+&eqos {
			+ pinctrl-names = "default";
			+ pinctrl-0 = <&pinctrl_eqos>;
			+ phy-mode = "rgmii-id";
			+ phy-handle = <&ethphy0>;
			+ snps,reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
			+ snps,reset-delays-us = <100000 200000 150000>;
			+ status = "okay";
			+
			+ mdio {
			+ compatible = "snps,dwmac-mdio";
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+ clock-frequency = <5000000>;
			+
			+ ethphy0: ethernet-phy@1 {
			+ ethphy0: ethernet-phy@0 { /* YT8521SH-CA */
			+ compatible = "ethernet-phy-ieee802.3-c22";
			+ reg = <0>;
			+ reg = <0>;
			+ eee-broken-1000t;
			+ };
			+ };
			+ };
			+ };
			+};
			+
			+/* Second 1000Mbps Ethernet on ENET1, test okay */
			+&fec {
			+ pinctrl-names = "default";
			+ pinctrl-0 = <&pinctrl_fec>;
			+ phy-mode = "rgmii-id";
			+ phy-handle = <&ethphy1>;
			+ phy-reset-duration = <200>;
			+ phy-reset-post-delay = <150>;
			+ phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
			+
			+ fsl,magic-packet;
			+ status = "okay";
			+
			+ mdio {
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+ #address-cells = <1>;
			+ #size-cells = <0>;
			+ clock-frequency = <5000000>;
			+
			+ ethphy1: ethernet-phy@1 {
			+ ethphy1: ethernet-phy@0 { /* YT8521SH-CA */
			+ compatible = "ethernet-phy-ieee802.3-c22";
			+ reg = <0>;
			+ reg = <0>;
			+ eee-broken-1000t;
			+ };
			+ };
			+ };
			+ };
			+};
			+
			+/*+------------------------+
			@@ -329,282 +315,279 @@
			+ +------------------------+*/
			+
			+&i2c1 {
			+ clock-frequency = <400000>;
			+ pinctrl-names = "default", "gpio";
			+ pinctrl-0 = <&pinctrl_i2c1>;
			+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
			+ scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
			+ sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
			+ status = "okay";
			+ clock-frequency = <400000>;
			+ pinctrl-names = "default", "gpio";
			+ pinctrl-0 = <&pinctrl_i2c1>;
			+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
			+ scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
			+ sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
			+ status = "okay";
			+
			+ pmic@25 {
			+ compatible = "nxp,pca9450c";
			+ reg = <0x25>;
			+ pinctrl-names = "default";
			+ pinctrl-0 = <&pinctrl_pmic>;
			+ interrupt-parent = <&gpio1>;
			+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
			+ pmic@25 {
			+ compatible = "nxp,pca9450c";
			+ reg = <0x25>;
			+ pinctrl-names = "default";
			+ pinctrl-0 = <&pinctrl_pmic>;
			+ interrupt-parent = <&gpio1>;
			+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
			+
			+ regulators {
			+ buck1: BUCK1 {
			+ regulator-name = "BUCK1";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <2187500>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ regulator-ramp-delay = <3125>;
			+ };
			+ regulators {
			+ buck1: BUCK1 {
			+ regulator-name = "BUCK1";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <2187500>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ regulator-ramp-delay = <3125>;
			+ };
			+
			+ buck2: BUCK2 {
			+ regulator-name = "BUCK2";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <2187500>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ regulator-ramp-delay = <3125>;
			+ nxp,dvs-run-voltage = <950000>;
			+ nxp,dvs-standby-voltage = <850000>;
			+ };
			+ buck2: BUCK2 {
			+ regulator-name = "BUCK2";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <2187500>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ regulator-ramp-delay = <3125>;
			+ nxp,dvs-run-voltage = <950000>;
			+ nxp,dvs-standby-voltage = <850000>;
			+ };
			+
			+ buck4: BUCK4{
			+ regulator-name = "BUCK4";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <3400000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ buck4: BUCK4{
			+ regulator-name = "BUCK4";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <3400000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+
			+ buck5: BUCK5{
			+ regulator-name = "BUCK5";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <3400000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ buck5: BUCK5{
			+ regulator-name = "BUCK5";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <3400000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+
			+ buck6: BUCK6 {
			+ regulator-name = "BUCK6";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <3400000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ buck6: BUCK6 {
			+ regulator-name = "BUCK6";
			+ regulator-min-microvolt = <600000>;
			+ regulator-max-microvolt = <3400000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+
			+ ldo1: LDO1 {
			+ regulator-name = "LDO1";
			+ regulator-min-microvolt = <1600000>;
			+ regulator-max-microvolt = <3300000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ ldo1: LDO1 {
			+ regulator-name = "LDO1";
			+ regulator-min-microvolt = <1600000>;
			+ regulator-max-microvolt = <3300000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+
			+ ldo2: LDO2 {
			+ regulator-name = "LDO2";
			+ regulator-min-microvolt = <800000>;
			+ regulator-max-microvolt = <1150000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ ldo2: LDO2 {
			+ regulator-name = "LDO2";
			+ regulator-min-microvolt = <800000>;
			+ regulator-max-microvolt = <1150000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+
			+ ldo3: LDO3 {
			+ regulator-name = "LDO3";
			+ regulator-min-microvolt = <800000>;
			+ regulator-max-microvolt = <3300000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ ldo3: LDO3 {
			+ regulator-name = "LDO3";
			+ regulator-min-microvolt = <800000>;
			+ regulator-max-microvolt = <3300000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+
			+ ldo4: LDO4 {
			+ regulator-name = "LDO4";
			+ regulator-min-microvolt = <800000>;
			+ regulator-max-microvolt = <3300000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ ldo4: LDO4 {
			+ regulator-name = "LDO4";
			+ regulator-min-microvolt = <800000>;
			+ regulator-max-microvolt = <3300000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+
			+ ldo5: LDO5 {
			+ regulator-name = "LDO5";
			+ regulator-min-microvolt = <1800000>;
			+ regulator-max-microvolt = <3300000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ };
			+ };
			+ ldo5: LDO5 {
			+ regulator-name = "LDO5";
			+ regulator-min-microvolt = <1800000>;
			+ regulator-max-microvolt = <3300000>;
			+ regulator-boot-on;
			+ regulator-always-on;
			+ };
			+ };
			+ };
			+};
			+
			+&iomuxc {
			+ pinctrl-names = "default";
			+ pinctrl-names = "default";
			+
			+ pinctrl_gpio_led: gpioledgrp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
			+ >;
			+ };
			+ pinctrl_leds: ledsgrp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
			+ >;
			+ };
			+
			+ pinctrl_uart2: uart2grp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
			+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
			+ >;
			+ };
			+ pinctrl_wdog: wdoggrp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
			+ >;
			+ };
			+
			+ pinctrl_i2c1: i2c1grp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
			+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
			+ >;
			+ };
			+ pinctrl_uart2: uart2grp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
			+ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
			+ >;
			+ };
			+
			+ pinctrl_i2c1_gpio: i2c1grp-gpio {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
			+ MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
			+ >;
			+ };
			+ pinctrl_i2c1: i2c1grp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
			+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
			+ >;
			+ };
			+
			+ pinctrl_pmic: pmicirq {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
			+ >;
			+ };
			+ pinctrl_i2c1_gpio: i2c1grp-gpio {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3
			+ MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3
			+ >;
			+ };
			+
			+ pinctrl_usdhc2: usdhc2grp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
			+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
			+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
			+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
			+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
			+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
			+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
			+ >;
			+ };
			+ pinctrl_pmic: pmicirq {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
			+ >;
			+ };
			+
			+ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
			+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
			+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
			+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
			+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
			+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
			+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
			+ >;
			+ };
			+ pinctrl_usdhc2_gpio: usdhc2grp-gpio {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
			+ >;
			+ };
			+
			+ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
			+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
			+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
			+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
			+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
			+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
			+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
			+ >;
			+ };
			+ pinctrl_usdhc2: usdhc2grp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
			+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
			+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
			+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
			+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
			+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
			+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
			+ >;
			+ };
			+
			+ pinctrl_usdhc2_gpio: usdhc2grp-gpio {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
			+ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
			+ >;
			+ };
			+ pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
			+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
			+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
			+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
			+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
			+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
			+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
			+ >;
			+ };
			+
			+ pinctrl_usdhc3: usdhc3grp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
			+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
			+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
			+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
			+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
			+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
			+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
			+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
			+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
			+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
			+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
			+ >;
			+ };
			+ pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
			+ MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
			+ MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
			+ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
			+ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
			+ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
			+ MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
			+ >;
			+ };
			+
			+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
			+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
			+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
			+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
			+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
			+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
			+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
			+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
			+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
			+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
			+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
			+ >;
			+ };
			+ pinctrl_usdhc3: usdhc3grp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
			+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
			+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
			+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
			+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
			+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
			+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
			+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
			+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
			+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
			+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
			+ >;
			+ };
			+
			+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
			+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
			+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
			+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
			+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
			+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
			+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
			+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
			+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
			+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
			+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
			+ >;
			+ };
			+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
			+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
			+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
			+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
			+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
			+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
			+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
			+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
			+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
			+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
			+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
			+ >;
			+ };
			+
			+ pinctrl_eqos: eqosgrp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
			+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
			+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
			+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
			+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
			+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
			+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
			+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
			+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
			+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
			+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
			+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
			+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
			+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
			+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
			+ >;
			+ };
			+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
			+ MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
			+ MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
			+ MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
			+ MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
			+ MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
			+ MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
			+ MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
			+ MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
			+ MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
			+ MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
			+ >;
			+ };
			+
			+ pinctrl_fec: fecgrp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
			+ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
			+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
			+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
			+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
			+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
			+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
			+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
			+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
			+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
			+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
			+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
			+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
			+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
			+ MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
			+ >;
			+ };
			+ pinctrl_eqos: eqosgrp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
			+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
			+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
			+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
			+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
			+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
			+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
			+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
			+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
			+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
			+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
			+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
			+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
			+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
			+ >;
			+ };
			+
			+ pinctrl_wdog: wdoggrp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
			+ >;
			+ };
			+ pinctrl_fec: fecgrp {
			+ fsl,pins = <
			+ MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
			+ MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
			+ MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
			+ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
			+ MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
			+ MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
			+ MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
			+ MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
			+ MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
			+ MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
			+ MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
			+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
			+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
			+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
			+ >;
			+ };
			+};
			diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
			index b1240279..e9bcd610 100644
			@@ -3264,10 +3247,10 @@
			+}
			diff --git a/configs/igkboard-imx8mp_defconfig b/configs/igkboard-imx8mp_defconfig
			new file mode 100644
			index 00000000..40c3b634
			index 00000000..bea65054
			--- /dev/null
			+++ b/configs/igkboard-imx8mp_defconfig
			@@ -0,0 +1,199 @@
			@@ -0,0 +1,173 @@
			+CONFIG_ARM=y
			+CONFIG_ARCH_IMX8M=y
			+CONFIG_TEXT_BASE=0x40200000
			@@ -3275,34 +3258,33 @@
			+CONFIG_SPL_GPIO=y
			+CONFIG_SPL_LIBCOMMON_SUPPORT=y
			+CONFIG_SPL_LIBGENERIC_SUPPORT=y
			+CONFIG_IMX_BOOTAUX=y
			+CONFIG_NR_DRAM_BANKS=3
			+CONFIG_ENV_SIZE=0x4000
			+CONFIG_ENV_OFFSET=0x700000
			+CONFIG_ENV_SECT_SIZE=0x10000
			+CONFIG_SYS_MEMTEST_START=0x60000000
			+CONFIG_SYS_MEMTEST_END=0xC0000000
			+CONFIG_SYS_I2C_MXC_I2C1=y
			+CONFIG_SYS_I2C_MXC_I2C2=y
			+CONFIG_SYS_I2C_MXC_I2C3=y
			+CONFIG_DM_GPIO=y
			+CONFIG_DEFAULT_DEVICE_TREE="igkboard-imx8mp"
			+CONFIG_SPL_TEXT_BASE=0x920000
			+CONFIG_TARGET_IGKBOARD_IMX8MP=y
			+CONFIG_SYS_PROMPT="u-boot=> "
			+CONFIG_SPL_SERIAL=y
			+CONFIG_SPL_DRIVERS_MISC=y
			+CONFIG_SPL_STACK=0x96dff0
			+CONFIG_SPL=y
			+CONFIG_IMX_BOOTAUX=y
			+CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
			+CONFIG_SYS_LOAD_ADDR=0x40400000
			+CONFIG_DISTRO_DEFAULTS=y
			+CONFIG_OF_BOARD_FIXUP=y
			+CONFIG_SYS_MEMTEST_START=0x60000000
			+CONFIG_SYS_MEMTEST_END=0xC0000000
			+CONFIG_REMAKE_ELF=y
			+CONFIG_SYS_MONITOR_LEN=524288
			+CONFIG_DEFAULT_DEVICE_TREE="igkboard-imx8mp"
			+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
			+CONFIG_FIT=y
			+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
			+CONFIG_SPL_LOAD_FIT=y
			+# CONFIG_USE_SPL_FIT_GENERATOR is not set
			+CONFIG_REMAKE_ELF=y
			+CONFIG_OF_BOARD_SETUP=y
			+CONFIG_OF_SYSTEM_SETUP=y
			+CONFIG_DISTRO_DEFAULTS=y
			+CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
			+CONFIG_DEFAULT_FDT_FILE="igkboard-imx8mp.dtb"
			+CONFIG_ARCH_MISC_INIT=y
			+CONFIG_BOARD_EARLY_INIT_F=y
			@@ -3314,7 +3296,6 @@
			+CONFIG_SPL_BOARD_INIT=y
			+CONFIG_SPL_BOOTROM_SUPPORT=y
			+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
			+CONFIG_SPL_STACK=0x96dff0
			+CONFIG_SYS_SPL_MALLOC=y
			+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
			+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
			@@ -3327,31 +3308,29 @@
			+CONFIG_SYS_MAXARGS=64
			+CONFIG_SYS_CBSIZE=2048
			+CONFIG_SYS_PBSIZE=2074
			+# CONFIG_BOOTM_NETBSD is not set
			+CONFIG_SYS_BOOTM_LEN=0x2000000
			+CONFIG_NR_DRAM_BANKS=3
			+CONFIG_HUSH_PARSER=y
			+# CONFIG_CMD_EXPORTENV is not set
			+# CONFIG_CMD_IMPORTENV is not set
			+CONFIG_CMD_ERASEENV=y
			+CONFIG_CMD_CRC32=y
			+CONFIG_CRC32_VERIFY=y
			+# CONFIG_BOOTM_NETBSD is not set
			+CONFIG_CMD_MEMTEST=y
			+CONFIG_CMD_CLK=y
			+CONFIG_CMD_FUSE=y
			+CONFIG_CMD_GPIO=y
			+CONFIG_CMD_I2C=y
			+CONFIG_CMD_MMC=y
			+CONFIG_CMD_CACHE=y
			+CONFIG_CMD_REGULATOR=y
			+CONFIG_CMD_MEMTEST=y
			+CONFIG_CMD_EXT2=y
			+CONFIG_CMD_EXT4=y
			+CONFIG_CMD_EXT4_WRITE=y
			+CONFIG_CMD_FAT=y
			+CONFIG_CMD_LED=y
			+CONFIG_CMD_FS_GENERIC=y
			+CONFIG_CMD_NAND_TRIMFFS=y
			+CONFIG_CMD_USB=y
			+CONFIG_CMD_USB_MASS_STORAGE=y
			+CONFIG_CMD_BMP=y
			+CONFIG_CMD_CACHE=y
			+CONFIG_CMD_REGULATOR=y
			+CONFIG_CMD_EXT4_WRITE=y
			+CONFIG_CMD_MTDPARTS=y
			+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
			+CONFIG_MTDPARTS_SKIP_INVALID=y
			+CONFIG_CMD_UBI=y
			+CONFIG_OF_CONTROL=y
			+CONFIG_SPL_OF_CONTROL=y
			+CONFIG_ENV_OVERWRITE=y
			@@ -3360,51 +3339,58 @@
			+CONFIG_ENV_IS_IN_NAND=y
			+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
			+CONFIG_SYS_MMC_ENV_DEV=1
			+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
			+CONFIG_USE_ETHPRIME=y
			+CONFIG_ETHPRIME="eth1"
			+CONFIG_NET_RANDOM_ETHADDR=y
			+CONFIG_USE_IPADDR=y
			+CONFIG_IPADDR="192.168.2.28"
			+CONFIG_USE_NETMASK=y
			+CONFIG_NETMASK="255.255.255.0"
			+CONFIG_USE_SERVERIP=y
			+CONFIG_SERVERIP="192.168.2.2"
			+CONFIG_SPL_DM=y
			+CONFIG_SPL_CLK_COMPOSITE_CCF=y
			+CONFIG_CLK_COMPOSITE_CCF=y
			+CONFIG_SPL_CLK_IMX8MP=y
			+CONFIG_CLK_IMX8MP=y
			+CONFIG_MXC_GPIO=y
			+CONFIG_DM_PCA953X=y
			+CONFIG_FASTBOOT=y
			+CONFIG_USB_FUNCTION_FASTBOOT=y
			+CONFIG_CMD_FASTBOOT=y
			+CONFIG_ANDROID_BOOT_IMAGE=y
			+CONFIG_FASTBOOT_UUU_SUPPORT=y
			+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
			+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
			+CONFIG_FASTBOOT_FLASH=y
			+CONFIG_MXC_GPIO=y
			+CONFIG_DM_PCA953X=y
			+CONFIG_DM_I2C=y
			+CONFIG_SYS_I2C_MXC=y
			+CONFIG_LED=y
			+CONFIG_LED_GPIO=y
			+CONFIG_DM_MMC=y
			+CONFIG_EFI_PARTITION=y
			+CONFIG_SUPPORT_EMMC_BOOT=y
			+CONFIG_MMC_IO_VOLTAGE=y
			+CONFIG_MMC_UHS_SUPPORT=y
			+CONFIG_MMC_HS400_ES_SUPPORT=y
			+CONFIG_MMC_HS400_SUPPORT=y
			+CONFIG_FSL_USDHC=y
			+CONFIG_MTD=y
			+CONFIG_DM_MTD=y
			+CONFIG_MTD_RAW_NAND=y
			+CONFIG_SYS_NAND_USE_FLASH_BBT=y
			+CONFIG_NAND_MXS=y
			+CONFIG_NAND_MXS_DT=y
			+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
			+CONFIG_SYS_NAND_ONFI_DETECTION=y
			+CONFIG_PHY_REALTEK=y
			+CONFIG_DM_ETH_PHY=y
			+CONFIG_PHY_GIGE=y
			+CONFIG_PHY=y
			+CONFIG_PHY_IMX8MQ_USB=y
			+CONFIG_DWC_ETH_QOS=y
			+CONFIG_DWC_ETH_QOS_IMX=y
			+CONFIG_FEC_MXC=y
			+CONFIG_MII=y
			+
			+CONFIG_PHY=y
			+CONFIG_PHY_IMX8MQ_USB=y
			+CONFIG_PINCTRL=y
			+CONFIG_SPL_PINCTRL=y
			+CONFIG_PINCTRL_IMX8M=y
			+CONFIG_POWER_DOMAIN=y
			+CONFIG_IMX8M_POWER_DOMAIN=y
			+CONFIG_IMX8M_BLK_CTRL=y
			+CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
			+CONFIG_DM_PMIC=y
			+CONFIG_SPL_DM_PMIC_PCA9450=y
			@@ -3417,353 +3403,38 @@
			+CONFIG_SYSRESET_PSCI=y
			+CONFIG_DM_THERMAL=y
			+CONFIG_IMX_TMU=y
			+CONFIG_USB_TCPC=n
			+CONFIG_USB=y
			+CONFIG_USB_XHCI_HCD=y
			+CONFIG_USB_XHCI_DWC3=y
			+CONFIG_USB_DWC3=y
			+CONFIG_USB_GADGET=y
			+CONFIG_USB_STORAGE=y
			+CONFIG_DM_USB=y
			+
			+CONFIG_OF_LIBFDT_OVERLAY=y
			+CONFIG_USB_GADGET_MANUFACTURER="FSL"
			+CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
			+CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
			+CONFIG_USB_GADGET_DOWNLOAD=y
			+CONFIG_USB_XHCI_HCD=y
			+CONFIG_USB_XHCI_IMX8M=y
			+CONFIG_USB_XHCI_DWC3=y
			+CONFIG_USB_DWC3=y
			+CONFIG_USB_DWC3_GADGET=y
			+
			+CONFIG_OF_BOARD_FIXUP=y
			+CONFIG_OF_BOARD_SETUP=y
			+
			+CONFIG_IMX8M_BLK_CTRL=y
			+CONFIG_VIDEO_IMX_LCDIFV3=y
			+CONFIG_VIDEO_IMX_SEC_DSI=y
			+CONFIG_VIDEO=y
			+CONFIG_VIDEO_LOGO=y
			+CONFIG_SYS_WHITE_ON_BLACK=y
			+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
			+CONFIG_VIDEO_IMX_SEC_DSI=y
			+CONFIG_VIDEO_IMX_LCDIFV3=y
			+CONFIG_SPLASH_SCREEN=y
			+CONFIG_SPLASH_SCREEN_ALIGN=y
			+CONFIG_BMP_16BPP=y
			+CONFIG_BMP_24BPP=y
			+CONFIG_BMP_32BPP=y
			+CONFIG_VIDEO_LOGO=y
			+CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
			+CONFIG_VIDEO_ADV7535=y
			+CONFIG_SYS_WHITE_ON_BLACK=y
			+CONFIG_SPLASH_SCREEN=y
			+CONFIG_SPLASH_SCREEN_ALIGN=y
			+CONFIG_CMD_BMP=y
			+
			+CONFIG_CMD_NAND=y
			+CONFIG_CMD_UBI=y
			+CONFIG_CMD_NAND_TRIMFFS=y
			+CONFIG_MTD_RAW_NAND=y
			+CONFIG_MTD=y
			+CONFIG_DM_MTD=y
			+CONFIG_CMD_MTDPARTS=y
			+CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
			+CONFIG_MTDPARTS_SKIP_INVALID=y
			+CONFIG_NAND=y
			+CONFIG_NAND_MXS=y
			+CONFIG_NAND_MXS_DT=y
			+CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
			+CONFIG_SYS_NAND_USE_FLASH_BBT=y
			+CONFIG_SYS_NAND_ONFI_DETECTION=y
			diff --git a/diff b/diff
			new file mode 100644
			index 00000000..9e1d6d4f
			--- /dev/null
			+++ b/diff
			@@ -0,0 +1,282 @@
			+--- igkboard-imx8mp_defconfig 2023-12-13 21:17:05.014287682 +0800
			++++ configs/igkboard-imx8mp_defconfig 2023-12-13 21:16:32.053328305 +0800
			+@@ -1,178 +1,199 @@
			+ CONFIG_ARM=y
			+ CONFIG_ARCH_IMX8M=y
			+-CONFIG_SYS_TEXT_BASE=0x40200000
			++CONFIG_TEXT_BASE=0x40200000
			+ CONFIG_SYS_MALLOC_LEN=0x2000000
			+-CONFIG_SYS_MALLOC_F_LEN=0x10000
			+ CONFIG_SPL_GPIO=y
			+ CONFIG_SPL_LIBCOMMON_SUPPORT=y
			+ CONFIG_SPL_LIBGENERIC_SUPPORT=y
			+-CONFIG_NR_DRAM_BANKS=3
			+-CONFIG_SYS_MEMTEST_START=0x60000000
			+-CONFIG_SYS_MEMTEST_END=0xC0000000
			++CONFIG_IMX_BOOTAUX=y
			+ CONFIG_ENV_SIZE=0x4000
			+-CONFIG_ENV_OFFSET=0x400000
			++CONFIG_ENV_OFFSET=0x700000
			+ CONFIG_ENV_SECT_SIZE=0x10000
			++CONFIG_SYS_MEMTEST_START=0x60000000
			++CONFIG_SYS_MEMTEST_END=0xC0000000
			++CONFIG_SYS_I2C_MXC_I2C1=y
			++CONFIG_SYS_I2C_MXC_I2C2=y
			++CONFIG_SYS_I2C_MXC_I2C3=y
			+ CONFIG_DM_GPIO=y
			+-CONFIG_DEFAULT_DEVICE_TREE="igkboard-imx8mp"
			+ CONFIG_SPL_TEXT_BASE=0x920000
			+ CONFIG_TARGET_IGKBOARD_IMX8MP=y
			++CONFIG_SYS_PROMPT="u-boot=> "
			+ CONFIG_SPL_SERIAL=y
			+ CONFIG_SPL_DRIVERS_MISC=y
			+ CONFIG_SPL=y
			+ CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
			+-CONFIG_OF_BOARD_FIXUP=y
			+-CONFIG_DISTRO_DEFAULTS=y
			+ CONFIG_SYS_LOAD_ADDR=0x40400000
			++CONFIG_DISTRO_DEFAULTS=y
			++CONFIG_SYS_MONITOR_LEN=524288
			++CONFIG_DEFAULT_DEVICE_TREE="igkboard-imx8mp"
			++CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
			+ CONFIG_FIT=y
			+ CONFIG_FIT_EXTERNAL_OFFSET=0x3000
			+-CONFIG_FIT_SIGNATURE=y
			+ CONFIG_SPL_LOAD_FIT=y
			+-CONFIG_LEGACY_IMAGE_FORMAT=y
			+-CONFIG_OF_BOARD_SETUP=y
			++# CONFIG_USE_SPL_FIT_GENERATOR is not set
			++CONFIG_REMAKE_ELF=y
			+ CONFIG_OF_SYSTEM_SETUP=y
			+-CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd"
			+ CONFIG_DEFAULT_FDT_FILE="igkboard-imx8mp.dtb"
			++CONFIG_ARCH_MISC_INIT=y
			+ CONFIG_BOARD_EARLY_INIT_F=y
			+ CONFIG_BOARD_LATE_INIT=y
			++CONFIG_SPL_MAX_SIZE=0x26000
			++CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
			++CONFIG_SPL_BSS_START_ADDR=0x96e000
			++CONFIG_SPL_BSS_MAX_SIZE=0x2000
			+ CONFIG_SPL_BOARD_INIT=y
			+ CONFIG_SPL_BOOTROM_SUPPORT=y
			+-CONFIG_SPL_SEPARATE_BSS=y
			++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
			++CONFIG_SPL_STACK=0x96dff0
			++CONFIG_SYS_SPL_MALLOC=y
			++CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
			++CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
			++CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
			+ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
			+ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
			+ CONFIG_SPL_I2C=y
			+ CONFIG_SPL_POWER=y
			+ CONFIG_SPL_WATCHDOG=y
			+-CONFIG_SYS_PROMPT="[u-boot@igkboard]# "
			+-# CONFIG_BOOTM_NETBSD is not set
			++CONFIG_SYS_MAXARGS=64
			++CONFIG_SYS_CBSIZE=2048
			++CONFIG_SYS_PBSIZE=2074
			++CONFIG_SYS_BOOTM_LEN=0x2000000
			++CONFIG_NR_DRAM_BANKS=3
			++CONFIG_HUSH_PARSER=y
			+ # CONFIG_CMD_EXPORTENV is not set
			+ # CONFIG_CMD_IMPORTENV is not set
			+ CONFIG_CMD_ERASEENV=y
			+-CONFIG_CMD_NVEDIT_EFI=y
			++CONFIG_CMD_CRC32=y
			+ CONFIG_CRC32_VERIFY=y
			+-CONFIG_CMD_MEMTEST=y
			++# CONFIG_BOOTM_NETBSD is not set
			+ CONFIG_CMD_CLK=y
			+-CONFIG_CMD_DFU=y
			+ CONFIG_CMD_FUSE=y
			+ CONFIG_CMD_GPIO=y
			+ CONFIG_CMD_I2C=y
			+ CONFIG_CMD_MMC=y
			+-CONFIG_CMD_OPTEE_RPMB=y
			+-CONFIG_CMD_POWEROFF=y
			+-CONFIG_CMD_USB=y
			+-CONFIG_CMD_USB_MASS_STORAGE=y
			+-CONFIG_CMD_SNTP=y
			+-CONFIG_CMD_BMP=y
			+ CONFIG_CMD_CACHE=y
			+-CONFIG_CMD_EFIDEBUG=y
			+-CONFIG_CMD_RTC=y
			+-CONFIG_CMD_TIME=y
			+-CONFIG_CMD_GETTIME=y
			+-CONFIG_CMD_TIMER=y
			+ CONFIG_CMD_REGULATOR=y
			++CONFIG_CMD_MEMTEST=y
			++CONFIG_CMD_EXT2=y
			++CONFIG_CMD_EXT4=y
			+ CONFIG_CMD_EXT4_WRITE=y
			++CONFIG_CMD_FAT=y
			++CONFIG_CMD_LED=y
			++CONFIG_CMD_FS_GENERIC=y
			++CONFIG_CMD_USB=y
			++CONFIG_CMD_USB_MASS_STORAGE=y
			+ CONFIG_OF_CONTROL=y
			+ CONFIG_SPL_OF_CONTROL=y
			+ CONFIG_ENV_OVERWRITE=y
			+ CONFIG_ENV_IS_NOWHERE=y
			+ CONFIG_ENV_IS_IN_MMC=y
			+-CONFIG_ENV_IS_IN_SPI_FLASH=y
			++CONFIG_ENV_IS_IN_NAND=y
			+ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
			+ CONFIG_SYS_MMC_ENV_DEV=1
			+ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
			+-CONFIG_NET_RANDOM_ETHADDR=y
			++CONFIG_USE_ETHPRIME=y
			++CONFIG_ETHPRIME="eth1"
			+ CONFIG_SPL_DM=y
			+-CONFIG_REGMAP=y
			+-CONFIG_SYSCON=y
			+ CONFIG_SPL_CLK_COMPOSITE_CCF=y
			+ CONFIG_CLK_COMPOSITE_CCF=y
			+ CONFIG_SPL_CLK_IMX8MP=y
			+ CONFIG_CLK_IMX8MP=y
			+-CONFIG_DFU_TFTP=y
			+-CONFIG_DFU_MMC=y
			+-CONFIG_DFU_RAM=y
			++CONFIG_MXC_GPIO=y
			++CONFIG_DM_PCA953X=y
			++CONFIG_FASTBOOT=y
			+ CONFIG_USB_FUNCTION_FASTBOOT=y
			+-CONFIG_UDP_FUNCTION_FASTBOOT=y
			++CONFIG_CMD_FASTBOOT=y
			++CONFIG_ANDROID_BOOT_IMAGE=y
			++CONFIG_FASTBOOT_UUU_SUPPORT=y
			+ CONFIG_FASTBOOT_BUF_ADDR=0x42800000
			+ CONFIG_FASTBOOT_BUF_SIZE=0x40000000
			+ CONFIG_FASTBOOT_FLASH=y
			+-CONFIG_MXC_GPIO=y
			+-CONFIG_DM_PCA953X=y
			+ CONFIG_DM_I2C=y
			++CONFIG_SYS_I2C_MXC=y
			+ CONFIG_LED=y
			+ CONFIG_LED_GPIO=y
			+-CONFIG_SUPPORT_EMMC_RPMB=y
			++CONFIG_DM_MMC=y
			++CONFIG_EFI_PARTITION=y
			+ CONFIG_SUPPORT_EMMC_BOOT=y
			+ CONFIG_MMC_IO_VOLTAGE=y
			+ CONFIG_MMC_UHS_SUPPORT=y
			+ CONFIG_MMC_HS400_ES_SUPPORT=y
			+ CONFIG_MMC_HS400_SUPPORT=y
			+ CONFIG_FSL_USDHC=y
			+-CONFIG_DM_SPI_FLASH=y
			+-CONFIG_SF_DEFAULT_MODE=0
			+-CONFIG_SF_DEFAULT_SPEED=40000000
			+-CONFIG_SPI_FLASH_BAR=y
			+-CONFIG_SPI_FLASH_STMICRO=y
			+ CONFIG_PHY_REALTEK=y
			+-CONFIG_DM_ETH=y
			+ CONFIG_DM_ETH_PHY=y
			+ CONFIG_PHY_GIGE=y
			++CONFIG_PHY=y
			++CONFIG_PHY_IMX8MQ_USB=y
			+ CONFIG_DWC_ETH_QOS=y
			+ CONFIG_DWC_ETH_QOS_IMX=y
			+ CONFIG_FEC_MXC=y
			+ CONFIG_MII=y
			+-CONFIG_PHY=y
			+-CONFIG_PHY_IMX8MQ_USB=y
			++
			+ CONFIG_PINCTRL=y
			+ CONFIG_SPL_PINCTRL=y
			+ CONFIG_PINCTRL_IMX8M=y
			++CONFIG_POWER_DOMAIN=y
			++CONFIG_IMX8M_POWER_DOMAIN=y
			++CONFIG_IMX8MP_HSIOMIX_BLKCTRL=y
			+ CONFIG_DM_PMIC=y
			+ CONFIG_SPL_DM_PMIC_PCA9450=y
			+ CONFIG_DM_REGULATOR=y
			+ CONFIG_DM_REGULATOR_FIXED=y
			+ CONFIG_DM_REGULATOR_GPIO=y
			+-CONFIG_DM_RTC=y
			+-CONFIG_RTC_EMULATION=y
			++CONFIG_DM_SERIAL=y
			+ CONFIG_MXC_UART=y
			+-CONFIG_SPI=y
			+-CONFIG_DM_SPI=y
			+-CONFIG_NXP_FSPI=y
			+ CONFIG_SYSRESET=y
			+ CONFIG_SYSRESET_PSCI=y
			+-CONFIG_TEE=y
			+-CONFIG_OPTEE=y
			+ CONFIG_DM_THERMAL=y
			+ CONFIG_IMX_TMU=y
			++CONFIG_USB_TCPC=n
			+ CONFIG_USB=y
			+-CONFIG_USB_XHCI_HCD=y
			+-CONFIG_USB_XHCI_DWC3=y
			+-CONFIG_USB_DWC3=y
			+ CONFIG_USB_GADGET=y
			++CONFIG_USB_STORAGE=y
			++CONFIG_DM_USB=y
			++
			++CONFIG_OF_LIBFDT_OVERLAY=y
			+ CONFIG_USB_GADGET_MANUFACTURER="FSL"
			+ CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9
			+ CONFIG_USB_GADGET_PRODUCT_NUM=0x0152
			+-CONFIG_DM_VIDEO=y
			+-CONFIG_VIDEO_LOGO=y
			+-CONFIG_SYS_WHITE_ON_BLACK=y
			+-CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
			+-CONFIG_VIDEO_IMX_SEC_DSI=y
			++CONFIG_USB_GADGET_DOWNLOAD=y
			++CONFIG_USB_XHCI_HCD=y
			++CONFIG_USB_XHCI_IMX8M=y
			++CONFIG_USB_XHCI_DWC3=y
			++CONFIG_USB_DWC3=y
			++CONFIG_USB_DWC3_GADGET=y
			++
			++CONFIG_OF_BOARD_FIXUP=y
			++CONFIG_OF_BOARD_SETUP=y
			++
			++CONFIG_IMX8M_BLK_CTRL=y
			+ CONFIG_VIDEO_IMX_LCDIFV3=y
			+-CONFIG_SPLASH_SCREEN=y
			+-CONFIG_SPLASH_SCREEN_ALIGN=y
			++CONFIG_VIDEO_IMX_SEC_DSI=y
			++CONFIG_VIDEO=y
			+ CONFIG_BMP_16BPP=y
			+ CONFIG_BMP_24BPP=y
			+ CONFIG_BMP_32BPP=y
			++CONFIG_VIDEO_LOGO=y
			++CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y
			+ CONFIG_VIDEO_ADV7535=y
			+-CONFIG_SPL_RSA=y
			+-CONFIG_SHA384=y
			+-CONFIG_LZO=y
			+-CONFIG_BZIP2=y
			+-CONFIG_OF_LIBFDT_OVERLAY=y
			+-CONFIG_EFI_MM_COMM_TEE=y
			+-CONFIG_EFI_VAR_BUF_SIZE=139264
			+-CONFIG_EFI_SET_TIME=y
			+-CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
			+-CONFIG_EFI_CAPSULE_ON_DISK=y
			+-CONFIG_EFI_IGNORE_OSINDICATIONS=y
			+-CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
			+-CONFIG_EFI_CAPSULE_AUTHENTICATE=y
			+-CONFIG_EFI_SECURE_BOOT=y
			++CONFIG_SYS_WHITE_ON_BLACK=y
			++CONFIG_SPLASH_SCREEN=y
			++CONFIG_SPLASH_SCREEN_ALIGN=y
			++CONFIG_CMD_BMP=y
			++
			++CONFIG_CMD_NAND=y
			++CONFIG_CMD_UBI=y
			++CONFIG_CMD_NAND_TRIMFFS=y
			++CONFIG_MTD_RAW_NAND=y
			++CONFIG_MTD=y
			++CONFIG_DM_MTD=y
			++CONFIG_CMD_MTDPARTS=y
			++CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
			++CONFIG_MTDPARTS_SKIP_INVALID=y
			++CONFIG_NAND=y
			++CONFIG_NAND_MXS=y
			++CONFIG_NAND_MXS_DT=y
			++CONFIG_NAND_MXS_USE_MINIMUM_ECC=y
			++CONFIG_SYS_NAND_USE_FLASH_BBT=y
			++CONFIG_SYS_NAND_ONFI_DETECTION=y
			+CONFIG_OF_LIBFDT_OVERLAY=y
			diff --git a/include/configs/igkboard-imx8mp.h b/include/configs/igkboard-imx8mp.h
			new file mode 100644
			index 00000000..16a4cb9b
			index 00000000..17d20930
			--- /dev/null
			+++ b/include/configs/igkboard-imx8mp.h
			@@ -0,0 +1,183 @@
			@@ -0,0 +1,81 @@
			+/* SPDX-License-Identifier: GPL-2.0+ */
			+/*
			+ * Copyright 2019 NXP
			+ * Copyright (C) 2023 LingYun IoT System Studio
			+ *
			+ * Configuration settings for LingYun IGKBoard(IoT Gateway Kits Board) based on i.MX8MP
			+ */
			+
			+#ifndef __IGKBOARD_IMX8MP_H
			@@ -3777,42 +3448,9 @@
			+#define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
			+
			+#if defined(CONFIG_CMD_NET)
			+#define CFG_FEC_MXC_PHYADDR 1
			+
			+#define PHY_ANEG_TIMEOUT 20000
			+
			+#define CFG_FEC_MXC_PHYADDR -1
			+#define PHY_ANEG_TIMEOUT 20000
			+#endif
			+
			+#ifdef CONFIG_DISTRO_DEFAULTS
			+#define BOOT_TARGET_DEVICES(func) \
			+ func(USB, usb, 0) \
			+ func(MMC, mmc, 1) \
			+ func(MMC, mmc, 2)
			+
			+#include <config_distro_bootcmd.h>
			+#else
			+#define BOOTENV
			+#endif
			+
			+#define JH_ROOT_DTB "imx8mp-evk-revb4-root.dtb"
			+
			+#define JAILHOUSE_ENV \
			+ "jh_clk= \0 " \
			+ "jh_root_dtb=" JH_ROOT_DTB "\0" \
			+ "jh_mmcboot=setenv fdtfile ${jh_root_dtb};" \
			+ "setenv jh_clk clk_ignore_unused mem=1920MB; " \
			+ "if run loadimage; then " \
			+ "run mmcboot; " \
			+ "else run jh_netboot; fi; \0" \
			+ "jh_netboot=setenv fdtfile ${jh_root_dtb}; setenv jh_clk clk_ignore_unused mem=1920MB; run netboot; \0 "
			+
			+#define SR_IR_V2_COMMAND \
			+ "nodes=/busfreq /power-domains /soc@0/caam-sm@100000 /soc@0/bus@30000000/caam_secvio /soc@0/bus@30000000/caam-snvs@30370000 /soc@0/bus@30800000/flexspi_nand@30bb0000 /soc@0/bus@32c00000/mipi_dsi@32e60000 /soc@0/bus@32c00000/lcd-controller@32e80000 /soc@0/bus@32c00000/blk-ctl@32ec0000 /soc@0/bus@30800000/i2c@30a20000/pca9450@25 /soc@0/bus@30800000/i2c@30a30000/adv7535@3d /soc@0/bus@30800000/i2c@30a30000/tcpc@50 /wdt-reboot /mcu_rdc /soc@0/bus@30800000/ethernet@30bf0000 /dsi-host /rm67199_panel /cbtl04gp /binman /vpu_g1@38300000 /vpu_g2@38310000 /vpu_vc8000e@38320000 /vpu_v4l2 /gpu3d@38000000 /gpu2d@38008000 /vipsi@38500000 /mix_gpu_ml \0" \
			+ "sr_ir_v2_cmd=cp.b ${fdtcontroladdr} ${fdt_addr_r} 0x10000;"\
			+ "fdt addr ${fdt_addr_r};"\
			+ "fdt set /soc@0/usb@32f10100/usb@38100000 compatible snps,dwc3;" \
			+ "fdt set /soc@0/usb@32f10108/usb@38200000 compatible snps,dwc3;" \
			+ "for i in ${nodes}; do fdt rm ${i}; done \0"
			+
			+#define CFG_MFG_ENV_SETTINGS \
			+ CFG_MFG_ENV_SETTINGS_DEFAULT \
			@@ -3822,101 +3460,36 @@
			+ "sd_dev=1\0"
			+
			+
			+#ifdef CONFIG_NAND_BOOT
			+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)"
			+#endif
			+
			+/* Initial environment variables */
			+#if defined(CONFIG_NAND_BOOT)
			+#define CFG_EXTRA_ENV_SETTINGS \
			+ CFG_MFG_ENV_SETTINGS \
			+ "splashimage=0x50000000\0" \
			+ "fdt_addr_r=0x43000000\0" \
			+ "fdt_addr=0x43000000\0" \
			+ "fdt_high=0xffffffffffffffff\0" \
			+ "mtdparts=" MFG_NAND_PARTITION "\0" \
			+ "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
			+ "bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=nandrootfs " \
			+ "root=ubi0:nandrootfs rootfstype=ubifs " \
			+ MFG_NAND_PARTITION \
			+ "\0" \
			+ "bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\
			+ "nand read ${fdt_addr_r} 0x7000000 0x100000;"\
			+ "booti ${loadaddr} - ${fdt_addr_r}"
			+
			+#else
			+#define CFG_EXTRA_ENV_SETTINGS \
			+ CFG_MFG_ENV_SETTINGS \
			+ JAILHOUSE_ENV \
			+ SR_IR_V2_COMMAND \
			+ BOOTENV \
			+ "prepare_mcore=setenv mcore_clk clk-imx8mp.mcore_booted;\0" \
			+ "scriptaddr=0x43500000\0" \
			+ "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
			+ "bsp_script=boot.scr\0" \
			+ "image=Image\0" \
			+ "splashimage=0x50000000\0" \
			+ "console=ttymxc1,115200\0" \
			+ "fdt_addr_r=0x43000000\0" \
			+ "fdt_addr=0x43000000\0" \
			+ "boot_fdt=try\0" \
			+ "fdt_high=0xffffffffffffffff\0" \
			+ "boot_fit=no\0" \
			+ "board=igkboard-imx8mp\0" \
			+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
			+ "bootm_size=0x10000000\0" \
			+ "mmcautodetect=yes\0" \
			+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
			+ "mmcpart=1\0" \
			+ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
			+ "mmcautodetect=yes\0" \
			+ "mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot}\0 " \
			+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \
			+ "bootscript=echo Running bootscript from mmc ...; " \
			+ "source\0" \
			+ "mmcroot=/dev/mmcblk${mmcdev}p2 rootwait rw\0" \
			+ "mmcargs=setenv bootargs console=${console} root=${mmcroot} net.ifnames=0\0" \
			+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
			+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
			+ "mmcboot=echo Booting from mmc ...; " \
			+ "run mmcargs; " \
			+ "if test ${boot_fit} = yes \|\| test ${boot_fit} = try; then " \
			+ "bootm ${loadaddr}; " \
			+ "else " \
			+ "if run loadfdt; then " \
			+ "booti ${loadaddr} - ${fdt_addr_r}; " \
			+ "else " \
			+ "echo WARN: Cannot load the DT; " \
			+ "fi; " \
			+ "fi;\0" \
			+ "netargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} " \
			+ "root=/dev/nfs " \
			+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
			+ "netboot=echo Booting from net ...; " \
			+ "run netargs; " \
			+ "if test ${ip_dyn} = yes; then " \
			+ "setenv get_cmd dhcp; " \
			+ "else " \
			+ "setenv get_cmd tftp; " \
			+ "fi; " \
			+ "${get_cmd} ${loadaddr} ${image}; " \
			+ "if test ${boot_fit} = yes \|\| test ${boot_fit} = try; then " \
			+ "bootm ${loadaddr}; " \
			+ "else " \
			+ "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
			+ "booti ${loadaddr} - ${fdt_addr_r}; " \
			+ "else " \
			+ "echo WARN: Cannot load the DT; " \
			+ "fi; " \
			+ "fi;\0" \
			+ "bsp_bootcmd=echo Running BSP bootcmd ...; " \
			+ "mmc dev ${mmcdev}; if mmc rescan; then " \
			+ "if run loadbootscript; then " \
			+ "run bootscript; " \
			+ "else " \
			+ "if run loadimage; then " \
			+ "run mmcboot; " \
			+ "else run netboot; " \
			+ "fi; " \
			+ "fi; " \
			+ "fi;"
			+#endif
			+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile}\0" \
			+ "bootos=booti ${loadaddr} - ${fdt_addr}\0" \
			+ "mmcboot=mmc dev ${mmcdev};run mmcargs;run loadimage;run loadfdt;run bootos\0" \
			+ "netboot=tftp $loadaddr $image; tftp $fdt_addr ${fdtfile}; run mmcargs; run bootos\0" \
			+ "bbl=tftp ${loadaddr} u-boot-${board}.imx && mmc dev ${mmcdev} 1 && mmc write ${loadaddr} 2 0x800\0" \
			+ "bdtb=tftp $fdt_addr $fdtfile && fatwrite mmc 1:1 $fdt_addr $fdtfile $filesize\0" \
			+ "bker=tftp $loadaddr $image&& fatwrite mmc 1:1 $loadaddr $image $filesize\0" \
			+ "bsys=run bdtb && run bker\0"
			+
			+#undef CONFIG_BOOTCOMMAND
			+#define CONFIG_BOOTCOMMAND "mmc dev ${mmcdev}; mmc rescan; run mmcargs; run loadimage; run loadfdt; run bootos"
			+
			+/* Link Definitions */
			+
			@@ -3931,13 +3504,7 @@
			+
			+#define CFG_MXC_UART_BASE UART2_BASE_ADDR
			+
			+#define CFG_SYS_NAND_BASE 0x20000000
			+
			+#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK
			+#define CFG_SYS_FSL_USDHC_NUM 1
			+#else
			+#define CFG_SYS_FSL_USDHC_NUM 2
			+#endif
			+
			+#ifdef CONFIG_ANDROID_SUPPORT
			+#include "imx8mp_evk_android.h"