build-imxboard.git

			@@ -113,10 +113,10 @@
			+
			diff --git a/arch/arm/boot/dts/alientek-imx6ull.dts b/arch/arm/boot/dts/alientek-imx6ull.dts
			new file mode 100644
			index 000000000..93a117fc0
			index 000000000..f63335dbc
			--- /dev/null
			+++ b/arch/arm/boot/dts/alientek-imx6ull.dts
			@@ -0,0 +1,237 @@
			@@ -0,0 +1,259 @@
			+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
			+//
			+// Copyright (C) 2022 LingYun IoT System Studio.
			@@ -196,6 +196,28 @@
			+ status = "okay";
			+};
			+
			+&usbotg1 {
			+ dr_mode = "otg";
			+ srp-disable;
			+ hnp-disable;
			+ adp-disable;
			+ status = "okay";
			+};
			+
			+&usbotg2 {
			+ dr_mode = "host";
			+ disable-over-current;
			+ status = "okay";
			+};
			+
			+&usbphy1 {
			+ tx-d-cal = <0x5>;
			+};
			+
			+&usbphy2 {
			+ tx-d-cal = <0x5>;
			+};
			+
			+&usdhc1 {
			+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
			+ pinctrl-0 = <&pinctrl_usdhc1>;
			@@ -256,8 +278,8 @@
			+
			+ pinctrl_uart1: uart1grp {
			+ fsl,pins = <
			+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
			+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
			+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
			+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
			+ >;
			+ };
			+
			@@ -277,23 +299,23 @@
			+
			+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
			+ fsl,pins = <
			+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
			+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
			+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
			+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
			+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
			+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
			+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
			+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
			+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
			+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
			+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
			+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
			+ >;
			+ };
			+
			+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
			+ fsl,pins = <
			+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
			+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
			+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
			+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
			+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
			+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
			+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
			+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
			+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
			+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
			+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
			+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
			+ >;
			+ };
			+
			@@ -301,10 +323,10 @@
			+ fsl,pins = <
			+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
			+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
			+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
			+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
			+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
			+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
			+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
			+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
			+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
			+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
			+ >;
			+ };
			+
			@@ -312,14 +334,14 @@
			+ fsl,pins = <
			+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
			+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
			+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
			+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
			+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
			+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
			+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
			+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
			+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
			+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
			+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
			+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
			+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
			+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
			+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
			+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
			+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
			+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
			+ >;
			+ };
			+
			@@ -327,14 +349,14 @@
			+ fsl,pins = <
			+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
			+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
			+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
			+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
			+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
			+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
			+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
			+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
			+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
			+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
			+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
			+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
			+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
			+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
			+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
			+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
			+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
			+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
			+ >;
			+ };
			+
			@@ -342,14 +364,14 @@
			+ fsl,pins = <
			+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
			+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
			+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
			+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
			+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
			+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
			+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
			+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
			+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
			+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
			+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
			+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
			+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
			+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
			+ MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
			+ MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
			+ MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
			+ MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
			+ >;
			+ };
			+};