| | |
| | | +dtb-$(CONFIG_ARCH_MXC) += igkboard-imx8mp.dtb |
| | | diff --git a/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts b/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts |
| | | new file mode 100644 |
| | | index 000000000..ce38a5b4a |
| | | index 000000000..31490ac6a |
| | | --- /dev/null |
| | | +++ b/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts |
| | | @@ -0,0 +1,782 @@ |
| | | @@ -0,0 +1,991 @@ |
| | | +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| | | +/* |
| | | +/* |
| | | + * Device Tree Source for LingYun IGKBoard(IoT Gateway Kits Board) - imx8mp |
| | | + * Copyright 2023 LingYun IoT System Studio. |
| | | + */ |
| | |
| | | + "LINPUT3", "Mic Jack", |
| | | + "Mic Jack", "MICB"; |
| | | + }; |
| | | + |
| | | + lvds0_panel { |
| | | + compatible = "boe,ev121wxm-n10-1850"; |
| | | + backlight = <&lvds_backlight>; |
| | | + |
| | | + port { |
| | | + panel_lvds_in: endpoint { |
| | | + remote-endpoint = <&lvds_out>; |
| | | + }; |
| | | + }; |
| | | + }; |
| | | + |
| | | + lvds_backlight: lvds_backlight { |
| | | + compatible = "pwm-backlight"; |
| | | + pwms = <&pwm2 0 100000 0>; |
| | | + status = "okay"; |
| | | + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; |
| | | + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 |
| | | + 10 11 12 13 14 15 16 17 18 19 |
| | | + 20 21 22 23 24 25 26 27 28 29 |
| | | + 30 31 32 33 34 35 36 37 38 39 |
| | | + 40 41 42 43 44 45 46 47 48 49 |
| | | + 50 51 52 53 54 55 56 57 58 59 |
| | | + 60 61 62 63 64 65 66 67 68 69 |
| | | + 70 71 72 73 74 75 76 77 78 79 |
| | | + 80 81 82 83 84 85 86 87 88 89 |
| | | + 90 91 92 93 94 95 96 97 98 99 |
| | | + 100>; |
| | | + default-brightness-level = <80>; |
| | | + }; |
| | | + |
| | | +}; |
| | | + |
| | | +/*+------------------------+ |
| | |
| | | + wlf,shared-lrclk; |
| | | + }; |
| | | + |
| | | + ov5640_0: ov5640_mipi@3c { |
| | | + compatible = "ovti,ov5640"; |
| | | + reg = <0x3c>; |
| | | + pinctrl-names = "default"; |
| | | + pinctrl-0 = <&pinctrl_csi0>; |
| | | + clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; |
| | | + clock-names = "xclk"; |
| | | + assigned-clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO2>; |
| | | + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; |
| | | + assigned-clock-rates = <24000000>; |
| | | + csi_id = <0>; |
| | | + powerdown-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; |
| | | + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; |
| | | + mclk = <24000000>; |
| | | + mclk_source = <0>; |
| | | + mipi_csi; |
| | | + status = "okay"; |
| | | + |
| | | + port { |
| | | + ov5640_mipi_0_ep: endpoint { |
| | | + remote-endpoint = <&mipi_csi0_ep>; |
| | | + data-lanes = <1 2>; |
| | | + clock-lanes = <0>; |
| | | + }; |
| | | + }; |
| | | + }; |
| | | + |
| | | + ms1112@4a { |
| | | + compatible = "ms,ms1112"; |
| | | + reg = <0x4a>; |
| | |
| | | +}; |
| | | + |
| | | +/*+------------------------+ |
| | | + | MIPI-CSI OV5640 Camera | |
| | | + +------------------------+*/ |
| | | + |
| | | +&mipi_csi_0 { |
| | | + #address-cells = <1>; |
| | | + #size-cells = <0>; |
| | | + status = "okay"; |
| | | + |
| | | + port@0 { |
| | | + reg = <0>; |
| | | + mipi_csi0_ep: endpoint { |
| | | + remote-endpoint = <&ov5640_mipi_0_ep>; |
| | | + data-lanes = <2>; |
| | | + csis-hs-settle = <13>; |
| | | + csis-clk-settle = <2>; |
| | | + csis-wclk; |
| | | + }; |
| | | + }; |
| | | +}; |
| | | + |
| | | +&vpu_g1 { |
| | | + status = "okay"; |
| | | +}; |
| | | + |
| | | +&vpu_g2 { |
| | | + status = "okay"; |
| | | +}; |
| | | + |
| | | +&vpu_vc8000e { |
| | | + status = "okay"; |
| | | +}; |
| | | + |
| | | +&vpu_v4l2 { |
| | | + status = "okay"; |
| | | +}; |
| | | + |
| | | +&cameradev { |
| | | + status = "okay"; |
| | | +}; |
| | | + |
| | | +&isi_0 { |
| | | + status = "okay"; |
| | | + |
| | | + cap_device { |
| | | + status = "okay"; |
| | | + }; |
| | | + |
| | | + m2m_device { |
| | | + status = "okay"; |
| | | + }; |
| | | +}; |
| | | + |
| | | +/*+------------------------+ |
| | | + | HDMI Display | |
| | | + +------------------------+*/ |
| | | + |
| | | +&irqsteer_hdmi { |
| | | + status = "okay"; |
| | | +}; |
| | | + |
| | | +&hdmi_blk_ctrl { |
| | | + status = "okay"; |
| | | +}; |
| | | + |
| | | +&hdmi_pavi { |
| | | + status = "okay"; |
| | | +}; |
| | | + |
| | | +&hdmi { |
| | | + status = "okay"; |
| | | +}; |
| | | + |
| | | +&hdmiphy { |
| | | + status = "okay"; |
| | | +}; |
| | | + |
| | | +&lcdif3 { |
| | | + status = "okay"; |
| | | + |
| | | + thres-low = <1 2>; /* (FIFO * 1 / 2) */ |
| | | + thres-high = <3 4>; /* (FIFO * 3 / 4) */ |
| | | +}; |
| | | + |
| | | +/*+------------------------+ |
| | | + | LVDS Display | |
| | | + +------------------------+*/ |
| | | + |
| | | +&pwm2 { |
| | | + pinctrl-names = "default"; |
| | | + pinctrl-0 = <&pinctrl_pwm2>; |
| | | + status = "okay"; |
| | | +}; |
| | | + |
| | | +&lcdif2 { |
| | | + status = "okay"; |
| | | +}; |
| | | + |
| | | +&ldb { |
| | | + status = "okay"; |
| | | + |
| | | + lvds-channel@0 { |
| | | + fsl,data-mapping = "spwg"; |
| | | + fsl,data-width = <24>; |
| | | + status = "okay"; |
| | | + |
| | | + /delete-node/ port@1; |
| | | + port@1 { |
| | | + reg = <1>; |
| | | + |
| | | + lvds_out: endpoint { |
| | | + remote-endpoint = <&panel_lvds_in>; |
| | | + }; |
| | | + }; |
| | | + }; |
| | | +}; |
| | | + |
| | | +&ldb_phy { |
| | | + status = "okay"; |
| | | +}; |
| | | + |
| | | +/*+------------------------+ |
| | | + | CAN/RS485 interface | |
| | | + +------------------------+*/ |
| | | + |
| | | +/* RS485 */ |
| | | +&uart3 { |
| | | + pinctrl-names = "default"; |
| | |
| | | + |
| | | +&iomuxc { |
| | | + pinctrl-names = "default"; |
| | | + pinctrl-0 = <&pinctrl_hog>; |
| | | + |
| | | + pinctrl_hog: hoggrp { |
| | | + fsl,pins = < |
| | | + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2 |
| | | + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2 |
| | | + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010 |
| | | + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000010 |
| | | + /* |
| | | + * M.2 pin20 & pin21 need to be set to 11 for 88W9098 to select the |
| | | + * default Reference Clock Frequency |
| | | + */ |
| | | + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4 |
| | | + >; |
| | | + }; |
| | | + |
| | | + pinctrl_wdog: wdoggrp { |
| | | + fsl,pins = < |
| | |
| | | + >; |
| | | + }; |
| | | + |
| | | + pinctrl_pwm1: pwm1grp { |
| | | + pinctrl_pwm1: pwm1grp { /* Buzzer */ |
| | | + fsl,pins = < |
| | | + MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT 0x116 |
| | | + >; |
| | | + }; |
| | | + |
| | | + pinctrl_pwm3: pwm3grp { |
| | | + pinctrl_pwm2: pwm2grp { /* LVDS */ |
| | | + fsl,pins = < |
| | | + MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x116 |
| | | + >; |
| | | + }; |
| | | + |
| | | + pinctrl_pwm3: pwm3grp { /* RPi#40Pin and MikroBUS */ |
| | | + fsl,pins = < |
| | | + MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x116 |
| | | + >; |
| | | + }; |
| | | + |
| | | + pinctrl_uart1: uart1grp { |
| | | + pinctrl_uart1: uart1grp { /* RPi#40Pin and MikroBUS */ |
| | | + fsl,pins = < |
| | | + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 |
| | | + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 |
| | | + >; |
| | | + }; |
| | | + |
| | | + pinctrl_uart2: uart2grp { |
| | | + pinctrl_uart2: uart2grp { /* Console */ |
| | | + fsl,pins = < |
| | | + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 |
| | | + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 |
| | | + >; |
| | | + }; |
| | | + |
| | | + pinctrl_uart3: uart3grp { |
| | | + pinctrl_uart3: uart3grp { /* RS485 */ |
| | | + fsl,pins = < |
| | | + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x82 |
| | | + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x82 |
| | |
| | | + >; |
| | | + }; |
| | | + |
| | | + pinctrl_ecspi2: ecspi2grp { |
| | | + pinctrl_ecspi2: ecspi2grp { /* RPi#40Pin and MikroBUS */ |
| | | + fsl,pins = < |
| | | + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 |
| | | + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 |
| | |
| | | + >; |
| | | + }; |
| | | + |
| | | + pinctrl_i2c1: i2c1grp { |
| | | + pinctrl_i2c1: i2c1grp { /* PMIC */ |
| | | + fsl,pins = < |
| | | + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 |
| | | + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 |
| | | + >; |
| | | + }; |
| | | + |
| | | + pinctrl_i2c2: i2c2grp { |
| | | + pinctrl_i2c2: i2c2grp { /* WM8960, MS1112, ISL1208 */ |
| | | + fsl,pins = < |
| | | + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 |
| | | + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 |
| | | + >; |
| | | + }; |
| | | + |
| | | + pinctrl_i2c5: i2c5grp { |
| | | + pinctrl_i2c5: i2c5grp { /* RPi#40Pin and MikroBUS, HDC1080, AT24C32 */ |
| | | + fsl,pins = < |
| | | + MX8MP_IOMUXC_SD1_CMD__I2C5_SDA 0x400001c2 |
| | | + MX8MP_IOMUXC_SD1_CLK__I2C5_SCL 0x400001c2 |
| | |
| | | + >; |
| | | + }; |
| | | + |
| | | + pinctrl_csi0: csi0_grp { |
| | | + fsl,pins = < |
| | | + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x10 /* PWN */ |
| | | + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x10 /* RST */ |
| | | + MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x50 /* MCLK */ |
| | | + >; |
| | | + }; |
| | | + |
| | | + pinctrl_pmic: pmicirq { |
| | | + fsl,pins = < |
| | | + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 |