Patch:IGKBoard-IMX8MP: Add HDMI support

guowenxue

2024-07-18 b8d02950d8c50611c2784c7a40e0b3003acf8d49

Patch:IGKBoard-IMX8MP: Add HDMI support

Signed-off-by: guowenxue <guowenxue@gmail.com>

 kernel/patches/igkboard-imx8mp/linux-imx-lf-6.1.36-2.1.0.patch

@@ -10,10 +10,10 @@
+dtb-$(CONFIG_ARCH_MXC) += igkboard-imx8mp.dtb
diff --git a/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts b/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts
new file mode 100644
index 000000000..ce38a5b4a
index 000000000..016d92023
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts
@@ -0,0 +1,782 @@
@@ -0,0 +1,829 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/* 
+ * Device Tree Source for LingYun IGKBoard(IoT Gateway Kits Board) - imx8mp
@@ -361,8 +361,40 @@
+};
+
+/*+------------------------+
+  |      HDMI Display      |
+  +------------------------+*/
+
+&irqsteer_hdmi {
+    status = "okay";
+};
+
+&hdmi_blk_ctrl {
+    status = "okay";
+};
+
+&hdmi_pavi {
+    status = "okay";
+};
+
+&hdmi {
+    status = "okay";
+};
+
+&hdmiphy {
+    status = "okay";
+};
+
+&lcdif3 {
+    status = "okay";
+
+    thres-low  = <1 2>;     /* (FIFO * 1 / 2) */
+    thres-high = <3 4>;     /* (FIFO * 3 / 4) */
+};
+
+/*+------------------------+
+  |  CAN/RS485 interface   |
+  +------------------------+*/
+
+/* RS485 */
+&uart3 {
+    pinctrl-names = "default";
@@ -549,6 +581,21 @@
+
+&iomuxc {
+    pinctrl-names = "default";
+    pinctrl-0 = <&pinctrl_hog>;
+
+    pinctrl_hog: hoggrp {
+        fsl,pins = <
+            MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL                 0x400001c2
+            MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA                 0x400001c2
+            MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD                     0x40000010
+            MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC                     0x40000010
+            /*
+             * M.2 pin20 & pin21 need to be set to 11 for 88W9098 to select the
+             * default Reference Clock Frequency
+             */
+            MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09                          0x1c4
+        >;
+    };
+
+    pinctrl_wdog: wdoggrp {
+        fsl,pins = <