From 2334ec8814e13e011b70a192541a65d70e63243a Mon Sep 17 00:00:00 2001
From: guowenxue <guowenxue@gmail.com>
Date: Fri, 26 Jan 2024 18:04:53 +0800
Subject: [PATCH] Build:Image:IGKBoard-All:Update build output system image name
---
kernel/patches/igkboard-imx8mp/linux-imx-lf-6.1.36-2.1.0.patch | 86 +++++++++++++++++++++++++++++++++++-------
1 files changed, 71 insertions(+), 15 deletions(-)
diff --git a/kernel/patches/igkboard-imx8mp/linux-imx-lf-6.1.36-2.1.0.patch b/kernel/patches/igkboard-imx8mp/linux-imx-lf-6.1.36-2.1.0.patch
index c6646b7..8ae32ed 100644
--- a/kernel/patches/igkboard-imx8mp/linux-imx-lf-6.1.36-2.1.0.patch
+++ b/kernel/patches/igkboard-imx8mp/linux-imx-lf-6.1.36-2.1.0.patch
@@ -10,12 +10,13 @@
+dtb-$(CONFIG_ARCH_MXC) += igkboard-imx8mp.dtb
diff --git a/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts b/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts
new file mode 100644
-index 000000000..cddc94704
+index 000000000..02267ac4d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/igkboard-imx8mp.dts
-@@ -0,0 +1,475 @@
+@@ -0,0 +1,531 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
++/*
++ * Device Tree Source for LingYun IGKBoard(IoT Gateway Kits Board) - imx8mp
+ * Copyright 2023 LingYun IoT System Studio.
+ */
+
@@ -31,16 +32,15 @@
+ model = "LingYun IoT Gateway Kits Board based on i.MX8MP";
+ compatible = "lingyun,igkboard-imx8mp", "fsl,imx8mp";
+
-+ /* console and bootargs */
++ /* console */
+ chosen {
-+ bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200";
+ stdout-path = &uart2;
+ };
+
+ /* MT53D512M32D2DS-053 WT:D, 2GB LPDDR4 */
+ memory@80000000 {
+ device_type = "memory";
-+ reg = <0x0 0x80000000 0 0x80000000>;
++ reg = <0x0 0x80000000 0 0x40000000>;
+ };
+
+ leds {
@@ -53,6 +53,56 @@
+ label = "sysled";
+ gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
++ linux,default-trigger = "heartbeat";
++ };
++
++ ledred {
++ label = "redled";
++ gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ ledgreen {
++ label = "greenled";
++ gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++
++ ledblue {
++ label = "blueled";
++ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
++ default-state = "on";
++ };
++ };
++
++ keys {
++ compatible = "gpio-keys";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_keys>;
++ status = "okay";
++
++ key1 {
++ label = "K1";
++ gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
++ linux,code = <BTN_1>;
++ };
++
++ key2 {
++ label = "K2";
++ gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
++ linux,code = <BTN_2>;
++ };
++
++ key3 {
++ label = "K3";
++ gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
++ linux,code = <BTN_3>;
++ };
++
++ key4 {
++ label = "K4";
++ gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
++ linux,code = <BTN_4>;
+ };
+ };
+};
@@ -166,14 +216,13 @@
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
-+ snps,reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
-+ snps,reset-delays-us = <100000 200000 150000>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
++ clock-frequency = <5000000>;
+
+ ethphy0: ethernet-phy@0 { /* YT8521SH-CA */
+ compatible = "ethernet-phy-ieee802.3-c22";
@@ -183,22 +232,19 @@
+ };
+};
+
-+/* Second 1000Mbps Ethernet on ENET1 */
++/* Second 1000Mbps Ethernet on ENET1, test okay */
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy1>;
-+ phy-reset-duration = <200>;
-+ phy-reset-post-delay = <150>;
-+ phy-reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
-+
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
++ clock-frequency = <5000000>;
+
+ ethphy1: ethernet-phy@0 { /* YT8521SH-CA */
+ compatible = "ethernet-phy-ieee802.3-c22";
@@ -323,6 +369,18 @@
+ pinctrl_leds: ledsgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
++ MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x140
++ MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x140
++ MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140
++ >;
++ };
++
++ pinctrl_keys: keysgrp {
++ fsl,pins = <
++ MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x140
++ MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140
++ MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x140
++ MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x140
+ >;
+ };
+
@@ -465,7 +523,6 @@
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
-+ MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x22
+ >;
+ };
+
@@ -485,7 +542,6 @@
+ MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
+ MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
+ MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
-+ MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x11
+ >;
+ };
+};
--
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